JP2002280558A - Complementary type switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To offset the variation of the output potential of a complementary type switch comprising n-type and p-type transistors, without increasing a circuit area. SOLUTION: In the complementary type switch 10, its n-type and p-type transistors 11, 12 are connected in parallel with each other, and gate controlling voltages having different polarities from each other are applied at the same time to gates of the respective transistors. On the upper side of the complementary type switch 10, via an insulation film, an auxiliary circuit 20, wherein the p-type and n-type transistors 21, 22 are connected in parallel with each other, and input and output sides of both transistors are short-circuited, and further, the gate controlling voltages having the different polarities from each other are applied at the same time to the gates of the respective transistors, is formed, and the output side of the switch 10 is connected to the input side of the auxiliary circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor product such as an array substrate of a color liquid crystal display device or a semiconductor IC.
In particular, it relates to a complementary switch circuit used for a digital / analog conversion circuit and the like.

[0002]

2. Description of the Related Art Conventionally, an electronic circuit constituted by a field effect transistor is incorporated in an array substrate or a semiconductor product such as a semiconductor IC of a color liquid crystal display device using a polycrystalline silicon thin film transistor. As switches in this electronic circuit, complementary switches (CMOs) in which n-type and p-type field-effect transistors are combined in parallel are used.
S switch) is often used.

This complementary switch can surely transmit all potentials from a high level to a low level from the input side to the output side as compared with a switch using only an n-type or p-type transistor, and consumes less power. Is frequently used because of its low content.

However, the relationship between the potential change of the gate electrode of the n-type transistor of the complementary switch and the output voltage is shown in FIG.
As shown in the figure, after the switch is turned on and the desired signal potential (input potential Va) is written to the output side, the moment the switch is turned off (the moment the gate voltage Vg of the n-type transistor goes from high level to low level) ) Changes the potential of the electrode of the transistor, redistribution of the charge stored between the transistor capacitance and the load capacitance occurs, and the potential written to the load capacitance on the output side becomes the output waveform ( As shown in (Vout), there is a problem that it fluctuates by ΔV. However, in FIG. 4, ΔV = Vo
ut−Va.

Although FIG. 4 shows an n-type transistor, the same applies to a p-type transistor, and the output potential fluctuates similarly, but the fluctuation is opposite between the n-type and p-type transistors.
Therefore, the fluctuation is canceled at the input potential of the center, but the fluctuation remains at the output potential at other input potentials.

In order to solve this, a complementary switch circuit shown in FIG. 5 is known. The complementary switch circuit shown in FIG. 5 includes a complementary switch 1 and an auxiliary circuit 2 connected to the output side of the complementary switch 1 and canceling a change in the output potential of the complementary switch 1. Complementary switch 1 is an n-type and p-type transistor 1
1, 12 are connected in parallel. Auxiliary circuit 2
Is formed by connecting p-type and n-type transistors 21 and 22 in parallel, and forms p-type and n-type transistors 21 and 22
The source S and the drain D are short-circuited. The gate G of the n-type transistor 11 and the gate G of the p-type transistor 21 are commonly connected by the wiring 3, and p
The gate G of the n-type transistor 12 and the gate G of the n-type transistor 22 are commonly connected by the wiring 4. Vin is input with the common drain D of the complementary switch 1 as an input, Vout is output with the common source S of the complementary switch 1 as an output, and this is input to the common source S of the auxiliary circuit 2 and the load capacitance C Is entered.

Hereinafter, n-type and p-type transistors 11, 1
2 is appropriately called transistors 11 and 12, and p-type and n-type transistors 21 and 22 are appropriately
It is called 22.

In the above configuration, when the transistors 11 and 12 of the complementary switch 1 are turned on, the transistors 21 and 22 of the auxiliary circuit 2 are turned off, and when the transistors 11 and 12 of the complementary switch 1 are turned off, the auxiliary circuit is turned off. The two transistors 21 and 22 are turned on.

Here, Cgsn (ON) is the capacitance between the gate and the source when the n-type transistor 11 is on, Cgs
p (ON) is the gate-source capacitance when the p-type transistor 12 is on, and Cgsno (ON) is the gate-source capacitance, Cgs when the n-type transistor 22 is on.
po (ON) is the gate-source capacitance when the p-type transistor 21 is on, and Cgsn (OFF) is the gate-source capacitance, Cg when the n-type transistor 11 is off.
sp (OFF) is the capacitance between the gate and the source when the p-type transistor 12 is off, and Cgsno (OFF) is the capacitance between the gate and the source when the n-type transistor 22 is off.
Assuming that Cgspo (OFF) is the gate-source capacitance when the p-type transistor 21 is off, C is the load capacitance, V is the input voltage, Vdd is the voltage when the gate of each transistor is at the high level, and FIG. Output voltage fluctuation Δ described
V satisfies the following equation (1).

ΔV = Vout−Vin = Vout−Va = {α (Vdd−Va) + βVa} / {C + Cgsn (OFF) + Cgsp (OFF) + 2Cgspo (ON) + 2Cgsno (ON)} (1) where α = Cgsp (OFF) -2Cgspo (OF
F) + 2Cgsno (ON) −Cgsn (ON), β =
Cgsp (ON) -2Cgspo (ON) + 2Cgsn
o (OFF) -Cgsn (OFF).

FIG. 6 is a characteristic diagram for explaining the capacitance characteristics of the n-type and p-type transistors of the complementary switch circuit shown in FIG. The p-type transistor has characteristics as shown in FIG. 6A. When the gate voltage is turned off at a high level, Cgsp (OFF) is reduced. On the other hand, an n-type transistor has characteristics as shown in FIG.
When the gate voltage goes low and turns off, Cgs
n (OFF) becomes small.

Therefore, when the n-type transistor 11 of the complementary switch 1 is turned off, the p-type transistor 21 of the auxiliary circuit 2 is turned on.
The capacitance between the gate and the source, which is reduced by
Since it becomes large at 1, the redistribution of electric charge that occurs when the n-type transistor 11 is turned off is canceled by turning on the transistor 21. A similar phenomenon occurs between the p-type transistor 12 and the n-type transistor 22. As a result, the potential change ΔV on the output side of the complementary switch 1 becomes zero.

FIG. 7 is a plan view showing a layout example of the conventional complementary switch circuit shown in FIG. In the figure, the portion surrounded by a broken line is the n-type transistor 1 shown in FIG.
1, p-type transistor 12, p-type transistor 2
1, an n-type transistor 22; the drains D of the n-type transistor 11 and the p-type transistor 12
1 form an input section of the complementary switch 1. On the other hand, the source S and the drain D of the p-type transistor 21 and the n-type transistor 22 of the auxiliary circuit 2 are commonly connected by a wiring 62, and the source S and the drain D are short-circuited. The output side of the complementary switch 1 and the input side of the auxiliary circuit 2 are connected via an electrode plate 63 forming a load capacitance C. According to the above configuration, by connecting the auxiliary circuit 2 to the output side of the complementary switch 1, it is possible to cancel the fluctuation of the output potential that occurs at the moment when the complementary switch 1 is turned off.

[0014]

However, when the auxiliary circuit 2 described in the prior art is provided in all the complementary switches 1 in the circuit, as shown in FIG. There is a problem that the area is doubled. In recent years, technology has been developed that incorporates a circuit for driving liquid crystal on a glass substrate and a circuit for converting digital and analog signals on the glass substrate by utilizing the driving capability of low-temperature polysilicon thin film transistors. It is desirable that the area (frame) other than the screen occupied by the above-described peripheral circuit in the area be as small as possible. However, since circuits for converting digital signals to analog signals are provided with a large number of switches, the area occupied by the circuit is doubled if the method described in the related art is used, and as a result, the frame This causes a problem that the occupied area increases.

An object of the present invention is to provide a complementary switch circuit in which a change in output potential of a complementary switch can be canceled by an auxiliary circuit without increasing a circuit area.

[0016]

In order to achieve the above object, a feature of the present invention is to connect a first n-type transistor and a first p-type transistor in parallel, and A complementary switch for simultaneously turning on / off both transistors by simultaneously applying gate control voltages having different polarities to the gate, a second n-type transistor and a second p-type transistor are connected in parallel, and both transistors are connected in parallel. And an auxiliary circuit for short-circuiting the input side and the output side of the complementary switch, and simultaneously applying a gate control voltage having a different polarity to the gate of each transistor to turn on / off both transistors at the same time. When an auxiliary circuit is connected, when the complementary switch is turned on, both transistors constituting the auxiliary circuit are turned off, and when the complementary switch is turned off, In complementary switch circuit to turn on both transistors constituting the serial auxiliary circuit is to form the auxiliary circuit through an insulating film on the complementary switch.

According to a second aspect of the present invention, in the first aspect, both transistors forming the complementary switch are formed by a top gate type field effect transistor, and both transistors forming the auxiliary circuit are formed by a bottom gate type electrolytic transistor. Effect transistor, the second p-type transistor is formed on the first n-type transistor via an insulating film, and both transistors have a common gate electrode, and the first p-type transistor is The second n-type transistor is formed on the transistor via a green film, and the gate electrodes of both transistors are common.

According to a third aspect of the present invention, in the second aspect, the area of the high-concentration ion-doped region of each of the field-effect transistors constituting the complementary switch is equal to the high-concentration ion-doping region of each of the field-effect transistors constituting the auxiliary circuit. It is characterized by being wider than the area of the doped region.

According to a fourth aspect of the present invention, in the second or third aspect, a source electrode and a drain electrode of both field effect transistors constituting the complementary switch, and a source electrode and a drain electrode of both field effect transistors constituting the auxiliary circuit are provided. The present invention is characterized in that the drain electrode and other wirings constituting the circuit are all formed in a single layer.

According to a fifth aspect of the present invention, in the second, third or fourth aspect, the thickness of the gate insulating film of each of the field effect transistors constituting the complementary switch is the same as that of each of the field effect transistors constituting the auxiliary circuit. Gate insulating film thickness 2
It is characterized by being twice.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a configuration of a complementary switch circuit according to the present embodiment. However, the same parts as those in the conventional example will be described using the same reference numerals. Further, when a specific region of a certain portion is indicated or the same portion is referred to by another name, or for convenience of explanation, reference numerals with parentheses are used as appropriate.

In this embodiment, an auxiliary circuit 20 formed by transistors 21 and 22 is disposed above a complementary switch 10 formed by transistors 11 and 12 via an insulating film (not shown). (In FIG. 1, the complementary switch 10 and the auxiliary circuit 20 are overlapped, and therefore, no reference numeral is given).

The drain D11 of the transistor 11 and the drain D12 of the transistor 12 are connected by a wiring 101 to form an input section 100 of the complementary switch 10. Source S11 of transistor 11 and transistor 1
The two sources S12 are connected by a wiring 102 to form an output section (output electrode 50) of the complementary switch 10. Source S21 of transistor 21 and transistor 2
2 sources S22 are connected by an I-type wiring 103,
The input section (input electrode 49) of the auxiliary circuit 20 is formed. Since the wiring 103 is connected to the wiring 102 in the wiring area 121, the output section (50) of the complementary switch 10
And the input section (49) of the auxiliary circuit 20 are connected. Note that the wiring 103 is formed by the input electrode 49, the output electrode 48, and the wiring region 120.

The drain D21 of the transistor 21 and the drain D22 of the transistor 22 are connected by a wiring 103 to form an output section (output electrode 48) of the auxiliary circuit 20, and the wiring section 120 forms an input section of the auxiliary circuit 20. (49) and the output section (48) are connected. The output section (50) of the complementary switch 10 is connected to the electrode plate 104 forming the load capacitance C, and the electrode plate 105 is a counter electrode of the load capacitance C on the ground side.

Next, the structure of the complementary switch circuit according to the present embodiment will be described in more detail with reference to FIG.

The transistor 11 forming the complementary switch 10 includes a lower semiconductor 201 and an intermediate gate electrode 205.
And the transistor 12 is connected to the lower semiconductor 20.
2 and an intermediate gate electrode 206.

On the other hand, the transistor 21 forming the auxiliary circuit 20 is composed of an upper semiconductor 203 and an intermediate gate electrode 205.
And the transistor 22 is formed by the upper semiconductor 20.
4 and an intermediate gate electrode 206. In the semiconductor 201, regions of a drain D11 and a source S11 are formed on both sides of the active layer.

FIG. 3 is a sectional view showing the structure of the electrical connection wiring between the lower complementary switch 10 and the upper auxiliary circuit 20 of the complementary switch circuit having the above structure. The complementary switch 10 is formed by the lower transistor 11 and the transistor 12, and the auxiliary circuit 20 is formed by the upper transistor 21 and the transistor 22. The drain D11 of the transistor 11 and the drain D12 of the transistor 12 are connected to the wiring 101 through contact holes 301 and 304. Source S of transistor 11
11 and the source S12 of the transistor 12 are connected to the wiring 102 through the contact holes 302 and 303 to form an output portion. The drain D2 of the transistor 21
1 and the source S21 are connected to the wiring 103 shown in FIG. The drain D22 and the source S22 of the transistor 22 are connected to the wiring 103 through contact holes 307 and 308. The aluminum wiring region of this example has a structure in which there is only one layer at the top.

According to the configuration of this embodiment, the auxiliary circuit 20
Is disposed above the complementary switch 10 via an insulating film (not shown). This has the advantage that not only can the auxiliary circuit 20 cancel out the variation in output potential that occurs when the complementary switch 10 is turned off, but also the area occupied by the circuit does not need to be increased.

However, if the transistors are simply formed on the upper and lower sides, the number of manufacturing steps increases too much. Therefore, as shown in FIGS. 2 and 3, the gates of the transistors constituting the complementary switch 10 and the transistors constituting the auxiliary circuit 20 are made common. That is, the transistors 11 and 12 are of a top gate type, and the transistors 21 and
22 is a bottom gate type.

As shown in FIGS. 2 and 3, the n-type transistor 22 of the auxiliary circuit 20 is formed above the p-type transistor 12 of the complementary switch 10.
The p-type transistor 21 is formed above the n-type transistor 11 of the complementary switch 10. Then, the gates G12 and G22 of the top-gate p-type transistor 12 and the bottom-gate n-type transistor 22 and the gates of the top-gate n-type transistor 11 and the bottom-gate p-type transistor 21 G11 and 21 can be common. By sharing the gates in this way, it is possible to eliminate the wiring structure for connecting the gates, which was conventionally required, and to prevent an increase in the number of manufacturing steps.

The contact holes 301 and 30 for the source electrode and the drain electrode of the transistors 11 and 12 are provided.
2 and 303 and 304, and contact holes 305 and 3 of the source and drain electrodes of the transistors 21 and 22.
S11 and S12 regions, which are high-concentration ion-doped regions of the transistors 11 and 12 located on the lower side, in order to form the wirings 101 and 102 extending from the respective contact holes in the same layer by making the semiconductor devices 06 and 307 and 308 independent. Is larger in size than the high-concentration ion-doped regions S21 and S22 of the transistors 21 and 22 located on the upper side. That is, the semiconductors 201 and 202 are replaced with the semiconductor 20.
It is longer than 3,204.

By the way, since all the charges accumulated in the load capacitance C and the capacitance of the transistor shown in the circuit diagram of FIG. 5 shown in the conventional example are stored before and after the complementary switch 10 is turned off, the switch is turned off. The variation ΔV of the output potential that occurs at this time is expressed by the equation (1) as described above. Assuming that the capacitance when the transistor is turned off is almost zero, the following relationship needs to be established in order for this ΔV to be 0 for an arbitrary input voltage.

2Cgsno (ON) = Cgsn (ON) 2Cgspo (ON) = Cgsp (ON) (2) By the way, the capacitance when the transistor is on is represented as follows. Cgs (ON) = εrWL / (2Tox) (3) where εr is the dielectric constant of the oxide film, W is the channel width, L is the channel length, and Tox is the oxide film thickness.

Since the transistors 11 and 21 or the transistors 12 and 22 have a common gate electrode, W and L are the same for all transistors. Therefore, in order to realize the expression (2), the gate oxide film thickness of the transistors 21 and 22 should be twice as large as the gate oxide film thickness of the transistors 11 and 12. For this reason, in FIG. 3, the gates G11 and G21 are
It is not at the center between 1 and 203 but near the semiconductor 201 side. Similarly, the gates G21 and G22 are not at the center of the semiconductors 202 and 204, but are closer to the semiconductor 202 side.

Next, assuming that a circuit composed of the above-described complementary switch circuit of the present embodiment is incorporated on an array substrate of a liquid crystal display of a low-temperature polysilicon thin film transistor, a specific example of the manufacturing method will be described below. I do.

In FIG. 3, an insulating film (112) and semiconductors (active layers) 201 and 20 are formed on a glass substrate (110).
An amorphous silicon film 2 is continuously formed in a vacuum using PE-CVD (plasma chemical vapor deposition). Thereafter, heat treatment is performed at 500 ° C. to remove hydrogen existing in the insulating film. Here, the insulating film is a silicon oxide film and has a thickness of 500 °, and the amorphous silicon film to be the active layer has a thickness of 500 °. Next, ELA
An amorphous silicon film to be an active layer is polycrystallized by (excimer laser annealing) method. Next, the polycrystalline silicon film is processed by a CDE (Chemical Dry Etching) method using a mixed gas of CF ₄ and O ₂ to obtain island-shaped regions (201, 202) as shown in FIG.

Next, an oxide film to be a gate insulating film (51) is formed by PE-CVD (plasma chemical vapor deposition). The thickness is 1000 °. After that, a region other than the portions S11 and D11 that are to be the high-concentration ion-doped regions of the n-type transistor 11 is masked with a resist, and PH3 serving as a donor is implanted by ion doping. The injection condition is an acceleration voltage of 10 Ke.
V, the dose IE15 / cm ² .

Next, after the resist is removed, a portion (S
12, D12) are masked with a resist, and diborane (B
₂ H ₆ ). The injection condition is an acceleration voltage of 10K.
eV and the dose IE15 / cm ² . Next, after removing the resist, the gates G11 and G12 and the gate G1 are removed.
2, 22, MoW to be the load capacitance electrode (lower side) 104
(Molybdenum tungsten alloy) is formed by sputtering, and then processed by CDE. The thickness of MoW is 2500 °. Thereafter, activation annealing is performed at 500 ° C. At this time, the impurities are activated and the drains D11 and D12 and the source S11 of the thin film transistor are formed.
S12 is formed.

Next, the gate insulating films (52) of the transistors 21 and 22 are formed at a film forming temperature of 350 ° C. The film thickness is 2000 ° which is twice the thickness of the gate insulating films of the transistors 11 and 12. Next, an amorphous silicon film to be an active layer (202, 203) of the transistors 21, 22 constituting the auxiliary circuit 20 is formed in a vacuum using a PE-CVD (plasma chemical vapor deposition) method.

Thereafter, a heat treatment is performed at 500 ° C. to remove hydrogen existing in the amorphous silicon film. here,
The thickness of the amorphous silicon film is 500 °.

Next, an amorphous silicon film to be an active layer is polycrystallized by an ELA (excimer laser annealing) method.

Next, the polycrystalline silicon film is formed of CF ₄ and Ο.
By working in a CDE (chemical dry etching) method using a _second gaseous mixture, obtaining a region (203, 204) Island-shaped as shown in FIG.

However, the size of each of the transistors 11, 1
2, the regions S21, S22, D21, D22 corresponding to the source and the drain are S11, S1
2, smaller than D11 and D12.

Thereafter, the high concentration of the p-type transistor 21 is
Except for portions (S21, D21) to be ion-doped regions
Mask the area with resist and use ion doping method
To inject PH3 as a donor. The injection conditions were
Pressure 10 KeV, Dose IE15 / cm²It is. Sa
Further, after the resist is removed, the p-type transistor 21 is removed.
(S21, D2)
Mask the area other than 1) with a resist,
Diborane (B₂H ₆)
After the implantation, the resist is removed. Injection conditions are accelerated
Voltage 10 KeV, dose amount IEI5 / cm²It is.

Next, an interlayer insulating film (53) is formed at a deposition temperature of 40.
Film formation at 0 ° C. At this time, the impurities of the transistors 21 and 22 are activated and the drain D2 of the thin film transistor is activated.
1, D22 and sources S21, S22 are formed.

The interlayer insulating film is an oxide film, and has a thickness of 5000 °. Next, contact holes 301, 302, 303 and 304 are opened using hydrofluoric acid.
After forming a load capacitor C composed of 1 and electrodes and wirings using a sputtering method, processing is performed using a wet method. The thickness of the deposited Al is 4500 °. Further, the electrodes and wirings are the input electrode 101, the output electrode (23) of the circuit,
Output electrode (50) of complementary switch 10 and auxiliary circuit 20
Wiring (12) for connecting the
1), input electrode (49) and output electrode (48) of auxiliary circuit
And a wiring (120) for connecting.

Next, the protective film (54) of the array is made of PE-C
The film is formed by the VD method. The protective film is a silicon nitride film and has a thickness of 2000 °.

According to the present embodiment, the complementary switch 10
By forming the auxiliary circuit 20 on the upper part of the circuit, the area of the circuit is not increased, and the fluctuation of the output potential that occurs when the switch is turned off can be canceled.
The switch circuit characteristics can be improved. Therefore, if the digital / analog conversion circuit constituted by the switches is incorporated on an array substrate such as a color liquid crystal display device, the display performance can be improved while the frame is kept narrow.

Further, by forming the gate of the transistor constituting the complementary switch 10 and the gate of the transistor constituting the auxiliary circuit 20 in common, the steps of the complementary switch circuit can be simplified.

Further, since the aluminum wiring region is formed as a single layer, the process can be simplified and problems such as parasitic capacitance can be reduced.

[0052]

As described above, according to the complementary switch circuit of the present invention, the fluctuation of the output potential of the complementary switch can be canceled by the auxiliary circuit without increasing the circuit area. Therefore, by incorporating the electronic circuit constituted by the complementary switch circuit of the present invention on the array substrate of the display device, it is possible to obtain excellent display performance with a narrow frame.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a complementary switch circuit according to an embodiment.

FIG. 2 is a perspective view showing a positional relationship between a complementary switch of the complementary switch circuit of FIG. 1 and a transistor forming an auxiliary circuit;

FIG. 3 is a sectional view showing a structure of electrical connection wiring between a lower complementary switch and an upper auxiliary circuit of the complementary switch circuit shown in FIG. 1;

FIG. 4 is a characteristic diagram showing a relationship between a potential change of a gate electrode of an n-type transistor of a complementary switch and an output voltage.

FIG. 5 is a circuit diagram showing a configuration of a conventional complementary switch circuit.

FIG. 6A is a diagram showing p of the complementary switch circuit shown in FIG.
FIG. 4 is a characteristic diagram illustrating capacitance characteristics of a type transistor. 6B is a characteristic diagram illustrating capacitance characteristics of an n-type transistor of the complementary switch circuit illustrated in FIG.

FIG. 7 is a plan view showing a layout example of the conventional complementary switch circuit shown in FIG. 5;

[Explanation of symbols]

 11, 22 ... n-type transistor 12, 21 ... p-type transistor D11, D12, D21, D22 ... drain S11, S12, S21, S22 ... source G11, 21, G12, 22 ... gate C ... load capacitance

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) NN23 NN24 NN35 NN77 NN78 PP03 PP35

Claims (5)

[Claims] 1. A first n-type transistor and a first p-type transistor are connected in parallel, and a gate control voltage having a different polarity is simultaneously applied to the gate of each transistor to turn on / off both transistors simultaneously. Complementary switches, a second n-type transistor and a second p-type transistor are connected in parallel, the input side and the output side of both transistors are short-circuited, and the gates of the transistors have different polarities. An auxiliary circuit for simultaneously applying a voltage to turn on / off both transistors simultaneously; connecting the auxiliary circuit to an output side of the complementary switch to configure the auxiliary circuit when the complementary switch is turned on Complementary switch circuit for turning on both transistors constituting the auxiliary circuit when the complementary switches are turned off and the complementary switch is turned off Oite, complementary switch circuit, characterized in that the formation of the auxiliary circuit through an upper insulating layer of the complementary switch. 2. The two transistors forming the complementary switch are formed by a top gate type field effect transistor, the two transistors forming the auxiliary circuit are formed by a bottom gate type field effect transistor, The second p-type transistor is formed on the n-type transistor via an insulating film, and the gate electrodes of these two transistors are made common, and the second p-type transistor is provided on the first p-type transistor via a green film. 2. The complementary switch circuit according to claim 1, wherein the second n-type transistor is formed, and the gate electrodes of both transistors are common. 3. The high-concentration ion-doped region of both field-effect transistors forming the complementary switch is wider than the area of the high-concentration ion-doped region of both field-effect transistors forming the auxiliary circuit. The complementary switch circuit according to claim 2, wherein 4. A source electrode and a drain electrode of both field effect transistors forming the complementary switch, a source electrode and a drain electrode of both field effect transistors forming the auxiliary circuit, and another wiring forming the circuit. 4. The complementary switch circuit according to claim 2, wherein all of the switches are formed in a single layer. 5. The semiconductor device according to claim 1, wherein a thickness of a gate insulating film of each of the field effect transistors forming the complementary switch is twice as large as a thickness of a gate insulating film of each of the field effect transistors forming the auxiliary circuit. The complementary switch circuit according to claim 2, 3, or 4.