JP2002280457A - Semiconductor integrated circuit and its placement and routing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and its placement and routing method in which the terminal target of a standard cell is extended over the design rule violating region of a ring (or a strap) so that the terminal wiring of the standard cell can be wired to the outside of the design rule violating region of a wide ring (or a strap) in order to reduce a dead space blocking high integration of the semiconductor integrated circuit. SOLUTION: The semiconductor integrated circuit comprises a standard cell formed on a different multilayer surface while having a terminal target and a narrow line being connected with the terminal target, and a wide line formed on the same multilayer surface as the narrow line. The terminal target extends over the design rule violating region while spaced apart from the wide line by a specified horizontal distance and the narrow line is formed on the outside of the design rule violating region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which a plurality of standard cells and a wide power supply wiring are arranged and wired, and a method of arranging and wiring the same.

[0002]

2. Description of the Related Art Heretofore, when designing the layout of a plurality of standard cells, an automatic layout design method called a standard cell method has been generally used. According to this method, standard cells including different types of logic gates (for example, inverters, AND gates, OR gates, latches, flip-flops, etc.) are registered in a cell library of an automatic wiring placement tool, and are input by a user. Based on the netlist, these standard cells are automatically arranged and wired, and a desired logic circuit having an optimized layout can be easily designed. These standard cells are generally composed of CMOS.

FIG. 5 is a layout plan view of a conventional semiconductor integrated circuit 51. The semiconductor integrated circuit 51 includes different types of logic gates (for example,
It has a plurality of standard cell rows 53 in which standard cells 52 including inverters, AND gates, OR gates, latches, flip-flops, etc. are arranged in a row.

The semiconductor integrated circuit 51 has relatively wide _VDD metal wiring 54 and GND metal wiring 55 (hereinafter referred to as a _VDD ring 54 and a GND ring 55, respectively) formed so as to surround the semiconductor integrated circuit 51. )).
The _VDD ring 54 and the GND ring 55 have portions 54a and 55a extending in the left-right direction (formed of one-layer metal wiring) and portions 54b extending in the vertical direction.
55b (formed of two-layer metal wiring). Further, the semiconductor integrated circuit 51 includes the respective rings 54,
Portion 54b extending in the vertical direction 55, relatively wide _{V DD} metal wiring 56 and the GND metal wire 57 (hereinafter which extends parallel to 55b, _{respectively, V D D} strap 5
6 and GND strap 57. ). Note that the _VDD strap 56 and GND
The strap 57 is formed by a metal two-layer wiring.

The standard cells 52 arranged in the standard cell row 53 share a _VDD metal wiring and a GND metal wiring for supplying a power supply voltage and a ground voltage. Part 5 of each ring 54, 55 extending vertically
4b and 55b are connected to a _VDD metal wiring and a GND metal wiring shared by the standard cell 52 via vertical via holes. The left and right portions 54a, 55a of the rings 54, 55 are connected to the _VDD strap 56 and the GND strap 5 via vertical via holes.
7 are connected to the _VDD metal wiring and the GND metal wiring shared by each standard cell 52.

FIG. 6 is an enlarged layout plan view of a conventional semiconductor integrated circuit 51, showing an inverter 60 and a wide GND strap 57 adjacent to the left side of the inverter 60. Inverter 60 includes p-type transistor regions 62a and n
A _VDD metal wiring 64a and a GND metal wiring 64b for supplying a power supply voltage and a ground voltage, respectively, are formed at the upper and lower ends of the type transistor region 62b using a metal 1 layer wiring. Further, the inverter 60 includes input and output terminal targets 66a, 66a.
b, which are formed using a single metal layer wiring. Furthermore, relatively narrow terminal wirings 70a and 70b connected via vertical via holes 68a and 68b are formed using metal two-layer wirings so as to be connected to other standard cells 52.

[0007] In recent years, the degree of integration of semiconductor integrated circuits has been increasing more and more in recent years, and standard cells including metal wiring have been further miniaturized. Accordingly, D
Research and development to replace the subtractive aluminum wiring (BEOL) used so far in the metal wiring process of the SM (Deep Sub Micron) process with a damascene copper wiring having a sheet resistance lower than about 40%. Is being promoted.

[0008]

However, it has been found that when wiring is performed using damascene copper wiring, constraints such as design rules are considerably stricter than when aluminum wiring is used. For example, the interval between two damascene copper interconnects needs to be set larger than the interval between aluminum interconnects. This will be described in more detail below with reference to FIG.

FIG. 7 shows a wide GND strap 57 (or _VDD ring 54) and terminal wiring 70 connected to input and output terminal targets 70a, 70b of a standard cell 52 (eg, inverter 60) adjacent thereto. It is an enlarged view which shows the outline dimension of. Inverter 6
The zero terminal wires 70a and 70b and the wide GND strap 57 are formed on the same laminated surface using a metal two-layer wire. In general, a distance d1 between the GND strap 57 and the adjacent terminal wiring 70b formed on the same lamination surface and a distance d2 between the terminal wirings 70a and 70b are defined as a design rule when arranging the standard cells. And each terminal wiring 70
It is determined depending on the widths a and b of the a and 70b and the metal constituent material. At this time, the terminal wiring 70b of the inverter 60 cannot be arranged closer than the predetermined distance d1 from the wide GND strap 57. (That is, a design rule violation occurs.) Hereinafter, in this specification,
A region including a predetermined interval d1 where a design rule violation occurs with respect to a wide wiring such as the GND strap 57 is referred to as a design rule violation region R. That is, the standard cell 5 adjacent to the wide GND strap 57
2, the terminal wiring 70 which is closer to the
b must not be arranged in the design rule violation area R.

The predetermined interval d1 defining the design rule violation region R of the GND strap 57 is substantially the same as the width of the terminal wires 70a and 70b when the metal wires are aluminum wires. When the metal wiring is a damascene copper wiring, the width can be approximately 5 to 20 times or more the width of the terminal wirings 70a and 70b. This is because when the damascene copper wiring is used as the metal wiring, the width of the GND strap 5 is wider than when the aluminum wiring is used.
7, the width is almost 5 to 2 times the width b of the terminal wiring 70.
This means that it is necessary to provide a design rule violation area R of about 0 times. In the design rule violation area R, the standard cells 52 cannot be wired. Therefore, in the conventional semiconductor integrated circuit 51, the entire standard cells 52 are arranged and designed at a predetermined interval from a wide wiring such as the GND strap 57. I had to do it. As a result, as shown in FIG.
It is necessary to provide a margin 80 between the second and GND straps 57, and this margin 80 becomes a dead space, which has been a cause of preventing high integration of the semiconductor integrated circuit.

Accordingly, the present invention has been developed to reduce a dead space which is a factor preventing high integration of a semiconductor integrated circuit.
The terminal target of the standard cell is extended beyond the design rule violation region R of the wide ring (or strap), and the terminal wiring of the standard cell is extended beyond the design rule violation region R of the wide ring (or strap). It is an object of the present invention to provide a semiconductor integrated circuit capable of wiring in the above, and a method of wiring and arranging the same.

[0012]

According to the first aspect of the present invention, there is provided a standard cell having a terminal target and a narrow wiring connected to the terminal target, the standard cell being formed on different lamination surfaces, A wide target formed on the same lamination surface as the wiring; a terminal target extending beyond a design rule violating region at a predetermined horizontal distance from the wide wiring; and a narrow wiring extending outside the design rule violating region. Can be provided.

According to the second aspect of the present invention, a standard cell formed on a different lamination surface and having a terminal target and a narrow wiring connected to the terminal target;
A lamination surface on which a terminal target is formed so that the narrow target and the wide wiring formed on the same lamination surface are provided, and the terminal target can be extended beyond a design rule violation area at a predetermined horizontal distance from the wide wiring. It is possible to provide a semiconductor standard cell in which an extendable area is set.

According to the third aspect of the present invention, the wide wiring is a wiring for supplying a power supply voltage or a ground voltage to the standard cell.

According to a fourth aspect of the present invention, in the method of arranging and routing at least one standard cell and a semiconductor standard cell having a wide wiring, the design rule violation area is separated from the wide wiring by a predetermined horizontal distance. Forming a standard cell having a terminal target to be extended; forming a narrow wiring outside the design rule violation area; forming a wide wiring on the same lamination surface as the narrow wiring; Externally connecting a narrow wiring to a terminal target.

According to a fifth aspect of the present invention, in the method of arranging and wiring a semiconductor standard cell having at least one standard cell and a wide wiring, the step of forming the standard cell is performed at a predetermined horizontal distance from the wide wiring. Preparing a plurality of standard cells having a terminal target extending beyond the design rule violation area, based on the positional relationship between the wide wiring and the narrow wiring from among the prepared standard cells,
Selecting an appropriate standard cell.

According to the sixth aspect of the present invention, the step of forming the standard cell includes the step of forming the terminal target so that the terminal target can extend beyond the design rule violation area at a predetermined horizontal distance from the wide wiring. A step of preparing a standard cell in which an extendable area is set in a lamination plane to be laminated, and a step of extending a terminal target to an extendable area based on a positional relationship between a wide wiring and a narrow wiring. An arrangement and wiring method can be provided.

According to the present invention, the wide wiring is a wiring for supplying a power supply voltage or a ground voltage to the standard cell.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit and a method of arranging and wiring the same according to the present invention will be described below in detail with reference to the drawings. In the description of the present embodiment, terms indicating directions (for example, “vertical direction”, “horizontal direction”, and the like) are used as appropriate for easy understanding, but these are for explanation. Does not limit the invention.

FIG. 1 is a layout plan view of a semiconductor integrated circuit 1 according to the present invention. The semiconductor integrated circuit 1 includes different types of logic gates (for example,
It has a plurality of standard cell rows 3 in which standard cells including inverters, AND gates, OR gates, latches, flip-flops and the like are arranged in a row.

The semiconductor integrated circuit 1 has a relatively wide V _DD metal wiring 4 formed so as to surround it.
And GND metal wiring 5 (hereinafter, referred to as _VDD ring 4 respectively)
And a GND ring 5. ). Also, V
_{The DD} ring 4 and the GND ring 5 are portions 4a and 5a extending in the left-right direction (formed of a single metal layer wiring).
And portions 4b and 5b extending in the vertical direction (formed of a two-layer metal wiring). Further, the semiconductor integrated circuit 1 has a relatively wide V extending parallel to the vertically extending portions 4b and 5b of the rings 4 and 5, respectively.
_DD metal wiring 6 and GND metal wiring 7 (hereinafter, respectively,
They are referred to as a _VDD strap 6 and a GND strap 7. ). Note that the _VDD strap 6 and the GND strap 7 are formed by two-layer metal wiring.

Each of the standard cells 2 arranged in the standard cell row 3 shares a _VDD metal wiring and a GND metal wiring (described later) for supplying a power supply voltage and a ground voltage. The vertically extending portions 4b and 5b of the rings 4 and 5 are connected to a _VDD metal wiring and a GND metal wiring shared by the standard cell 2 via vertical via holes. The portions 4a and 5a of the rings 4 and 5 extending in the left-right direction are V V via vertical via holes.
_{The DD} strap 6 and the GND strap 7 are connected to the _VDD metal wiring and the GND metal wiring shared by the standard cell 2. Thereby, the standard cell 2
Can be compensated for the voltage drop of the _VDD metal wiring and the GND metal wiring shared by the two.

Each of the metal wirings described so far is preferably designed to preferentially extend in a certain direction. For example, portions 4a, 5 of the rings 4, 5 extending in the left-right direction.
1 is preferentially extended in the left-right direction shown in FIG.
The metal two-layer wiring such as b, 5b, _VDD strap 6, and GND strap 7 is ruled so as to extend in the vertical direction. Similarly, it is preferable that the odd-numbered metal wirings after the metal three-layer wiring (not shown) are preferentially wired so as to extend in the left-right direction and the even-numbered metal wirings extend in the up-down direction.

FIG. 2 is an enlarged layout plan view of the semiconductor integrated circuit 1 according to the present invention.
And the wide GND strap 7 adjacent to the left side. First, regarding the general configuration of the standard cell 2,
A description will be given using the inverter 10. Standard cell 2
Has a plurality of transistors formed of CMOS,
For example, the inverter 10 includes a p-type transistor region 12
a and an n-type transistor region 12b. Also,
At upper and lower ends of the standard cell 2, _VDD metal wirings 14 for supplying a power supply voltage and a ground voltage, respectively.
a and the GND metal wiring 14b are formed using a metal one-layer wiring. As described above, the standard cell rows 3 arranged in a row share the _VDD metal wiring 14a and the GND metal wiring 14b extending linearly. Further, the standard cell 2 has at least one input and output terminal target 16a, 16b, which are formed using a metal 1 layer wiring. Further, relatively narrow terminal wirings 20a and 20b connected via the vertical via holes 18a and 18b are formed using metal two-layer wirings so as to be connected to the other standard cells 2 mutually.

Generally, in a floor plan step of a DSM (Deep Sub Micron) process, it is not possible to design a layout such that two metal wirings formed on the same lamination surface are brought closer than a predetermined interval defined as a design rule. Can not. In other words, when placing one metal wiring,
It is necessary to design the layout at a position separated from the other metal wiring by a predetermined distance or more. As described above, in this specification, a region in which the design placement of the other metal wiring is prohibited in a region within a predetermined distance from one metal wiring is referred to as a design rule violation region R. Varies depending on various factors such as a metal material and a wiring width.
For example, the design rule violation region R of the damascene copper wiring is wider than that of the aluminum wiring, and the design rule violation region R of the wide metal wiring is wider than the narrow metal wiring.
Therefore, when the wide metal wiring and the narrow metal wiring are arranged adjacent to each other using the same metal material, it is necessary to design the layout so that the narrow metal wiring is not wired in the design rule violation region R of the wide metal wiring. There is.

As apparent from FIG. 2, the GND strap 7 and the terminal wirings 20a and 20b of the inverter 10 are provided.
Are formed of two-layer metal wiring and are adjacent to each other. Therefore, in the metal two-layer wiring, the terminal wirings 20a and 20b must be laid out outside the design rule violation region R at a predetermined horizontal distance d1 from the GND strap 7.

Therefore, according to the present invention, the output terminal target 16b extends beyond the design rule violation area R in a direction away from the GND strap 7, and violates the design rule via the terminal wiring 20b and the vertical via hole 18b. The connection is made outside the region R. Thereby, it is possible to eliminate a design rule violation that occurs between the GND strap 7 and the terminal wiring 20b.

Referring to FIG. 3, a modification of the inverter 10 shown in FIG. 2 will be described. FIG. 3A is a plan view of only the inverter 10 of FIG. 2, and includes the GND strap 7, the terminal wires 20 a and 20 b, and the via hole 18.
a and 18b are omitted. 3 (b) to 3
FIG. 3D is a layout plan view similar to FIG. 3A.

FIG. 3B shows a wide GND strap 7.
The inverter 10 in which the terminal target 16b is further extended in a direction away from the inverter 10 is shown. Thus, even if the design rule violation region R is wider than the case shown in FIG. 3A, the terminal wiring 20b can be routed while avoiding the design rule violation for the wide GND strap 7. .

Note that the wide GND strap 7 is
When the inverter 10 is disposed on the right side of the inverter 10 shown in FIG. 3A or FIG. 3B, a design for a wide GND strap 7 is performed by using the inverter 10 having a mirror image relationship (symmetrical relationship) with the inverter 10. The terminal wirings 20a and 20b can be arranged while avoiding a rule violation. In other words, by selecting and using an appropriate inverter 10 according to the positional relationship between the wide GND strap 7 and the terminal wirings 20a and 20b, it is possible to eliminate the design rule violation.

In the inverter 10 shown in FIG. 3C, not only the terminal target 16b extends rightward, but also the terminal target 18a extends leftward.
The inverter 10 configured as described above has a wide GND
It can be used whether the strap 7 is on the right or left side. That is, it can be used regardless of the arrangement position of the wide GND strap 7 and the terminal wirings 20a and 20b.

As will be described later, the inverter 10 shown in FIGS. 3A to 3C is registered in the cell library in advance together with the attribute information on the pattern shape. Alternatively, an appropriate standard cell 2 can be selected and used according to the positional relationship between the strap 6 and the terminal wires 20a and 20b. Thus, only the standard cell 2 adjacent to the wide ring 5 or the strap 6 is
By substituting the standard cell 2 as shown in (a) to (c), it is possible to very easily avoid or eliminate the design rule violation regarding the wide wiring.

Referring to FIG. 3D, a further modification of the inverter 10 according to the present invention will be described. The inverter 10 shown in FIG. 3D can be changed to the inverter 10 shown in FIG. 3A or FIG. 3B according to the positional relationship between the wide GND strap 7 and the terminal wiring 20b.
This is the same as the conventional inverter 60 shown in FIG. 6 except that a blank area 18 is previously secured on the same lamination surface as the terminal target 16b. Accordingly, when the inverter 10 is arranged adjacent to the wide GND strap 7, the inverter
In the reserved blank area 18.
It is possible to change or modify the inverter 10 with the extension b. In other words, the inverter 10 shown in FIG. 3D is the same as the inverter 10 shown in FIG. 3A or FIG.
Terminal target 16b so that it can be changed or modified to
A blank area 18 such that no metal wiring or the like is formed on the same lamination surface is secured (set).

As described above, according to the present invention, the metal 2
Wide wiring formed as layer wiring (portion 4b extending in the vertical direction of _VDD ring 4 and straps 6, 7)
By extending the terminal targets 16a and 16b beyond the design rule violation region R, the design rule violation at the time of wiring the terminal wirings 20a and 20b of the metal two-layer wiring connected thereto is avoided or eliminated. Can be. Similarly, according to the present invention, by extending the terminal target beyond the design rule violation region R of the wide wiring (the portion 4a extending in the left-right direction of the _VDD ring 4) formed as a metal one-layer wiring, In addition, it is possible to avoid or eliminate design rule violation when arranging the terminal wiring of the metal one-layer wiring connected thereto. That is, although the present specification has mainly described avoiding or eliminating design rule violations that can occur between a wide wiring formed as a two-layer metal wiring and a terminal wiring, those skilled in the art can easily understand. As described above, the present invention can be applied to solve a design rule violation that may occur between a wide wiring formed as a metal single-layer wiring and a terminal wiring.

Further, with reference to FIG. 1, a case has been described where the _VDD ring 4 surrounding the semiconductor integrated circuit 1 is arranged inside. However, the _VDD ring 4 is arranged outside and the GND ring 5 is arranged inside. And the present invention is not limited thereby.

Next, a method for arranging and wiring semiconductor integrated circuits according to the present invention will be described with reference to the flowchart of FIG. Here, a method of placing and routing the semiconductor integrated circuit 1 using a widely used automatic placement and routing tool will be described. However, the use of the automatic routing and placement tool is not essential and does not limit the present invention.

In the floor plan process of step ST01, the user places the different types of standard cells 2 (eg, inverters, AND gates, OR gates, latches, flip-flops, etc.) in their layout information and layout and wiring constraints (design rules). The attribute information such as information is registered in advance in the cell library of the automatic wiring placement tool. In addition to the standard cell 2, a macro cell may be similarly registered in the cell library. Preferably, a plurality of standard cells having the same shape and function and different attribute information (layout information) are registered for one type of standard cell 2 as described above. For example, an inverter 10 as shown in FIGS. 3A to 3D is registered in the cell library.

In the floor plan process of step ST01, the user inputs circuit wiring information (connection information) between the standard cells 2 for the semiconductor integrated circuit 1 to be laid out to the netlist of the automatic wiring placement tool. At the same time, property information such as timing information (wiring delay information) and pin arrangement information is input. In the floor plan process of step ST01, the user sets the number of rows in which standard cells are to be arranged, the average arrangement density, and defines the shape (aspect ratio) of the arrangement area.

The automatic wiring placement tool executes step ST02
In the ring / strap arranging step, each ring 4, 5 and each strap 6, 7 are arranged based on the information input by the user, and in the standard cell arranging step in step ST03, each standard cell 2 is roughly arranged. . At this time, the automatic wiring arrangement tool arranges each standard cell 2, each ring 4, 5 and each strap 6, 7 so that the area of the semiconductor integrated circuit 1 is minimized.

Further, the automatic wiring placement tool performs the standard wiring 2 and the ring 4 based on the input netlist in the schematic wiring process of step ST04.
5 and the respective straps 6 and 7 are roughly wired, and step S
In the rough evaluation step of T05, the semiconductor integrated circuit 1 can be arranged and arranged while satisfying the design rules between the terminal wirings 20a and 20b of the standard cell 2 and the wide rings 4 and 5 and the straps 6 and 7. Determine whether or not.

In the rough evaluation process of step ST05, when the automatic wiring placement tool determines that a design rule violation occurs (in the case of NO), for example, a wide GND
A design rule violation occurs between the strap 7 and the terminal wiring 20b of the inverter 10 adjacent to the right side thereof (for example, the terminal wiring 20b of the inverter 10 is arranged in the design rule violation region R of the wide GND strap 7). And the case where the automatic wiring placement tool determines. An inverter 10 (FIG. 3A) that extends the conventional inverter 60 (FIG. 6) beyond the design rule violation region R in a direction in which the terminal target 16b moves away from the wide GND strap 7 (to the right in this case). By the replacement, the design rule violation between the wide GND strap 7 and the terminal wiring 20b of the inverter 10 can be eliminated.

As described above, since the inverter 10 shown in FIGS. 3A to 3C has been registered in the cell library in advance as an inverter having different attribute information in the floor plan process of step ST01, The wiring placement tool recognizes the violation of the design rule and recognizes the plurality of inverters 10 registered in the cell library in advance.
Therefore, an appropriate inverter 10 can be selected from the inverters shown in FIGS. 3A to 3C and replaced based on the positional relationship between the wide GND strap 7 and the narrow terminal wiring 20b. The inverter 10 shown in FIGS. 3A to 3C has a terminal target 16b.
Have the same shape and function except for the layout described above, the replacement of these inverters 10 does not affect the layout design of the entire semiconductor integrated circuit 1. Thus, the time and labor required to complete the placement and routing of the entire semiconductor integrated circuit 1 can be significantly reduced.

Similarly, when the design rule is violated between the wide GND strap 7 and the terminal wiring 20a of the inverter 10 adjacent to the left side, FIG.
Similarly, by replacing the inverter 10 having the layout of the terminal targets 16a and 16b in a mirror image relationship with the inverter 10 shown in (a) or (b) or the inverter 10 shown in FIG. Rule violations can be eliminated.

In addition, an inverter 10 for securing a blank area as shown in FIG. 3D is registered in the cell library in advance, and the layout of the entire semiconductor integrated circuit 1 is designed using the inverter 10 to be used for the adjacent layout. If a design rule violation is recognized with the wide GND strap 7, the wide G
The inverter 10 may be changed or modified so that the terminal target 16b extends beyond the design rule violation region R at a predetermined horizontal distance from the ND strap 7. By changing the terminal target 16b of the inverter 10, the layout design of the entire semiconductor integrated circuit 1 is not affected, and similarly, the time and labor for completing the arrangement and wiring of the entire semiconductor integrated circuit 1 can be significantly reduced. .

In the general evaluation step of step ST05, when the automatic wiring and placement tool determines that the wiring can be roughly arranged (in the case of YES), the automatic wiring and placement tool executes the standard cell in the detailed wiring step of step ST06. 2. Wiring the wide rings 4 and 5 and the straps 6 and 7 in detail.

In the detailed evaluation step of step ST07, the terminal wirings 20a and 20b of the standard cell 2
While satisfying the design rules between the wide rings 4 and 5 and the straps 6 and 7, the semiconductor integrated circuit 1
It is determined whether or not wiring can be roughly arranged.

In the detailed evaluation step of step ST07, when the automatic wiring placement tool determines that a design rule violation occurs (in the case of NO), as in step ST05, based on the positional relationship between the wide wiring and the narrow wiring, the shape and the shape are determined. By replacing or changing with a standard cell 2 having the same function and a different attribute (terminal target 16b), a design rule violation can be easily eliminated.

In the general evaluation step of step ST07, when the automatic wiring and placement tool determines that the wiring can be arranged in detail (in the case of YES), the automatic wiring and placement tool sets the standard cell 2 and the wide rings 4 and 5 , And the respective straps 6 and 7 are wired in detail as they are, and the arrangement and wiring process of the semiconductor stand-alone cell 1 is completed.

[0049]

According to the first to third aspects of the present invention, it is possible to provide a highly integrated semiconductor integrated circuit without providing a margin for a dead space between a standard cell and a wide wiring. .

According to the present invention, there is provided a method for arranging and wiring a semiconductor integrated circuit with a high degree of integration without providing a margin serving as a dead space between a standard cell and a wide wiring. Can be provided.

In particular, according to the present invention, even when a design rule is violated between a wide wiring and an adjacent narrow wiring, the design rule violation region R is separated from the wide wiring by a predetermined horizontal distance. By replacing or changing with a standard cell having a terminal target extending beyond, the design rule violation can be easily eliminated. At this time, since there is no need to redesign the entire semiconductor standard cell 2, the time and labor required to complete the layout and wiring of the entire semiconductor integrated circuit 1 can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a layout plan view of a semiconductor standard cell according to the present invention.

FIG. 2 is an enlarged layout plan view of a semiconductor standard cell according to the present invention.

3 (a) is a plan view of only the inverter shown in FIG. 2, and FIGS. 3 (b) to 3 (d) show a modification of the inverter shown in FIG. 3 (a).

FIG. 4 is a flowchart showing a method for arranging and wiring semiconductor standard cells according to the present invention.

FIG. 5 is a layout plan view of a conventional semiconductor standard cell.

FIG. 6 is an enlarged layout plan view of a conventional semiconductor standard cell.

FIG. 7 is an enlarged view showing schematic dimensions of a wide wiring and a terminal wiring of a standard cell adjacent thereto;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Standard cell, 3 ... Standard cell row, 4a, 4b ... _VDD ring, 5a, 5
b ... GND ring, 6 ... V _DD strap, 7 ... GND
Strap, 10 ... inverter, 12a ... p-type transistor region, 12b ... n-type transistor region, 14a ... V
_DD metal wiring, 14b GND metal wiring, 16a input terminal target, 16b output terminal target, 18
a, 18b: via hole, 20a, 20b: terminal wiring.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F033 MM01 UU02 UU04 XX00 5F038 BE07 CA02 EZ08 EZ11 EZ20 5F064 AA04 BB07 DD05 DD25 EE03 EE14 EE52 GG10

Claims (7)

[Claims] 1. A standard cell formed on a different lamination surface and having a terminal target and a narrow wiring connected to the terminal target, and a wide wiring formed on the same lamination surface as the narrow wiring. A semiconductor integrated circuit, wherein the target extends beyond a design rule violation area at a predetermined horizontal distance from the wide wiring, and the narrow wiring is formed outside the design rule violation area. 2. A standard cell formed on a different lamination surface and having a terminal target and a narrow wiring connected to the terminal target, and a wide wiring formed on the same lamination surface as the narrow wiring. A semiconductor integrated circuit, wherein an extendable area is set in a lamination plane on which a terminal target is formed so that a target can extend beyond a design rule violation area at a predetermined horizontal distance from a wide wiring. 3. The semiconductor integrated circuit according to claim 1, wherein the wide wiring is a wiring for supplying a power supply voltage or a ground voltage to the logic gate. 4. A method for arranging and routing a semiconductor integrated circuit having at least one standard cell and a wide wiring, comprising: a standard cell having a terminal target extending beyond a design rule violation area at a predetermined horizontal distance from the wide wiring. Forming, forming a narrow wiring outside the design rule violation area, forming a wide wiring on the same lamination surface as the narrow wiring, connecting the narrow wiring to the terminal target outside the design rule violation area Performing the steps of: 5. The method according to claim 4, wherein the step of forming a standard cell comprises preparing a plurality of standard cells having terminal targets extending beyond a design rule violation area at a predetermined horizontal distance from the wide wiring. And selecting an appropriate standard cell from a plurality of prepared standard cells based on the positional relationship between the wide wiring and the narrow wiring. 6. The method according to claim 4, wherein the step of forming the standard cell includes the step of: forming the terminal target so that the terminal target can extend beyond a design rule violation area at a predetermined horizontal distance from the wide wiring. A step of preparing a standard cell having an extendable area set in a stacking surface to be formed; and extending a terminal target to the extendable area based on a positional relationship between the wide wiring and the narrow wiring. how to. 7. The method according to claim 4, wherein the wide wiring is a wiring for supplying a power supply voltage or a ground voltage to a standard cell.