JP2002279783A - Semiconductor memory and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory realizing optimum transfer operation in accordance with an application. SOLUTION: An address input means 1 receives an input of an address. A readout means 2 reads out automatically and successively data corresponding to the address of 1 inputted through the address input means 1 from banks 5-1 to 5-m of m (<=n) pieces. A data output means 3 outputs data read out from the banks 5-1 to 5-m of m pieces by the read-out means 2 to the outside as batch data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and an information processing device, and more particularly to a semiconductor memory device having n (n> 1) banks, such a semiconductor memory device, and a control device for controlling the same. And an information processing apparatus having the same.

[0002]

2. Description of the Related Art Data is exchanged between a semiconductor memory device and a control device for controlling the semiconductor memory device with a predetermined number of bits determined according to an application such as an OS (Operating System).

In the case of an application having a small number of bits, when the amount of data to be read / written increases, the number of command inputs increases accordingly, so that a single command input causes a read operation and a precharge operation to be performed. Auto-precharge type DRAM (Dy
It is effective to use a static random access memory (SRAM) or a static RAM (SRAM) that does not require precharging.

FIGS. 10 and 11 are diagrams for explaining such a situation. FIG. 10 is a diagram for explaining the operation of a DRAM having no auto-precharge function, that is, a non-auto-precharge type DRAM in which the number of data bits per read operation is 2 bits. . Such non-auto-precharge type DRA
In the case of M, as shown in FIG. 10B, when the access ends, the precharge commands (PRE1 to PRE
It is necessary to input 3) and execute precharge. In the example of this figure, read commands (RD1 to RD3) are input at the 0th, 2nd, and 4th rising edges of the basic clock (see FIG. 10A), and the first, third, and At the fifth rising edge, precharge commands (PRE1 to PRE3) are input. As a result of the input of the read command, FIG.
As shown in FIG. 0 (C), 2-bit data (Q11, Q12, Q21, Q22, Q3) is output from the DATA output terminal at the first, third, and fifth rising edges.
1, Q32) are output.

On the other hand, FIG. 11 is a diagram for explaining the operation of an auto-precharge type DRAM which automatically performs precharge, in which the number of data bits per read operation is 2 bits. is there. As shown in this figure, in the case of an auto-precharge type DRAM, it is not necessary to input a precharge command.
As shown in (B), the read commands (RD1 to RD)
3) can be input continuously. Further, as a result, the intervals between commands become narrower, and as shown in FIG. 11C, data (Q11, Q12, Q21, Q22, Q3) output from the DATA output terminal is output.
The intervals of (1, Q32) are also closer compared to the case of FIG. Therefore, all data can be read in a shorter time than in the case of FIG.

As described above, a semiconductor memory device,
If the number of bits of data transmitted to and received from a control device for controlling the
A device that automatically executes a precharge operation, such as M, can relatively increase the command density, and as a result, can advantageously increase the data access density.

By the way, the case where the number of bits of data transmitted and received between the semiconductor memory device and the control device for controlling the semiconductor memory device is small has been described. The case where the number of bits is large will be considered below. .

FIG. 12 is a diagram for explaining the operation of an auto precharge type DRAM in which the number of bits of data transmitted to and received from a control device is 8 bits. In the example of this figure, at the 0th rising edge of the basic clock shown in FIG.
2 (B)), and as a result, the data read out as shown in FIG.
Output from the output terminal.

FIG. 13 shows an auto-precharge type DRAM in which the number of bits of data transmitted to and received from a control device is 8 bits, and the number of bits of data per read operation is 2 bits. It is a figure explaining operation at the time of using.

As shown in FIG. 1, a DRAM in which the number of bits of data per one read operation is 2 bits,
When used in a system in which the number of bits of data exchanged with the control device is 8 bits, it is necessary to input four RD commands (RD1 to RD4). As a result, the intervals between the RD commands become narrower, so that there is a disadvantage that other devices cannot access during the access.

[0011]

As described above, conventionally, an optimum device is selected according to the number of bits of data transmitted and received between a semiconductor memory device and a control device for controlling the same. I needed to. In other words, conventionally, there is a problem that there is no device corresponding to all the bit numbers.

The present invention has been made in view of such a point, and an optimum operation is performed irrespective of the number of bits of data transmitted and received between a semiconductor memory device and a control device that controls the semiconductor memory device. It is an object of the present invention to provide a semiconductor storage device that can be used and an information processing device including such a semiconductor storage device.

[0013]

According to the present invention, in order to solve the above-described problems, in a semiconductor memory device having n (n> 1) banks shown in FIG. And data corresponding to one address input via the address input means 1 are represented by m (≦
reading means 2 for sequentially reading out from n) banks 5-1 to 5-m;
And a data output means for outputting data read from 1 to 5-m to the outside as a set of data.

The address input means 1 receives an address. The reading means 2 reads data corresponding to one address input via the address input means 1 into m (≦
(n) Read sequentially from the banks 5-1 to 5-m. The data output means 3 outputs the data read from the m banks 5-1 to 5-m by the read means 2 to the outside as a set of data.

Further, in an information processing device having a semiconductor memory device having n (n> 1) banks and a control device for controlling the same, the semiconductor memory device comprises: an address input means for receiving an address; The data corresponding to one address input through the address input means is represented by m
Reading means for sequentially reading from (≦ n) banks;
Data output means for outputting the data read from the m banks by the read means as a set of data to the outside, wherein the control device has a cycle time determined according to a read cycle of the read means. And an access prohibition unit for prohibiting access to a predetermined bank in accordance with the bank being read by the reading unit. You.

Here, in the semiconductor memory device, the address input means receives an address. The reading means sequentially reads data corresponding to one address input via the address input means from m (≦ n) banks. The data output means outputs the data read from the m banks by the reading means to the outside as a set of data. In the control device,
The control means controls the semiconductor memory device according to a cycle time determined according to a read cycle of the read means. The access prohibiting unit prohibits access to a predetermined bank according to the bank from which the reading unit is reading.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram for explaining the operation principle of the present invention. As shown in this figure, the semiconductor memory device of the present invention comprises an address input unit 1, a read unit 2,
Data output means 3, output data amount setting means 4, and
It is constituted by banks 5-1 to 5-n.

The address input means 1 receives an address to be accessed from outside. The reading means 2 receives the 1 input via the address input means 1
Are sequentially read from m (≦ n) banks.

The data output means 3 outputs the data read from the m banks by the read means 2 to the outside as a set of data. The output data amount setting means 4 sets the data amount to be output by the data output means 3.

Next, the operation of the above principle diagram will be described. The output data amount setting means 4 inputs information for designating a data amount to be output as a group of data by the data output means 3 by, for example, a control signal from a control device (not shown) when the semiconductor memory device is started. Then, the output data amount is set according to the information.

When an address is externally input to the address input means 1 in a state where the data output means 3 sets the data amount to be output as a set of data, the address input means 1 The input address is supplied to the reading means 2.

When the data amount set by the output data amount setting unit 4 exceeds the data amount that can be read out from a single bank at a time, the reading unit 2 first starts the address input unit 1 A bank corresponding to the input address is selected, data is read from the bank, and supplied to the data output means 3. Subsequently, the reading unit 2 executes a process of switching to the next bank, and acquires another data from the same address of the new bank that has been switched. Such an operation is repeated until data corresponding to the output data amount specified by the output data amount setting means 4 is read. At this time, the reading means 2 reads data from each bank at predetermined time intervals so that data read from different banks does not congest each other.

At this time, the data output means 3 sequentially acquires data sequentially read from the banks 5-1 to 5-n by the reading means 2 and sequentially outputs the data to the outside. As a result, if the amount of data output by the data output unit 3 as a set of data is equal to or less than the amount of data read at a time from a single bank, the reading unit 2 outputs a single data. When the data is read from the bank and the read operation is completed, on the contrary, when the former exceeds the latter, the read means 2 automatically switches between the banks 5-1 to 5-n and supplies the data from the address input means 1. Done 1
Can be read from each bank.

Therefore, the amount of data read by one address designation can be changed in accordance with the amount of data (a set of data) at the time of transmission / reception with the control device determined by the application. It is possible to provide a semiconductor memory device that can be used for any purpose.

FIG. 2 shows a case where there are four banks (n = 4), and when the number of bits of data read from a single bank is two, a group output by the data output means 3 is shown. FIG. 9 is a diagram illustrating an example of an operation when the number of data bits is set to 8 bits.

In the example of this figure, the read command RD1 is input in synchronization with the 0th rising edge of the basic clock shown in FIG. In this case, since the number of bits of data read from a single bank is 2 bits, the reading means 2 sequentially switches the four banks, and transfers data corresponding to one address input from the address input means 1 to each bank. And supplies it to the data output means 3. As shown in FIG. 2C, the data output means 3 supplies data (Q11, Q12,..., Q41, Q42) supplied from the read means 2 four times.
Is output to the outside as a set of data.

As a result, in the case of the conventional semiconductor memory device, it is necessary to input the read command four times, as shown by the broken line in FIG. become.

In the above example, the reading means 2
Although the data amount set by the output data amount setting means 4 is detected by referring to the data output means 3, it is also possible to detect by directly referring to the output data amount setting means 4.

Next, an embodiment of the present invention will be described. FIG. 3 is a diagram showing a configuration example of an embodiment of the information processing apparatus of the present invention. As shown in this figure, the information processing apparatus of the present invention has a CPU (Central Processing Unit) 1
0, a control device 20, a semiconductor memory device 30, and a bus 40.

Here, the CPU 10 is connected to the semiconductor memory device 3
By executing various programs and the like stored in “0”, each part of the apparatus is controlled and various arithmetic processes are executed.

The control device 20 controls the setting of the burst length of the semiconductor memory device 30 and the refresh operation. The semiconductor memory device 30 stores the data supplied from the CPU 10 under the control of the control device 20, reads the stored data, and supplies the read data to the CPU 10.

The bus 40 transmits data from the CPU 10 to the semiconductor memory device 30 and also transmits data from the semiconductor memory device 30 to the CPU 10. FIG. 4 is a diagram showing a detailed configuration example of the semiconductor memory device 30 shown in FIG. As shown in this figure, the semiconductor memory device 30 is configured by a control unit 50, a bank A60, and a bank B70. The bank A60 includes a cell 61, a column decoder 62, a row decoder 63, and an SA (Sense Amplifier) 6.
4 and an I / O (Input Output) circuit 65. Similarly, the bank B70 is connected to the cell 7
1, a column decoder 72, a row decoder 73, an SA 74, and an I / O circuit 75.

The control unit 50 includes a CLK signal, a CMD signal,
An operation of inputting an ADD signal, a DATA signal, and the like, supplying the data to each unit of the device, and selecting a predetermined bank when transferring data, and reading or writing data from the selected bank. Execute

The cells 61 of the bank A60 are composed of a group of storage elements arranged in a matrix, and store input data. The row decoder 63 specifies a predetermined row of the cells 61 based on a row address when inputting / outputting data.

The column decoder 62 designates a predetermined column of the cell 61 based on a column address when inputting / outputting data. The SA 64 amplifies the signal read from the cell 61 with a predetermined gain and converts the signal into a digital level signal.

The I / O circuit 65 controls data input / output. Since the bank B70 has the same configuration, the description thereof is omitted. FIG. 5 is a diagram showing a detailed configuration example of the control unit 50 shown in FIG.

Here, CLK input terminal 80 receives an input of a CLK signal from outside. The CMD input terminal 81 receives an input of a CMD signal from outside. ADD input terminal 82
Receives an ADD signal from outside.

The CLK input circuit 83 has a CLK input terminal 8
After shaping the CLK signal input from 0, the CMD
It is supplied to an input circuit 84, an ADD input circuit 85, and a bank activation control circuit 88.

The CMD input circuit 84 has a CMD input terminal 8
After shaping the waveform of the CMD signal input from step 1,
It is supplied to the decoder 86. The ADD input circuit 85
After waveform-shaping the ADD signal input from the D input terminal 82, the signal is supplied to a burst length determination circuit 87.

The CMD decoder 86 has a CMD input circuit 8
4 is decoded, and the obtained R
The D command or the WR command is supplied to the bank activation control circuit 88 and the ADD latch 90.

For example, when a command for setting a burst length is input at the time of starting the apparatus, the burst length determining circuit 87 analyzes the command and determines the burst length required to be set. Then, the obtained burst length is notified to the bank activation control circuit 88.

The bank activation control circuit 88, the timing circuit 89, and the ADD latch 90 are provided in each of the banks A60 and B70 shown in FIG. 4, and each of the banks has an internal address. An IADD is supplied to control data reading.

Here, the bank activation control circuit 88 controls the timing circuit 89 according to the set burst length, and performs control when data is read from each bank. A
The DD latch 90 latches the ADD signal output from the ADD input circuit 85 in synchronization with the RD command output from the CMD decoder 86.

The timing circuit 89 includes an ADD latch 90
The ADD signal latched by the internal address I is latched at the timing according to the control of the bank activation control circuit 88.
It is supplied to each bank as ADD.

FIG. 6 is a diagram showing a detailed configuration example of the bank activation control circuit 88, the timing circuit 89, and the ADD latch 90. As shown in the figure, the bank activation control circuit 88 includes inverters 100 to 102, NOR
Elements 103 and 104, NAND element 105, DFF (Da
ta Flip Flop) elements 106 to 109 and CMOS
(Complementary Metal-Oxide Semiconductor) Switches 110 and 111 are provided.

The inverter 100 includes a CMD decoder 86
Inverts the RD / WR signal supplied from the NOR element 1
03. The NOR element 104 receives the ADD signal for specifying the bank supplied from the ADD input circuit 85 and the BL8 signal (“H” when the burst length is set to “8”) supplied from the burst length determination circuit 87. Of the NOR element 1)
03.

The NOR element 103 supplies the result obtained by inverting the logical sum of the output of the inverter 100 and the output of the NOR element 104 to the DFF element 106. DFF element 106-1
08 is NO in synchronization with the falling edge of the CLK signal.
The output of the R element 103 is sequentially delayed and output. The output of the DFF element 108 is supplied to a CMOS switch 110.

The DFF element 109 latches the output of the NOR element 103 in synchronization with the falling edge of the CLK signal and supplies it to the CMOS switch 111. Inverter 1
01 inverts and outputs the ADD signal. The NAND element 105 outputs the result of inverting the logical product of the output of the inverter 101 and the BL8 signal to the inverter 102 and the CMOS
This is supplied to the switches 110 and 111.

The CMOS switch 110 is turned on when the output of the NAND element 105 is in the "L" state, and supplies the output of the DFF element 108 to the timing circuit 89 as a BACT signal. When the output is in "H" state, it is in OFF state.

The CMOS switch 111 is turned on when the output of the NAND element 105 is "H", and supplies the output of the DFF element 109 to the timing circuit 89 as a BACT signal. Is in the OFF state when the output is "L".

Therefore, when the output of the NAND element 105 is "H", the CMOS switch 111 is turned on.
And the output of the DFF element 109 is supplied to the timing circuit 89 as a BACT signal, and the NAND circuit 1
When the output of the switch 05 is “L”, the CMOS switch 110 is turned on, and the output of the DFF element 108 is supplied to the timing circuit 89 as a BACT signal.

The ADD latch 90 includes an inverter 130 and a DFF element 131. Inverter 130 inverts and outputs the RD / WR signal. DF
The F element 131 latches the ADD signal in synchronization with the falling edge of the output from the inverter 130, that is, the rising edge of the RD / WR signal, and outputs it as a BADD signal.

The timing circuit 89 includes an inverter 120
And the DFF element 121. The inverter 120 inverts and outputs the BACT signal output from the CMOS switch 110. DFF element 121
Is the falling edge of the output from inverter 120,
That is, BA is synchronized with the rising edge of the BACT signal.
The DD signal is latched, output as an IADD signal as an internal address, and supplied to the bank A60 or the bank B70.

FIG. 7 shows the DFF elements 106-1 shown in FIG.
FIG. 9 is a diagram illustrating a detailed configuration example of the embodiment 09. As shown in this figure, the DFF element includes inverters 140 to 144 and C
MOS switches 145 and 146 are provided.

Here, the inverter 140 inverts the CLK signal and supplies it to the CMOS switches 145 and 146. The CMOS switch 145 sets the clock signal to “H”.
, The input signal is supplied to the inverter 141.

When the clock signal goes to “L”, the CMOS switch 146 turns on, and supplies the output of the inverter 141 to the inverter 143. The inverter 141 inverts the output of the CMOS switch 145 and supplies the inverted output to the CMOS switch 146.

The inverter 142 inverts the output of the inverter 141 and feeds it back to the input of the inverter 141. The inverter 143 includes a CMOS switch 146
Is inverted and output.

The inverter 144 inverts the output of the inverter 143 and feeds it back to the input of the inverter 143. Next, the operation of the above embodiment will be described.

Assuming that the information processing apparatus shown in FIG. 3 is turned on, the CPU 10 determines the number of bits of data to be transmitted to and received from the semiconductor memory device 30 in accordance with the application to be executed. Notify 20.

Control device 20 sets the burst length of semiconductor memory device 30 in accordance with the number of bits of the data notified from CPU 10. For example, when the bit length of data that can be read from the banks A60 and B70 of the semiconductor memory device 30 at one time is 4 bits and the burst length is set to 8 bits, the control device 20 controls the semiconductor memory device. A command for setting the burst length is input from the CMD input terminal 81 of
Data indicating the burst length “8” is input from the D input terminal 82. In a conventional semiconductor memory device, it is not allowed to set a burst length that exceeds the number of bits of data that can be read from a bank at one time, but the present embodiment is characterized in that such a setting is allowed. There is.

As a result, the CMD decoder 86 detects that a command for setting the burst length has been input, and requests the burst length determination circuit 87 to set the burst length. The burst length determination circuit 87 decodes the data supplied from the ADD input circuit 85 and detects that the burst length is set to “8”. And bank A6
0 and bank activation control circuit 8 of both banks B70
The BL8 signal (the signal which becomes “H” when the burst length is “8”) supplied to the “8” is set to “H”.

The operation of the bank activation control circuit 88 of the bank A60 when a read command requesting to read data from the bank A60 is input in such a state will be described with reference to FIGS. I do.

As shown in FIG. 8B, an RD command is input in synchronization with the 0th rising edge, and an address (see FIG. 8C) for selecting bank A60 is input to ADD input circuit 85. It is assumed that it is supplied from.

The DFF elements 106 to 108 sequentially delay the output signal of the NOR element 103 in synchronization with the falling edge of the CLK signal and output the output signals as N1 to N3, respectively (FIG. 8 (H) to (J)). )reference).

The DFF element 109 latches the output signal of the NOR element 103 in synchronization with the falling edge of the CLK signal and outputs it as an output signal N4 (see FIG. 8 (K)).

At this time, the output of NAND element 105 of bank activation control circuit 88 of bank A60 is at "H" as shown in FIG.
The N5 signal, which is the output of the CMOS switch 111, is in the "L" state as shown in FIG.
The state becomes N. As a result, the N4 signal (see FIG. 8K) output from the DFF element 109 is selected, and this N4 signal is supplied to the timing circuit 89 as a BACT signal (see FIG. 8L).

The ADD latch 90 latches the ADD signal in synchronization with the rising edge of the RD / WR signal,
As a DD signal (see FIG. 8 (M)), the timing circuit 8
9.

The timing circuit 89 latches the BACT signal in synchronization with the rising edge of the BACT signal,
It is supplied to the bank A60 as an ADD signal (see FIG. 8 (N)).

As a result, the bank A60 reads out the data corresponding to the specified address and outputs it from the DATA output terminal (not shown) (see FIG. 8 (O)). At this time, in the bank activation control circuit 88 of the bank B70, the N5 signal (see FIG. 9E) is in the "H" state, and the N6 signal (see FIG. 9F) is in the "L" state. In this state, the output of the DFF element 108 is selected and supplied to the timing circuit 89.

The N3 signal (see FIG. 9 (J)) output from the DFF element 108 is obtained by delaying the N1 signal (see FIG. 9 (H)) by two cycles of the CLK signal.
The BADD signal (see FIG. 9 (M)) latched by the DD latch 90 is supplied to the bank A60 by the IADD signal.
Delayed from the signal by two periods of the CLK signal, IADD
The signal is supplied to the bank B70.

The bank B70 reads data stored at an address specified by the IADD signal supplied from the timing circuit 89, and outputs the data from a DATA output terminal (not shown) to the outside.

As a result, when the burst length is set to "8", first, data is read from the designated bank (bank A60 in the above example), and then only for two cycles of the CLK signal. With a delay, data is automatically read from another bank (bank B70 in the above example) (without re-input of an external address) and output to the outside.

Here, when the semiconductor memory device 30 is an auto-precharge type device, the auto-precharge is executed when the read operation from another bank is completed.

In the above example, the case where the bank A60 is specified first, and then the bank B70 is specified has been described. However, the case where the bank B70 is specified, and then the bank A60 is specified. A similar operation is performed, and 8-bit data is output.

The above is the operation in the case where the burst length is set to "8". When the burst length is set to "4" or less, any one of them is performed similarly to the conventional storage device. Data is read and output from only the bank.

That is, when the burst length is set to a value other than "8", the BL8 signal becomes "L", so that the outputs of the NAND elements 105 of the banks A60 and B70 are always "H". As a result, the CMOS 111 is turned on.

At this time, the output of the NOR element 104 becomes "L" when the bank managed by itself is designated, and becomes "H" otherwise. Accordingly, the NOR element 103 allows the RD / WR signal to pass only when the self element is selected, and shuts off when a bank other than the self element is specified.

As a result, when its own bank is designated, the signal output from DFF element 109
The signal is supplied to the timing circuit 89 as a signal, and the BADD signal latched by the ADD latch 90 is supplied to the bank as an IADD signal in synchronization with the rising edge.

Therefore, for example, when the burst length is set to "4", IADD is supplied only to the bank specified by the address specifying the bank, and the data stored at the corresponding address is read. Then, the data is output from a DATA output terminal (not shown) to the outside, where the operation is completed.

When the burst length is set to "8" and one of the banks is being accessed, the other bank cannot be accessed.
Executes a process for prohibiting such an interrupt request when an interrupt request is made to a bank other than the bank being accessed.

When the burst length is set to "8", the total time during which data is read from the two banks is the cycle time, so that control device 20 determines the cycle time according to the burst length. Then, control according to the control is performed.

In the above embodiment, the case where there are two banks has been described. However, it goes without saying that the present invention can be applied to the case where there are three or more banks. The circuits described in the above embodiments are only examples.
It goes without saying that the present invention is not limited to such a circuit.

[0083]

As described above, in the present invention, n (n
In the semiconductor memory device having> 1) banks, address input means for receiving an address and data corresponding to one address input via the address input means are transferred from m (≦ n) banks. A read unit for sequentially reading data and a data output unit for outputting data read from the m banks by the read unit to the outside as a set of data are provided, so that an optimal operation according to an application is performed. It can be realized.

Further, in an information processing apparatus having a semiconductor memory device having n (n> 1) banks and a control device for controlling the same, the semiconductor memory device comprises: an address input means for receiving an address; The data corresponding to one address input through the address input means is represented by m
Reading means for sequentially reading from (≦ n) banks;
Data output means for outputting data read from the m banks by the read means as a set of data to the outside, and the control device controls a cycle time determined according to a read cycle of the read means. Control means for controlling the semiconductor memory device in response to the data, and access inhibiting means for inhibiting access to a predetermined bank in accordance with the bank being read by the reading means. It is possible to realize an optimum operation even when an application that requires the above is executed.

[Brief description of the drawings]

FIG. 1 is a principle diagram for explaining the operation principle of the present invention.

FIG. 2 is a timing chart for explaining an outline of the operation of the principle diagram shown in FIG. 1;

FIG. 3 is a diagram illustrating a configuration example of an embodiment of the present invention.

FIG. 4 is a diagram showing a detailed configuration example of the semiconductor memory device shown in FIG. 3;

FIG. 5 is a diagram illustrating a detailed configuration example of a control unit illustrated in FIG. 4;

6 is a diagram showing a detailed configuration example of a bank activation control circuit, a timing circuit, and an ADD latch shown in FIG. 5;

FIG. 7 is a circuit diagram showing a detailed configuration example of the DFF element shown in FIG.

FIG. 8 is a timing chart for explaining the operation of the embodiment shown in FIG. 2;

FIG. 9 is a timing chart for explaining the operation of the embodiment shown in FIG. 2;

FIG. 10 is a timing chart for explaining an operation of a conventional semiconductor memory device.

FIG. 11 is a timing chart for explaining an operation of a conventional semiconductor memory device.

FIG. 12 is a timing chart for explaining an operation of a conventional semiconductor memory device.

FIG. 13 is a timing chart for explaining an operation of a conventional semiconductor memory device.

DESCRIPTION OF SYMBOLS 1 Address input means 2 Read means 3 Data output means 4 Output data amount setting means 5-1 to 5-n Bank 10 CPU 20 Control device 30 Semiconductor storage device 40 Bus 50 Control unit 60 Bank A 61 Cell 62 Column decoder 63 Row decoder 64 SA 65 I / O circuit 70 Bank B 71 cell 72 Column decoder 73 Row decoder 74 SA 75 I / O circuit 80 CLK input terminal 81 CMD input terminal 82 ADD input terminal 83 CLK input circuit 84 CMD input circuit 85 ADD input circuit 86 CMD decoder 87 Burst length judgment circuit 88 Bank activation control circuit 89 Timing circuit 90 ADD latch

Claims (5)

[Claims] 1. A semiconductor memory device having n (n> 1) banks, comprising: address input means for receiving an address; and data corresponding to one address input via the address input means. reading means for sequentially reading data from m (≦ n) banks; and data output means for outputting data read from the m banks by the reading means to the outside as a set of data. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein said read means sequentially reads data from said m banks at predetermined time intervals so that data congestion does not occur. 3. An output data amount setting means for setting an amount of data to be output by the data output means, wherein the reading means has a number corresponding to the data amount set by the output data amount setting means. 2. The semiconductor memory device according to claim 1, wherein data is sequentially read from the bank. 4. The semiconductor memory device according to claim 1, further comprising an auto-precharge means for automatically executing a pre-charge for each bank when an access to each bank is completed. 5. An information processing apparatus having a semiconductor memory device having n (n> 1) banks and a control device for controlling the semiconductor memory device, wherein the semiconductor memory device has an address input means for receiving an address input. Reading means for sequentially reading data corresponding to one address input from the address input means from m (≦ n) banks, and reading data read from the m banks by the reading means. Control means for controlling the semiconductor memory device according to a cycle time determined according to a read cycle of the read means. And an access prohibition unit for prohibiting access to a predetermined bank according to the bank from which the reading unit is reading. The information processing apparatus according to claim and.