JP2002270798A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely form the lower electrode of a stacked capacitor, which uses a high dielectric as a capacitance insulating film and which uses a platinum-group metal or the like for the lower electrode. SOLUTION: By a sputtering method, a lower-electrode formation film 15A, whose film thickness is about 20 nm and which is composed of platinum, is deposited over the whole face including the bottom face and the wall surface of openings 14a in an upper interlayer insulating film 14. In succession, by a spin coating method, a mask formation film 16A which contains, e.g. polyarylether which contains SOG is coated on the film 15, so as to fill the openings 14a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a concave capacitor.

[0002]

2. Description of the Related Art The design rules of semiconductor devices continue to shrink, and this is no exception in semiconductor memory devices. 2. Description of the Related Art A memory cell constituting a dynamic random access memory (DRAM) device, which is a kind of semiconductor memory device, includes a pass gate transistor (memory cell transistor) and a capacitor for storing capacitance.

In a DRAM device, in order to reduce power consumption and prevent soft errors, even if the memory cell is miniaturized and the projected area of the capacitor on the substrate is reduced, the storage capacity of the capacitor can be reduced. Can not. The storage capacitance of a capacitor is generally proportional to the relative dielectric constant of a dielectric film (capacitive insulating film) used for the capacitor and the area of a counter electrode opposed to the dielectric film, and is inversely proportional to the thickness of the dielectric film. I do.

If the thickness of the dielectric film is reduced in order to increase the storage capacity of the capacitor, the leakage current of the capacitor increases, so that it is necessary to shorten the refresh cycle of the memory cell. For this reason, power consumption increases, and there is a limit in reducing the thickness of the dielectric film used for the capacitor.

In order to increase the area of the counter electrode so as to compensate for the decrease in the projected area of the capacitor due to the miniaturization of the memory cell, a method of forming the capacitor into a three-dimensional structure has been adopted. Usually, silicon is used for a counter electrode of a capacitor, and an oxynitride film (O
N film).

Hereinafter, a method for manufacturing a semiconductor device having a concave type stack capacitor as a first conventional example using silicon for the counter electrode and an ON film for the dielectric film will be described with reference to the drawings.

FIGS. 6 (a) to 6 (d) and 7 (a),
FIG. 7B schematically illustrates a cross-sectional configuration in a process order of a method of manufacturing a semiconductor device according to a first conventional example.

First, an interlayer insulating film 102 made of silicon oxide (SiO ₂ ) is formed over the entire surface of a semiconductor substrate 101 on which a memory cell transistor (not shown) including a gate insulating film, a gate electrode, a source region and a drain region is formed. After that, connection holes for connecting to the source region of the memory cell transistor are provided in the interlayer insulating film 102 of the memory cell portion 1A, and a plug 103 made of silicon is formed in each connection hole. As shown.

Next, a capacitor forming insulating film 104 of silicon oxide having a thickness of about 1.2 μm is deposited on the interlayer insulating film 102, and subsequently, the capacitor forming insulating film 104 is formed by lithography and etching. An opening 104a for forming a counter electrode is formed in the film 104. The opening 104a has, for example, a short axis of 0.3 μm and a long axis of 0.9 μm.
6 (b), when it is formed so as to include the plug 103 on its bottom surface.

Next, a film thickness of about 7 is formed on the entire surface including the bottom surface and the wall surface of the opening 104a on the capacitor forming insulating film 104.
A lower electrode forming film 105A made of 0 nm amorphous silicon is deposited. Thereafter, a resist film 106 is formed on the lower electrode
When applied so as to fill 4a, it becomes as shown in FIG.

Next, the resist film 106 is etched back, and then the lower electrode forming film 10 is etched using the resist film 106 left inside the opening 104a as a mask.
5A is removed by etching to expose the upper surface of the capacitor forming insulating film 104, thereby forming the opening 104a.
When a lower electrode 105B made of amorphous silicon is formed on the bottom surface and the wall surface of FIG.

Next, as shown in FIG. 7A, the resist film 106 inside the opening 104a of the capacitor forming insulating film 104 is removed by ashing.
As shown in (b), an ON film 107 serving as a capacitive insulating film and an upper electrode forming film 108A made of amorphous silicon are sequentially deposited on the bottom surface and the wall surface of the opening 104a in the lower electrode 105B, and a concave type is formed. Stack capacitor can be realized.

Here, as shown in FIG. 6C, the thickness of the resist film 106 on the memory cell portion 1A is such that the opening portion 104a is filled with the resist film 106. It becomes smaller by about 0.3 μm than the thickness.

This film thickness difference d (hereinafter, referred to as an absolute step)
Has been confirmed to occur constantly when a film is formed by a spin coating method.

Lower electrode forming film 1 in peripheral circuit section 1B
05A must be completely removed. Therefore, when performing etch-back on the resist film 106, the resist film 106 on the peripheral circuit portion 1B must be reliably removed. As a result, the area on the resist film 106 in the memory cell section 1A is 0.1 mm larger than that in the peripheral circuit section 1B.
It will be over-etched by about 3 μm. However, the depth of the opening 104a of the capacitor forming insulating film 104 is about 1.2 μm, which is larger than the amount of over-etching, and the difference between the etching rates of the resist film 106 and the lower electrode forming film 105A is large. Therefore, even if such an absolute step d exists, a decrease in the storage capacity of the capacitor does not cause a significant problem.

In recent years, as a method of increasing the storage capacity of a capacitor, research has been conducted on using a dielectric material having a large relative dielectric constant for a capacitor insulating film of the capacitor. Examples of the high dielectric material having a large relative dielectric constant include metal oxides such as aluminum oxide (Al ₂ O ₃ ) and tantalum pentoxide (Ta ₂ O ₅ ), and a perovskite crystal structure having a higher relative dielectric constant. Large barium strontium titanium oxide (BST), lead zirconium titanium oxide (PZ
T), strontium bismuth tantalum oxide (S
Metal oxides such as BT).

Since a chemical reaction in an oxidizing atmosphere is generally used for forming these high dielectric materials, if silicon is used for the counter electrode as in the related art, the silicon is easily oxidized and the relative dielectric constant is reduced. Since a small silicon oxide film is formed, it is difficult to increase the storage capacity of the capacitor. Therefore, when such a high dielectric material is used as a capacitor insulating film, a noble metal (a platinum group metal) or a high melting point metal is used for the counter electrode.

In addition, when the design rule of the semiconductor device is 0.
If the size is reduced to about 15 μm or less, it is necessary to increase the area of the counter electrode even in a capacitor using a high dielectric material for the capacitor insulating film. It needs to be structured.

[0019]

Problems to be Solved by the Invention FIGS. 8A to 8
(D) shows a cross-sectional configuration in a process order of a method of manufacturing a semiconductor device having a concave-type stack capacitor according to a second conventional example using platinum as a counter electrode and a high dielectric as a dielectric film. I have.

First, as shown in FIG. 8A, an interlayer insulating film 102 made of silicon oxide is deposited on the entire surface of a semiconductor substrate 101 in the same manner as in the first conventional example. Connection holes for connecting to the source region of the memory cell transistor are provided in the interlayer insulating film 102, and a plug 103 made of silicon is formed in each connection hole. Subsequently, a capacitor forming insulating film 114 made of silicon oxide having a thickness of about 0.3 μm is deposited on the interlayer insulating film 102, and an opening for forming a counter electrode is formed on the deposited capacitor forming insulating film 114. The portion 114a is formed to include the plug 103 on the bottom surface.

Next, as shown in FIG. 8B, a lower electrode forming film 115 made of platinum having a thickness of about 20 nm is formed on the entire surface of the capacitor forming insulating film 114 including the opening 114a.
Then, a resist film 116 is applied on the lower electrode formation film 115A by a spin coating method so as to fill the opening 114a. At this time, the absolute step of the resist film 116 is about 0.3 μm.

Thereafter, when the resist film 116 is etched back, the absolute step and the film thickness of the capacitor forming insulating film 114 become substantially the same, and therefore, as shown in FIG. The resist film 116 inside is removed. As a result, the lower electrode forming film 115A
8D, the lower electrode forming film 115A inside the opening 114a is formed as shown in FIG.
Is etched, the lower electrode 115B remains only on the side surface of the opening 114a.
Since 15B cannot come into contact with the plug 103, it cannot function as an electrode.

As described above, in the manufacturing method according to the first conventional example, a high dielectric material is used for the capacitive insulating film and a platinum group metal material or a high melting point metal material is used for the lower electrode. There is a problem that the lower electrode 115B cannot be manufactured.

That is, in the case of the first conventional example in which silicon is used for the lower electrode 105B and the ON film 107 is used for the capacitor insulating film, since the relative dielectric constant is small, the film thickness of the capacitor forming insulating film 104, that is, Opening (concave) 10
4a is required to be about 1.0 μm to 2.0 μm, whereas in the second conventional example using a high dielectric material for the capacitance insulating film, the relative dielectric constant of the capacitance insulating film is ON. The opening 114a has a depth of 0.2 μm because it is sufficiently larger than the film.
It will be better if it is about m to 1.0 μm.

For this reason, when the absolute step of the resist film 116 formed by the spin coating method is, for example, about 0.3 μm and about the same as the depth of the opening 114a, the resist film of the peripheral circuit section 1B If the layer 116 is completely removed by etch back or the like, the resist film 116 that masks the wall surface of the opening 114a is almost completely removed. As a result, the lower electrode 115B is formed from the lower electrode forming film 115A. When patterning is performed, the lower electrode 115B has a shape that does not function as an electrode.

The present invention solves the above-mentioned conventional problems, and makes it possible to reliably form a lower electrode of a stack type capacitor using a high dielectric material for a capacitive insulating film and a platinum group metal or the like for a lower electrode. The purpose is to:

[0027]

In order to achieve the above object, the present invention provides a method of using a glass coating film by a spin coating method for a sacrificial film for masking a wall surface of an opening (concave), or using a chemical vapor deposition method. A configuration using a deposition film formed by a growth method is employed.

More specifically, the first method for manufacturing a semiconductor device according to the present invention is based on the premise that a method for manufacturing a semiconductor device in which a memory cell portion and a peripheral circuit portion are formed on a substrate, and an insulating film is formed on the substrate. A first step of depositing, a second step of forming an opening for forming a capacitor in the insulating film in the memory cell portion, and forming a platinum group metal or a platinum group metal on the insulating film including the bottom and wall surfaces of the opening. A third step of forming a first conductor film made of a metal oxide or a high melting point metal, and a fourth step of forming a sacrificial film made of a glass coating film on the first conductor film including the inside of the opening. A fifth step of removing the sacrificial film and the first conductor film so that the upper surface of the insulating film is exposed; a sixth step of removing the sacrificial film inside the opening; A seventh step of forming a capacitive insulating film on the bottom surface and the wall surface of the opening; And a eighth step of forming a second conductive film on the amounts insulating film.

The first method for manufacturing a semiconductor device is characterized in that a glass coating film (SOG film) is used as a sacrificial film of the first conductor film, and the glass coating film is smaller than the viscosity of the resist film. The absolute step of the sacrificial film formed on the insulating film for formation can be reliably reduced.

On the other hand, simply forming the sacrificial film by lowering the viscosity of the conventional resist film results in the resist film being applied directly to the surface of the first conductor film made of metal to be the lower electrode, The resist film is easily left on the first conductor film. In particular, in the case where a platinum group metal is used for the first conductor film, the platinum group metal acts as a catalyst to harden the resist film more than necessary during the baking step of the resist film. It becomes even more difficult. However, in the first method for manufacturing a semiconductor device, a glass coating film is used as the sacrificial film of the first conductive film made of metal, so that the sacrificial film can be easily and reliably removed.

In the first method for manufacturing a semiconductor device, the sacrificial film is preferably made of a material containing polyallyl ether. By doing so, the viscosity can be reduced more easily than with a normal resist film, and it can be removed by ashing as with a normal resist film. Therefore, in this case, it is preferable that the sixth step includes a step of removing the sacrificial film using oxygen plasma.

In the first method for manufacturing a semiconductor device, the sacrificial film is preferably made of a material containing silanol.
As described above, even when silanol is contained, the viscosity can be reduced more easily than in a normal resist film. In this case, it is preferable that the sixth step includes a step of removing the sacrificial film by using hydrogen fluoride water.

Further, when the sacrificial film is made of a material containing silanol, it is preferable that at least the upper part of the insulating film is made of a silicon nitride film. With this configuration, when silicon oxide is used for the insulating film for forming the capacitor, the silicon nitride film can be used as an etching stopper for the sacrificial film because the main component of the sacrificial film containing silanol is also silicon oxide.

A second method for manufacturing a semiconductor device according to the present invention is based on a method for manufacturing a semiconductor device in which a memory cell portion and a peripheral circuit portion are formed on a substrate, and a first method for depositing an insulating film on a substrate. And a second step of forming an opening for forming a capacitor in the insulating film in the memory cell portion, and forming a platinum group metal or its metal oxide on the insulating film including the bottom surface and the wall surface of the opening. A third step of forming a first conductor film made of a refractory metal, and a first step including the inside of the opening.
A fourth step of forming a sacrificial film on the conductive film by chemical vapor deposition, a fifth step of removing the sacrificial film and the first conductive film so that the upper surface of the insulating film is exposed, A sixth step of removing the sacrificial film inside the portion, a seventh step of forming a capacitive insulating film on the bottom and wall surfaces of the opening in the first conductive film, and a second conductor on the capacitive insulating film. Eighth to form a film
Steps.

In the first method for manufacturing a semiconductor device, since a glass coating film is used as a sacrificial film, cracks are likely to occur when the thickness is increased. Therefore, in the second method for manufacturing a semiconductor device, the thickness of the sacrificial film can be optimized by using a deposited film formed by a chemical vapor deposition method instead of the glass coating film.

In the second method for manufacturing a semiconductor device, the fourth step preferably includes a step of forming a sacrificial film at a temperature of about 500 ° C. to 600 ° C. using ozone and TEOS as raw materials. With this configuration, the opening of the insulating film for forming the capacitor can be reliably filled with the sacrificial film,
The sacrifice film can be more easily embedded in the opening.

In this case, ozone is generated from oxygen,
Preferably, the weight concentration of the generated ozone with respect to oxygen is about 7% or more. By doing so, the embedding property into the opening is further improved.

In the first or second method for manufacturing a semiconductor device, it is preferable that the capacitance insulating film is made of a high dielectric or ferroelectric. By doing so, the capacity of the capacitor can be increased.

In the first or second method for manufacturing a semiconductor device, it is preferable that the fifth step is a step performed using dry etching.

In the method of manufacturing the first or second semiconductor device, it is preferable that the fifth step includes a step of polishing the sacrificial film or the first conductor film by a chemical mechanical polishing method.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION The inventors of the present invention produce a sacrifice film formed of a spin-on-glass (SOG) film by a spin coating method on a film provided with an opening (concave). As a result of repeated studies on the absolute step,
The knowledge as shown in FIG. 1 has been obtained.

FIG. 1 is a graph showing the relationship between the thickness of the SOG film, the depth of the concave, and the absolute step amount of the SOG film. Here, a silanol (Si (OH) ₄ ) -based SOG film is selected as the material of the coating film by the spin coating method, and the thickness of the SOG film and the depth of the concave filling the SOG film are changed to change the SOG film The absolute step amount on the upper surface of is measured.

Each of the substrate and the concave formation film provided on the substrate has a minor axis of about 0.13 μm and a major axis of about 0.4
A plurality of concaves having an elliptical shape of μm are formed, and an empty region having an area of about 2 mm ^{2 where} no concave is formed is formed. At this time, the area occupied by the concave formation region with respect to the substrate is about 40%. This value substantially reflects the actual projected area of the capacitor of the DRAM memory cell. Further, the absolute step amount is a difference between the thickness of the SOG film formed in the empty region and the thickness of the SOG film from the upper end of the concave formed in the concave formation region.

As shown in FIG. 1, when the depth of the concave is 0.3 μm, the thickness of the SOG film is 500 nm,
The absolute steps at 600 nm and 700 nm are S
The thickness is approximately 120 nm regardless of the thickness of the OG film.

When the thickness of the SOG film is 600 nm, the absolute step difference when the depth of the concave is 0.3 μm, 0.4 μm and 0.5 μm is 120 n in order.
m, 150 nm and 200 nm.

From the above, it can be seen that even when the thickness of the SOG film is increased, the absolute step amount hardly decreases, and the absolute step amount increases as the depth of the concave increases.

When the depth dimension of the concave is increased, the area of the lower electrode is increased and the capacitance of the capacitor is increased.
For this reason, as the miniaturization of the semiconductor device progresses and the miniaturization of the concave accompanying the reduction in the area of the memory cell progresses, in order to maintain a predetermined value of the capacitance of the capacitor, the depth of the concave is increased. , It is necessary to increase the area of the lower electrode. However, when the hole depth is increased, the absolute step height increases, and it becomes more difficult to form a concave-type lower electrode.

Here, if a deposited film using a chemical vapor deposition method is used for the sacrificial film instead of the spin coating method, the coverage of the deposited film is about 60% to 100%. The absolute step height does not depend on the depth of the concave,
It has also been found that it can be suppressed to about 50 nm. Since a deposited film formed by the chemical vapor deposition method needs to be filled in a miniaturized concave, it is desired that the film be excellent in embedding property. For example, a deposition film formed by a chemical vapor deposition (CVD) method using TEOS (tetraethyl orthosilicate) and ozone (O ₃ ) as raw materials is preferable because of excellent embedding property.

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIGS. 2 (a) to 2 (d) and 3 (a),
FIG. 3B schematically shows a cross-sectional configuration in a process order of the method for manufacturing the capacitor of the DRAM device according to the first embodiment of the present invention.

First, a memory cell transistor (not shown) having a MISFET structure including a gate insulating film, a gate electrode, a source region and a drain region is formed on a semiconductor substrate 11 made of, for example, silicon (Si). A lower interlayer insulating film 12 made of silicon oxide is deposited over the entire surface including the portion 1A and the peripheral circuit portion 1B.
Thereafter, the lower interlayer insulating film 12 in the memory cell portion 1A is formed by using a lithography method and a dry etching method.
After a plurality of connection holes having a diameter of about 0.15 μm are provided in the source region of the memory cell transistor, each connection hole is filled with polysilicon to form a plug 13, and the state shown in FIG. 2A is obtained.

Next, as shown in FIG. 2B, a capacitor is formed on the entire surface including the plug 13 on the lower interlayer insulating film 12 by, for example, silicon oxide having a thickness of about 0.4 μm by CVD. Of the upper interlayer insulating film 14 is deposited. Subsequently, for example, a short axis is about 0.13 μm and a long axis is about 0.1 mm for forming a counter electrode on the upper interlayer insulating film 14 by lithography and dry etching.
A plurality of openings (concave) 14a of about 4 μm are formed on the respective bottom surfaces so as to include the plugs 13 respectively.

Since the lower interlayer insulating film 12 and the upper interlayer insulating film 14 are both made of silicon oxide, the opening 14
As an etching stopper of a, a silicon nitride film is preferably provided between the lower interlayer insulating film 12 and the upper interlayer insulating film 14.

Next, the opening 14a is formed by sputtering.
Titanium (Ti) (not shown) is deposited on the entire surface of the upper interlayer insulating film 14 including the bottom surface and the wall surface, and a lower electrode forming film 15A made of platinum (Pt) having a thickness of about 20 nm.
Is deposited.

Subsequently, an SO containing polyallyl ether as a main component is formed on the lower electrode forming film 15A by spin coating.
The sacrificial film 16A made of G is formed so that the film thickness in the peripheral circuit portion 1B becomes about 600 nm and the upper interlayer insulating film 1A is formed.
4 is applied so as to fill each opening 14a. Thereafter, when sintering (baking) is performed on the sacrificial film 16A at a heating temperature of about 400 ° C., the sacrificial film 16A becomes a polyallyl ether film, and is in the state shown in FIG. 2C. Generally, the viscosity of the resist is several tens cP (centipoise), but the viscosity of the SOG is about 0.7 cP to 15 cP, which is smaller than that of the resist. The absolute step amount with the film thickness can be reduced.

At this time, the absolute difference between the thickness of the memory cell portion 1A and the thickness of the peripheral circuit portion 1B in the sacrificial film 16A is about 150 nm.

Next, a fluorocarbon gas such as a C ₄ F ₈ gas and a CHF ₃ gas and an oxygen (O ₂ ) gas are used as an etching gas by an inductively coupled plasma etching apparatus.
Source power is about 500W and bias power is 5
Etchback is performed on the sacrificial film 16A under etching conditions of about 0 W and a pressure of about 60 Pa. Subsequently, an argon (Ar) gas, an oxygen (O ₂ ) gas and a chlorine (Cl ₂ ) gas are used as an etching gas in the same inductively coupled plasma etching apparatus, and the source power is set to 500.
W, the bias power is about 50 W, and the pressure is about 40 Pa.
When the lower electrode 15B is formed from the lower electrode forming film 15A by performing etch-back on 5A, FIG.
As shown in FIG.

Here, in order to expose the upper surface of the upper interlayer insulating film 14, instead of etching the sacrificial film 16A and the lower electrode forming film 15A, a chemical mechanical polishing (CMP) method may be used. good.

Next, as shown in FIG. 3A, the sacrifice film 16B remaining inside the opening 14a is removed by ashing with oxygen plasma, similarly to a normal resist material.

Next, as shown in FIG. 3B, a capacitive insulating film 17 made of, for example, BST is deposited on the bottom surface and the wall surface of each opening 14a in the lower electrode 15B by the CVD method or the sputtering method. , Followed by sputtering or CV
An upper electrode forming film 18A made of platinum is deposited on the capacitor insulating film 17 by the method D.

Thereafter, the upper electrode forming film 18A is patterned into a predetermined shape, and further, wiring is formed to form a concave stack capacitor.

When a resist material having a relatively high viscosity is used for the sacrificial film 16A as in the prior art, it becomes difficult to reliably embed the resist material in the finer openings 14a. Even if the viscosity of the resist material is reduced, since the lower electrode forming film 15A is made of platinum,
At the time of baking or ashing of the resist material, the platinum becomes a catalyst to harden the resist material more than necessary, so that the resist material is easily left when the resist material is removed. If a residue is left, the capacitor insulating film 17 formed in a later step is formed.
And the lower electrode 15B do not adhere to each other, and a predetermined capacitance value cannot be obtained in the capacitor.

On the other hand, in the first embodiment, polyallyl ether is used for the sacrificial film 16A. Since polyallyl ether is less susceptible to the catalytic effect of platinum, no residue is generated by the oxygen plasma treatment for removing the sacrificial film 16B, and a predetermined capacitance value can be obtained in the capacitor.

The SOG film constituting the sacrificial film 16A is not limited to polyallyl ether, and may be formed by dissolving hydrogensiloxane (HSQ) as inorganic SOG or polymethylsiloxane as organic SOG in an organic solvent. Good.

In general, the properties of the SOG film almost reflect the properties of the solute material, and by changing the solute material,
Since the properties of the G film can be changed, for example, when the organic component of the solute is increased, the removal by ashing with oxygen plasma becomes easier.

When a silanol-based SOG film is used, it can be easily removed by using an aqueous solution of hydrogen fluoride (HF) instead of oxygen plasma. Here, when silicon oxide is used for the upper interlayer insulating film 14, the upper interlayer insulating film 14 is also etched at the same time. Is desirable.

The following combinations of the capacitance insulating film 17 and the lower electrode 15B are preferable.

(1) When the capacitance insulating film 17 is BST, the lower electrode 15B is made of platinum or ruthenium (Ru) which is a platinum group, or ruthenium dioxide (Ru) which is an oxide thereof.
O ₂ ) or iridium (Ir).

(2) When tantalum pentoxide is used for the capacitance insulating film 17, the lower electrode 15B may be made of platinum group ruthenium or refractory metal tungsten (W), molybdenum (M
o) or tungsten nitride (WN).

(3) SBT or PZT is formed on the capacitance insulating film 17.
Is used, the lower electrode 15B is made of platinum, iridium, or iridium dioxide (IrO ₂ ) which is an oxide thereof.

In this case, the semiconductor device is a DRAM device, but the present invention is not limited to this, and it goes without saying that the present invention can be applied to a ferroelectric memory device.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 4 (a) to 4 (d) and 5 (a),
FIG. 5B schematically illustrates a cross-sectional configuration in a process order of a method for manufacturing a capacitor of a DRAM device according to a second embodiment of the present invention.

First, a memory cell transistor (not shown) having a MISFET structure including a gate insulating film, a gate electrode, a source region and a drain region is formed on a semiconductor substrate 21 made of, for example, silicon (Si). A lower interlayer insulating film 22 made of silicon oxide is deposited over the entire surface including the portion 1A and the peripheral circuit portion 1B.
Thereafter, the lower interlayer insulating film 22 in the memory cell portion 1A is formed by lithography and dry etching.
When a plurality of connection holes having a diameter of about 0.15 μm are provided in the source region of the memory cell transistor, and each connection hole is filled with polysilicon to form a plug 23, a state shown in FIG.

Next, the lower interlayer insulating film 2 is formed by the CVD method.
For example, a first upper interlayer insulating film 24 made of silicon oxide having a thickness of about 0.3 μm and a second upper interlayer insulating film made of silicon nitride having a thickness of about 0.1 μm By sequentially depositing a film 25, a first upper interlayer insulating film 24 and a second upper interlayer insulating film 25 are formed.
An upper interlayer insulating film 26 for forming a capacitor is formed. Here, the second upper interlayer insulating film 25 is
Since both 8A and 28B and the first upper interlayer insulating film 24 are made of silicon oxide, the first upper interlayer insulating film 24 is provided so as not to be etched when the sacrificial film 28B is removed in a later step.

Subsequently, a plurality of openings having a short axis of about 0.13 μm and a long axis of about 0.4 μm for forming a counter electrode on the upper interlayer insulating film 26 by lithography and dry etching, for example. When the portions (concave) 26a are formed to include the plugs 23 on the respective bottom surfaces,
The state shown in FIG.

A silicon nitride film may be further provided between the lower interlayer insulating film 22 and the first upper interlayer insulating film 24 as an etching stopper for the opening 26a.

Next, as shown in FIG. 4C, titanium (not shown) is deposited on the entire surface of the upper interlayer insulating film 26 including the bottom surface and the wall surface of the opening 26a by sputtering.
Further, a lower electrode forming film 27A made of platinum having a thickness of about 20 nm is deposited.

Subsequently, a sacrificial film 28A made of silicon oxide is filled on the lower electrode forming film 27A to fill each opening 26a of the upper interlayer insulating film 26 by using a CVD method using TEOS and ozone as raw materials. Deposited on As a result, the film thickness on the peripheral circuit section 1B is about 600 nm, and the film thickness on the memory cell section 1A is about 550 nm. At this time, the film forming conditions of the sacrificial film 28A are such that the substrate temperature is about 540 ° C.
The flow rate of TEOS is about 600 mg / min (standard condition),
The flow rate of oxygen is about 8 L / min. In addition, ozone is generated by irradiating oxygen with ultraviolet rays, and the weight concentration of the generated ozone with respect to oxygen is set to 12%. As described above, it has been confirmed that when the weight concentration of ozone in oxygen is about 7% or more, the embedding property into the opening 26a is improved.

Next, the sacrificial film 28A is etched back and removed to expose the lower electrode forming film 27A. Sacrificial film 28A
Is used a fluorocarbon gas such as a C ₄ F ₈ gas or a CHF ₃ gas. At this time, the sacrificial film 28B remains inside each opening 26a of the upper interlayer insulating film 26. Subsequently, the lower electrode forming film 27 is formed using the sacrificial film 28B.
A is dry-etched with an argon gas, an oxygen gas and a chlorine gas so that the lower electrode forming film 27 is formed.
A, the lower electrode 2 is formed on the bottom surface and the wall surface of each opening 26a.
When each of 7B is formed, the state shown in FIG. Here, in order to expose the upper surface of the upper interlayer insulating film 26, instead of etching the sacrificial film 28A and the lower electrode forming film 27A, chemical mechanical polishing (CMP) is performed.
Method may be used.

Next, as shown in FIG. 5A, an aqueous solution of hydrogen fluoride is etched to remove the sacrificial film 28B remaining inside each opening 26a of the upper interlayer insulating film 26. At this time, since the second upper interlayer insulating film 25 made of silicon nitride is provided on the upper interlayer insulating film 26, the upper interlayer insulating film 26 is not etched.

Next, a capacitive insulating film 29 made of, for example, BST is deposited on the bottom surface and the wall surface of the opening 26a by the CVD method or the sputtering method.
An upper electrode forming film 30 made of platinum is deposited on the capacitor insulating film 29 by the VD method. Then, the upper electrode forming film 3
By patterning 0 into a predetermined shape and further forming a wiring, a concave stack capacitor is formed, as shown in FIG. 5B.

As described above, according to the second embodiment, the sacrificial film 28A for forming the lower electrode 27B is a deposited film formed by the CVD method.
Does not cause cracking in the sacrificial film 28A.

Although the semiconductor device is a DRAM device, the present invention can be applied to a ferroelectric memory device instead.

[0085]

According to the method of manufacturing a semiconductor device of the present invention, a first conductor film made of a platinum group metal or a high melting point metal is reliably formed in an opening (a concave) of an insulating film for forming a capacitor. can do.

[Brief description of the drawings]

FIG. 1 is a view showing a semiconductor device manufacturing method according to the present invention;
6 is a graph showing the relationship between the thickness of the OG film, the depth of the concave, and the absolute step amount of the SOG film.

FIGS. 2A to 2D are schematic cross-sectional views in the order of steps showing a method for manufacturing a capacitor of the semiconductor device according to the first embodiment of the present invention.

FIGS. 3A and 3B are schematic cross-sectional views illustrating a method for manufacturing a capacitor of the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIGS. 4A to 4D are schematic sectional views in the order of steps showing a method for manufacturing a capacitor of a semiconductor device according to a second embodiment of the present invention.

FIGS. 5A and 5B are schematic cross-sectional views in a process order illustrating a method for manufacturing a capacitor of a semiconductor device according to a second embodiment of the present invention.

FIGS. 6A to 6D are schematic sectional views in the order of steps showing a method for manufacturing a capacitor of a semiconductor device according to a first conventional example.

FIGS. 7A and 7B are schematic sectional views in the order of steps showing a method for manufacturing a capacitor of a semiconductor device according to a first conventional example.

FIGS. 8A to 8D are schematic sectional views in the order of steps showing a method for manufacturing a capacitor of a semiconductor device according to a second conventional example.

[Explanation of symbols]

 1A Memory cell section 1B Peripheral circuit section 11 Semiconductor substrate 12 Lower interlayer insulating film 13 Plug 14 Upper interlayer insulating film 14a Opening (concave) 15A Lower electrode forming film 15B Lower electrode 16A Sacrificial film 16B Sacrificial film 17 Capacitive insulating film 18A Upper electrode Forming film 21 Semiconductor substrate 22 Lower interlayer insulating film 23 Plug 24 First upper interlayer insulating film 25 Second upper interlayer insulating film 26 Upper interlayer insulating film 26a Opening (concave) 27A Lower electrode forming film 27B Lower electrode 28A Sacrificial film 28B Sacrifice Film 29 Capacitive insulating film 30 Upper electrode forming film

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Atsushi Shibata 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5F083 AD24 JA14 JA38 JA39 JA40 JA43 MA06 MA17 NA08 PR39 PR40

Claims (12)

[Claims] 1. A method for manufacturing a semiconductor device in which a memory cell portion and a peripheral circuit portion are formed on a substrate, wherein: a first step of depositing an insulating film on the substrate; A second step of forming an opening for forming a capacitor; and a first conductor made of a platinum group metal, a metal oxide thereof, or a refractory metal on the insulating film including a bottom surface and a wall surface of the opening. A third step of forming a film, a fourth step of forming a sacrificial film made of a glass coating film on the first conductive film including the inside of the opening, and exposing an upper surface of the insulating film. The sacrificial film and the first
A fifth step of removing the conductive film, a sixth step of removing the sacrificial film inside the opening, and forming a capacitive insulating film on a bottom surface and a wall surface of the opening in the first conductive film. A method of manufacturing a semiconductor device, comprising: a seventh step of forming a second conductive film on the capacitive insulating film. 2. The method according to claim 1, wherein the sacrificial film is made of a material containing polyallyl ether. 3. The method according to claim 1, wherein the sixth step includes a step of removing the sacrificial film using oxygen plasma. 4. The method according to claim 1, wherein the sacrificial film is made of a material containing silanol. 5. The method according to claim 4, wherein the sixth step includes a step of removing the sacrificial film using a hydrogen fluoride solution. 6. The method according to claim 5, wherein at least an upper portion of the insulating film is made of a silicon nitride film. 7. A method for manufacturing a semiconductor device in which a memory cell portion and a peripheral circuit portion are formed on a substrate, wherein: a first step of depositing an insulating film on the substrate; A second step of forming an opening for forming a capacitor; and a first conductor made of a platinum group metal, a metal oxide thereof, or a refractory metal on the insulating film including a bottom surface and a wall surface of the opening. A third step of forming a film, a fourth step of forming a sacrificial film on the first conductor film including the inside of the opening by chemical vapor deposition, and an upper surface of the insulating film is exposed. The sacrificial film and the first
A fifth step of removing the conductive film, a sixth step of removing the sacrificial film inside the opening, and forming a capacitive insulating film on a bottom surface and a wall surface of the opening in the first conductive film. A method of manufacturing a semiconductor device, comprising: a seventh step of forming a second conductive film on the capacitive insulating film. 8. The semiconductor according to claim 7, wherein said fourth step includes a step of forming said sacrificial film at a temperature of about 500 ° C. to 600 ° C. using ozone and TEOS as raw materials. Device manufacturing method. 9. The method according to claim 8, wherein the ozone is generated from oxygen, and a weight concentration of the generated ozone with respect to oxygen is about 7% or more. 10. The capacitor insulating film according to claim 1, wherein the capacitor insulating film is made of a high dielectric or a ferroelectric.
13. The method for manufacturing a semiconductor device according to the above item. 11. The method according to claim 1, wherein the fifth step is a step performed using dry etching.
0. The method of manufacturing a semiconductor device according to claim 1, wherein 12. The method according to claim 1, wherein the fifth step includes a step of polishing the sacrificial film or the first conductor film by a chemical mechanical polishing method.
13. The method for manufacturing a semiconductor device according to the above item.