JP2002261098A - Formation method of copper seed layer in ulsi metallization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a formation method of copper seed layer in ULSI metallization which is simple at a low cost, suitable for a substrate having a via with a large aspect ratio and can prevent problems generated by a reactive by- products. SOLUTION: A diffusion barrier layer is formed in a substrate. A replacing layer is formed in a diffusion barrier layer, and a part of a replacing layer is replaced with a thin copper film in mixture solution including a replacing reactant. Activation copper ion and a substance restraining oxidation of silicon are incorporated in mixture solution. A replacing layer is formed of a polysilicon layer, a non-crsytalline silicon layer or a TaSix layer. A diffusion barrier layer is formed of a TiN layer, a Ta layer, a TaN layer or a TaSix layer. A substrate has a plurality of vias and trenches. Mixture solution contains CuSO4 .5H2 O and HF. A copper layer is plated on a thin copper film. Since etchant is incorporated in mixture solution for carrying out replacement, formation of by-products of reaction is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

(Technical field to which the invention pertains)
The present invention relates to a method for forming a copper seed layer in SI metallization, and more particularly to a method for forming a copper seed layer by replacing a polysilicon layer, an amorphous silicon layer, or a TaSix layer.

(Background of the Invention) In the ULSI manufacturing process, RC
In order to reduce the delay time, it is necessary to form a copper layer instead of aluminum. In order to make the cost relatively low, an electroplating process of a copper layer is used in industry. In the copper layer electroplating process, before the copper layer is plated on the wafer, a seed layer is formed on the surface of the wafer to form an excellent electrode surface, thereby forming a high quality plating layer.
The seed layer is a thin copper layer on the surface on which the metal layer is plated. The seed layer is formed on the surface of the silicon dioxide or the wafer. However, when vias with a large aspect ratio are present on the surface of the wafer, a seed layer physical vapor deposition (PVD) mismatch occurs. To solve this problem, chemical vapor deposition (CVD) is used.

[0003] Christine Whitman et al.
OCVD-Cu process, electrochemical formation or MOCV
It has been shown that it is possible to form a uniform and low-resistance copper seed layer by sufficient deposition of the continuous copper filling with D. (Christine Whitman, Mehrdad M. Mosleh
i, Ajit Paranjpe, Lino Velo, Tom Omstead, J. Va
c. Sci. Technol. A 17 (4), 1893, 19
99) Although the CVD process can form a suitable copper seed layer, the cost is high and it is not possible to reduce the manufacturing cost of ULSI.

[0004] Robert Mikkola et al. Disclosed a method of forming a copper seed layer by PVD forming a copper seed layer of 1000 銅 on a tantalum layer of 200Å. According to their experiments, when the thickness of the copper layer on the sidewall of the via is 1000 °, the via can be filled with a diameter of 0.25 μm and an aspect ratio of 4. The resistance of the tuned layer is 0.25
μΩ-cm. 40 hours at room temperature or 2 hours at 80 ° C
After self-annealing for 0 minutes, the resistance is 1.85 μΩ-
cm (RD Mikkola et al., “Electroplating of Copper with Advanced Interconnection Technology,” Plating and Surf
ace Finishing, March 2000 P81).
However, the above-described method, when filling a via with a high aspect ratio, requires a step coverage of the PVD film.
coverage) is a problem.

Yuri Lantasov et al. Have disclosed a power saving electroplating method in which the activated palladium deposit is replaced with copper to form a seed layer. According to Lantasov et al., This method can fill vias on a wafer with a via diameter of 0.35 μm and an aspect ratio of 3. However, the above method is not suitable for wafers with high aspect ratio vias because the palladium layer is sputtered on the surface of the wafer (Yuri Lantasov et al. New plating bath for forming "Microelectronic Engineering
50, 2000, p441).

MJ Shaw applies pressure at 240 ° C.
Photo CV using Cu (hfac) ² as reactant
Announced a method to form a copper film directly on a silicon underlayer using D technology (MC Shiao, “Si under pressure.
Study on selective copper film formation on (100) substrate "National
Chiao Tung University, MSECG, 1998,
pt 1: 2). However, in the aforementioned studies, the resistance of the copper film is adjusted to 8.88 μΩ-cm.

MK Lee et al. Have disclosed a method of chemically replacing silicon with copper to form a copper film at room temperature.
When the thickness of the copper film is 5000 °, the low resistance 2.16
μΩ-cm can be obtained (MK Lee et al. “Copper film formation on silicon using lead copper sulfate and hydrogen fluoride” Journal
of Electrochemical Society, Vol. 144, No.
5, May 1997). According to the report, Lee et al. Did not consider the presence of a diffusion barrier and a copper interconnect adhesion layer. Therefore, a step of suppressing the diffusion of copper is required.

(Object of the Invention) The object of the present invention is to
An object of the present invention is to provide a method of forming a copper seed layer in ULSI metallization, which is low-cost and simple. Another object of the present invention is to provide a method for forming a copper seed layer in ULSI metallization, which is suitable for a substrate having a via having a large aspect ratio. It is another object of the present invention to provide a method for forming a copper seed layer in ULSI metallization, which can prevent problems caused by reaction by-products.

(Summary of the Invention) ULS according to the claims of the present invention
According to the method of forming a copper seed layer in I-metallization, the substrate is adjusted and a diffusion barrier layer is formed on the substrate. A substitution layer is formed on the diffusion barrier layer, and a part of the substitution layer is substituted with a thin copper film in a mixed solution containing a substitution reactant. The mixture contains activated copper ions and a substance that reduces oxidation of silicon. The replacement layer is formed of a polysilicon layer, an amorphous silicon layer, or a TaSix layer. The diffusion barrier layer is formed of a TiN layer, a tantalum layer, or a TaN layer. Alternatively, the diffusion barrier layer is formed of a TaSix layer. A plurality of vias and trenches are formed in the substrate. The mixed solution is CuSO ₄
- and a 5H ₂ O and HF. Plating a copper layer on the thin copper film. Since the mixture to be replaced contains ethylene, formation of by-products of the reaction is prevented.

(Detailed Description of the Invention) Hereinafter, a method for forming a copper seed layer in the ULSI metallization of the present invention will be described in detail. The present invention is used in various ULSI metallization processes. The application of the invention described below is one embodiment for illustrative purposes. However, the scope of the present invention is not limited to the embodiment.

As shown in FIG. 1, according to a method of forming a copper seed layer in ULSI metallization according to one embodiment of the present invention, in step (a), a substrate having vias and trenches is prepared. Below the vias and trenches are metal interconnects. The material of the substrate is an insulating material suitable for the metallization process. Usually, silicon dioxide is used for the material of the substrate. The vias and trenches in the substrate are formed by chemical etching or other etching techniques. Alternatively, vias and trenches may be formed in the substrate by another technique. The method of forming vias and trenches is determined by the material of the substrate and the conditions required for preparation or application. Detailed description of this step is omitted.

In a step (b), a barrier layer is formed on the substrate. A suitable material for the barrier layer is TiN, TaN or tantalum. The thickness of the barrier layer is about 500 °. When the material of the barrier layer is TiN, a barrier is formed on the substrate by the LPCVD technique. When the material of the barrier layer is tantalum, a barrier is formed on the substrate by sputtering or CVD technology. Other techniques for forming a diffusion layer on a substrate are also suitable for the present invention.

Then, a polysilicon layer is formed on the diffusion barrier layer. In this step, in the LPCVD reactor,
A polysilicon layer is formed on the diffusion barrier layer at 590 ° C. and 170 mmtorr (22.6 Pa). The thickness of the polysilicon layer is about 650 °. In another embodiment, an amorphous silicon layer is formed on the surface of the diffusion barrier layer by a PECVD technique.

In step (c), the formed product prepared as described above is immersed in the replacement solution. The replacement solution contains copper ions so that the polysilicon layer is replaced by copper. Suitable reactants are other reactants comprising CuCO ₄ · 5H ₂ O, and copper ions. The electrochemical reaction in which polysilicon is replaced with copper is an oxidation-reduction reaction between silicon and copper as described below.

[0015] The ^{anode: Si 0 + 6F - → SiF} 6 2-
+ 4e ⁻ (oxidation) Cathode: 2Cu ²⁺ + 4e ⁻ → 2Cu ⁰ (metal reduction) Total reaction: Si ⁰⁺ 2Cu ²⁺ + 6F ⁻ → SiF ₆ ^2-
+ 2Cu ⁰ side reaction: Si ⁴⁺ + 2O ^2- → SiO ₂

Since the presence of by-product SiO ₂ adversely affects the adhesion of copper to the wafer, an etchant is used to etch SiO ₂ . Therefore, by-product Si
O ₂ is not present in the reactants of the seed layer and the replacement of the seed layer is sufficient. The replacement solution contains a reactant containing copper ions and an etchant. A suitable replacement solution is CuSO _4.
It is a mixed solution containing a 1.5 g / l solution of 5H ₂ O and a 7 cc / l solution of HF.

In the redox reaction of this embodiment, the etching rate of polysilicon is about 75 ° / min, and the adhesion rate of copper is about 155 ° / min. In order to adjust the thickness of the polysilicon layer and the concentration of the HF etchant, after the substitution reaction, there is no polysilicon remaining in the diffusion barrier layer that hinders the adhesion of copper to the barrier layer.

After the reaction, the formed copper seed layer is formed on the surface of the substrate. As shown in FIG.
iO ₂ is hardly found on the surface. The resistance of the copper seed layer is 11.2 μΩ-cm and the average particle size is about 360
Å. As shown in FIG. 3, polysilicon is replaced with copper in the tantalum structure.

In step (c), the formation is annealed at 350 ° C. for 8 minutes in nitrogen to increase the adhesion of the copper layer to the diffusion barrier layer. This annealing reduces the resistance of the seed layer and increases the density of the copper film structure. Step (d)
Then, the metal is plated on the seed layer. In this step, a thick copper layer is electroplated on the seed layer at 2.0 ASD and room temperature in an electroplating bath. The plating solution CuSO ₄ · 5H ₂
O (25 g / l), H ₂ SO ₄ (200 g / l), HCl
(0.15 cc / l) and surfactant (5 cc / l)
including. After 15 minutes, the thickness of the copper film is about 5000Å,
The resistance is about 1.85 μΩ-cm. As shown in FIG. 4, a suitable tissue having a <111> component exists in this film.

Also, the present invention utilizes an electrochemical displacement reaction for the deposition of the copper seed layer, thus providing excellent step coverage. After electroplating process, diameter 0.3
Vias of 5 μm and aspect ratio 2 are sufficiently filled. FIG. 5 shows the state. When the material of the diffusion barrier is tantalum and the diffusion barrier is formed by the CVD technique, the step coverage of the seed layer (step coverage)
Are improved, and smaller diameter, higher aspect ratio vias are filled with electroplated copper.

The present invention can be used for a MOS capacitor. Capacitors at 300 ° C, 400 ° C, 450 ° C, 5
Heat to 00 ° C. and measure Vfb oscillation. The copper layer plated on the prepared seed layer shows excellent results, 450 ° C
And stable. The product formed in this embodiment is ULS
Suitable as low insulator / copper in L manufacturing process. FIG. 6 shows the characteristics of the formed product. This embodiment is a suitable embodiment, and can be modified without departing from the spirit of the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a schematic view showing steps of a method for forming a copper seed layer in ULSI metallization according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating an Auger profile of a product formed by a method of forming a copper seed layer in ULSI metallization according to one embodiment of the present invention.

FIG. 3 is a view illustrating a surface morphology of a copper seed layer according to an embodiment of the present invention;

FIG. 4 shows an XR of an electroplated copper layer according to an embodiment of the present invention.
It is a figure showing a D result.

FIG. 5 is a SEM cross-sectional photograph of a layer of copper via filling according to one embodiment of the present invention.

FIG. 6 is a diagram illustrating a relationship between an electric capacity and a voltage of a product formed by a method for forming a copper seed layer in ULSI metallization according to an embodiment of the present invention.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/288 H01L 21/88 B 21/768 21/90 A F term (Reference) 4K022 AA13 AA43 BA08 BA31 CA07 CA08 DA04 4K044 AA16 AB02 BA06 BB03 BC14 CA15 CA18 4M104 BB17 BB30 BB32 DD06 DD16 DD37 DD43 DD51 DD52 DD78 EE09 EE16 FF13 FF17 FF18 FF22 GG19 HH13 HH14 5F033 HH11 HH21 HH32 PP13 NN11 JJ11 NN11 JJ11 NN11 QQ09 QQ37 QQ73 RR04 VV10 XX02 XX04 XX10 XX34

Claims (8)

[Claims] A step of preparing a substrate; a step of forming a diffusion barrier layer on the substrate; a step of forming a substitution layer on the diffusion barrier layer; and a step of forming the substitution layer in a mixed solution containing a substitution reactant. Replacing at least a part with a thin copper film, wherein the mixed solution contains a chemical substance for supplying activated copper ions and at least one chemical substance for suppressing oxidation of silicon. A method for forming a copper seed layer in lithography. 2. The method according to claim 1, wherein the replacement layer is formed of one of a polysilicon layer, an amorphous silicon layer, and a TaSix layer. 3. The method according to claim 1, wherein the diffusion barrier layer is formed of any one of a TiN layer, a tantalum layer, and a TaN layer. 4. A step of preparing a substrate, a step of forming a diffusion barrier layer on the substrate, and a step of replacing at least a part of the diffusion barrier layer with a thin copper film in a mixed solution containing a substitution reactant. The method of forming a copper seed layer in ULSI metallization, wherein the mixed solution includes a chemical substance that supplies activated copper ions and at least one chemical substance that suppresses oxidation of silicon. 5. The method for forming a copper seed layer in ULSI metallization according to claim 4, wherein the diffusion barrier layer is formed of a TaSix layer. 6. The method of forming a copper seed layer in ULSI metallization according to claim 1, wherein a plurality of vias and trenches are formed in the substrate. 7. The method for forming a copper seed layer in ULSI metallization according to claim 1, wherein the mixed solution contains CuSO ₄ .5H ₂ O and HF. 8. The method according to claim 1, further comprising plating a copper layer on the thin copper film.