JP2002261028A - Combination of substrate placement tool for semiconductor device manufacture and vertical furnace, substrate placement tool, and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase thermal stability in a vertical hot wall type, and to stably supply an easily decomposable gas. SOLUTION: A heat shelter plate 14a is provided at the upper section of a furnace (a), a vacuum heat-insulating section (15) is provided at the upper section of the furnace (b), the vacuum heat insulating section (15) is provided at the upper section of the furnace, and a vacuum heat insulating section (17) is provided at the lower section of a substrate transfer tool 16(c). The heat shelter plate 14a is provided at the upper section of a furnace, and the vacuum heat insulating section (17) is provided at the lower section of the substrate transfer tool 16(d), or a vacuum heat insulating section (36a) is provided in a gas guiding pipe that is positioned in the furnace (e).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a combination of a substrate mounting jig for manufacturing a semiconductor device and a vertical furnace, a substrate mounting jig, and a method of manufacturing a semiconductor device. , Low pressure CVD, diffusion, annealing, etc., in which batch processing is performed in a heating furnace, the uniformity of the temperature characteristics in the furnace is excellent, and a pseudo semiconductor substrate (sometimes called a “dummy wafer”) is used as much as possible. It concerns methods that are not used or not used at all. Further, the present invention relates to a vertical furnace batch process using a readily decomposable gas.

[0002]

2. Description of the Related Art Prior art will be described in the following order. 1. Vertical heating furnace 2. 2. Various film forming methods without using ozone Film formation method using ozone

[0003] 1. Vertical heating furnace The double tube type vertical furnace is, for example, a patent No. 2 according to the inventor's invention.
No. 6,350,019. In the double tube vertical heating furnace, in the case of an 8-inch semiconductor substrate, generally, about 100 to 150 substrates are batch-processed in a soaking region having a length of 700 to 900 mm. Since the upper and lower ends of the substrate mounting jig are close to the upper and lower limits of the soaking length, stabilize the temperature. About 5 to 7 pseudo substrates are arranged, and a semiconductor substrate as a product is interposed therebetween. Such a pseudo substrate is used because, in a vertical heating furnace, the upper part is likely to become hot due to convection, and the balance between the radiation from the heater and the heat radiation from the furnace body to the outside tends to collapse at the upper and lower parts of the furnace. This is because the flow velocity and concentration distribution of the gas become non-uniform above and below the furnace. The pseudo substrate receives the same heat history as the product substrate, and is replaced at an appropriate processing cycle. This replacement is considerably complicated, and for example, Japanese Patent Application Laid-Open No. 11-6787.
As proposed in No. 8, computer automation is being considered.

According to JP-A-11-54448,
In order to equalize the temperature of the vertical furnace reaction tube in a short time, it has been proposed to provide an insulating plate on the top of the wafer holding boat. Generally, the heating rate of a batch type vertical furnace is 10
~ 80 ° C / min, while the cooling rate is 2-3 ° C / min.
Min to 20 to 30 ° C / min, and the cooling time from the reaction temperature to a temperature at which the wafer can be taken out is usually 20 to 30 ° C.
It lasts 40 minutes. In the batch type vertical furnace having such characteristics, when the heat insulating plate is fixed to the wafer holding boat as described in the above publication, the cooling time becomes longer due to the heat capacity of the heat insulating plate, and the lead time of the semiconductor device manufacturing process becomes longer.

[0005] 2. Film formation method without using ozone P of the BPSG film BPSG film is used as a passivation film for capturing a trace amount of heavy metal and preventing contamination of the MOS device for the purpose of improving the reliability of the device. BPSG (boro phosphosilica
The te glass) film is reflowed at 800-900 ° C. The BPSG film was formed at about 400 ° C. using SiH ₄ , B ₂ H ₆ , PH ₃ , and O ₂ as reaction gases (for example, Japanese Patent Laid-Open No. 3-212958). In the batch method, a method of forming a BPSG film by low-pressure CVD, which has better step coverage than normal pressure CVD, is used (Semiconductor World. 1999.9, p33-38, monthly). BP
The source gas for the SG film is tetraethoxysilane (TEOS), diacetate dibenzene silicon (DADBS), trimethyl phosphate (TMP-ate), and trimethyl phosphite (T
MP-ite), triethyl borate (TEB) and oxygen as oxidizing agent. Introduce TEOS, TMP-ate, TEB, etc. from separate sources as oxygen into the inlet of a batch type horizontal furnace as a carrier gas and grow at 640-680 ° C to form a BPSG film with a film thickness distribution of ± 5%. are doing. The source gas inlet tube is heated to near or above the boiling point of the source gas to prevent liquefaction of the gas. Since the dope gas introduced together with the source gas is easily decomposed, the B and P concentration distributions were not good in the case of batch processing. BP
SG is also used for filling grooves. This BPSG is 3-8
wt%, P4 ~ 8wt% B, BPS of such composition
G is deposited under the conditions of 640 to 680 ° C. It is desired that the growth temperature be as low as possible after forming the source and drain of the MOSFET.

[0006] nitride film further, include a film formation method of a variety of other films. A nitride film is formed by the following reaction. 3SiH ₂ Cl ₂ + 4NH ₃ → Si ₃ N ₄ + 6HCl + 6H ₂ … (1) 3SiH ₄ + 4NH ₃ → Si ₃ N ₄ + 12H ₂ … (2) The reaction of formula (1) using dichlorosilane (DCS) 68
The reaction of the formula (2) is carried out at 520 to 700 ° C at 0 to 800 ° C. Using N ₂ O instead of NH ₃ in formula (1) or (2)
An SiON film is being formed. The formation of a titanium nitride film is performed by the following reaction. TiCl ₄ + NH ₄ → TiN + 4HCl… (3)

The P-doped polysilicon film using the polysilicon films SiH ₄ and PH ₃ has a reduced pressure C
VD growth is performed in a batch type vertical furnace. The reaction temperature is about 530 ° C., the growth rate is 10 to 15 Å / min, and the growth rate of SiH ₄ is 80 to 100 Å / min when the film is formed at 620 ° C. by the low pressure CVD method.

The above-mentioned reaction is carried out by, for example, disposing 100 to 150 8-inch wafers in a soaking region of 700 to 900 mm in a vertical furnace. For example, SiH ₄ and PH ₃ gases are disclosed in Japanese Patent No. 26305019. Is introduced into the furnace from the lower part of the vertical furnace. In this method, PH _{3 which} is easily decomposed decomposes quickly, and a high concentration of P is doped into the wafer set on the lower side.

3. Film formation method using ozone Ozone is used as an oxidizing gas, and O ₃ → O ₂ + [O] (about 370-400 ° C.) by TEOS and TEB generated during the reaction of (3) A BPSG film is formed by the method described above, and is also used for embedding a trench for element isolation and insulating between aluminum layers (referred to as an “O ₃ -TEOS method”).

The O ₃ -TEOS method is currently implemented in the following single-wafer apparatus. That is, a normal-pressure belt conveyor / single-wafer type device manufactured by Company A, a normal-pressure single-wafer type equipment of Company B,
This is a reduced pressure single-wafer type device close to normal pressure of Company C.

[0011]

Conventionally, since a vertical double-tube heating furnace was premised on the use of a pseudo substrate, efforts have been made to improve the pressure and temperature characteristics of the heating furnace itself. It is difficult to say that it will be difficult to cope with a larger wafer and a thinner film in the future. In addition, if the heat insulating plate is fixed to the uppermost portion of the wafer holding boat, the cooling time becomes longer, and the productivity is reduced. Accordingly, an object of the present invention is to overcome these problems in a batch process using a double tube type vertical heating furnace and to form a film / layer with excellent uniformity on a large-diameter substrate. Another object of the present invention is to provide a batch processing method having excellent composition uniformity in a method of manufacturing a semiconductor device using a readily decomposable gas. Furthermore, in the CVD method using ozone, batch processing is difficult because the source gas is easily decomposed at 370 ° C. or higher. An object of the present invention is to provide a batch-type film forming method that can solve these problems.

[0012]

According to a first aspect of the present invention, a semiconductor substrate including or not including a dummy wafer is removably laid horizontally from a jig, and arranged at regular intervals in a vertical direction. In a combination of a substrate mounting jig for bringing a semiconductor substrate into contact with a gas in a uniform temperature and pressure constant region in a vertical heating furnace and a vertical heating furnace (hereinafter, simply referred to as “combination”), A heat shield is provided in the heat equalizing area of the upper space, which is opposed to the semiconductor substrate array area and is separated from the furnace space by the gas-impermeable partition wall, but communicates with the outside air. The semiconductor device is characterized in that the size is not less than the size of the semiconductor substrate, and the vertical dimension is not less than four times the fixed interval. The second combination according to the present invention is to provide a vacuum heat insulating portion opposed to the semiconductor substrate array region in the heat equalizing region in the upper space in the furnace, and to set the lower lateral dimension thereof to be equal to or larger than the size of the semiconductor substrate. And the vertical dimension is at least four times the fixed interval. The combination according to the third aspect of the present invention is a combination of an upper vacuum heat insulating portion opposed to the semiconductor substrate arrangement region in the heat equalizing region in the upper space inside the furnace, and at least a part located in the heat equalizing space in the lower space inside the furnace. The lower vacuum heat insulating portion is provided so as to face the semiconductor substrate array region, and the dimensions of the upper and lower vacuum heat insulating portions are set such that the lateral dimension at the portion closest to the semiconductor substrate is equal to or larger than the size of the semiconductor substrate. In this case, the vertical dimension is at least four times the fixed interval. The fourth combination according to the present invention is arranged so as to be opposed to the semiconductor substrate arrangement region in the soaking region in the upper space inside the furnace and to be isolated from the space inside the heating furnace by the gas-impermeable partition but to communicate with the outside air. And a horizontal dimension of the lower portion is equal to or greater than the dimension of the semiconductor substrate, and a vertical dimension is equal to or greater than four times the constant interval. The lower vacuum heat insulating portion is provided so as to be located opposite to the semiconductor substrate array region so that the dimension of the vacuum heat insulating portion is greater than or equal to the size of the semiconductor substrate in the portion closest to the semiconductor substrate. , Characterized in that the vertical dimension is at least four times the fixed interval. A substrate mounting jig for manufacturing a semiconductor device according to the present invention, a semiconductor substrate including or not including a dummy wafer is removably placed horizontally from the jig, and arranged at regular intervals in the vertical direction, In the substrate mounting jig for contacting the gas in the uniform temperature and constant pressure region in the vertical heating furnace, a vacuum heat insulating portion is provided below the substrate mounting jig in a portion closest to the semiconductor substrate arrangement region. The semiconductor device is characterized in that it is fixed, its horizontal dimension is equal to or larger than the dimension of the semiconductor substrate, and its vertical dimension is equal to or more than four times the predetermined interval. The method for manufacturing a semiconductor device according to the present invention is characterized in that a semiconductor substrate including or not including a dummy wafer is removably horizontally placed on a substrate mounting jig moving vertically in a vertical heating furnace and detachably and vertically. In a method for manufacturing a semiconductor device in which a semiconductor substrate and a gas are brought into contact with a semiconductor substrate in a uniform temperature and pressure constant region in the vertical heating furnace and arranged at a constant interval from each other in a direction, a vacuum heat insulating portion is provided around a tube. The gas is guided in the vertical heating furnace by a pipe. Hereinafter, the method of the present invention will be described.

In the present invention, the substrate mounting jig for semiconductor manufacturing means that a wafer is loaded into a heating furnace, held at a predetermined position in the furnace, taken out of the furnace after processing, and removed from the jig itself. It is a known jig which can be removed, for example, as disclosed in Japanese Patent Application Laid-Open No. 8-45861 of the present applicant (FIG. 3).
5) can be used. In the present invention, the dummy wafer is a semiconductor substrate having the same size and material as the semiconductor substrate forming the device, and absorbs the transient phenomena of the temperature and / or pressure in the heating furnace and some faults in the furnace condition, and reduces the influence on the former. It is well known per se, which is taken in and out with the wafer to reduce it. The installation position of the dummy wafer is usually the uppermost and / or lowermost position.
In the following description, a dummy wafer and a wafer serving as a device are collectively referred to as a “wafer”. In the present invention, the soaking area is a meaning generally used in the art (Semiconductor Manufacturing Equipment Glossary (4th edition) Nikkan Kogyo Shimbun 1
Published on November 20, 997, p. 197, see "soaking length"). In the present invention, the constant pressure region is a region where the pressure is measured in a vertical direction at a constant position in a space excluding the vicinity of the reaction tube wall, the vicinity of the wafer surface, and the like, and the constant pressure. Instead of the actual measurement, a value with almost no error can be obtained by simulation software. More practically, a wafer arrangement region in which the film thickness measured in the soaking region is a constant value including an error allowed as a product can be called a constant pressure region.

Usually, the wafers are arranged over substantially the entire length of the soaking area. That is, a maximum of 150 8-inch wafers is reduced to about 5
When processing 50 wafers in a heating furnace that can be arranged at an interval of mm, the wafers are arranged at an interval of 15 mm. However, it is also possible to arrange 50 wafers in a part of the soaking area. In the latter method, for example, 50 wafers are offset by about 5 mm at an interval of 5 mm above the soaking furnace area.
An appropriate number of quartz plates are supported on a wafer mounting jig in the lower heat equalizing area of 00 mm, and can be heated and cooled in the same manner as a wafer. In this case, no lower vacuum insulation is needed.

In the first combination according to the present invention, the heat shield provided above the uppermost wafer prevents heat from radiating upward from the wafer and stores heat, and at the same time dissipates heat due to a temperature difference from outside air. Is performed to increase the temperature uniformity in the furnace. The space in the furnace and the space in the heat shield are separated by a partition made of a material such as quartz having sufficient heat resistance at the reaction temperature and gas impermeability and not contaminating the wafer. The lower portion of the heat shield has a disk shape having a horizontal dimension substantially the same as or larger than the wafer, and a vertical dimension that is four times or more the wafer arrangement interval. The air present in the heat shield has a specific heat of 1.2 at room temperature with respect to Si.
Since it is 9 times, it is approximately the same as Si is arranged in the concave space. For this reason, the thermal stability is improved, and the number of used dummy wafers can be eliminated or the dummy wafer need not be used. When the heat shielding portion is smaller than the above-mentioned size, the effect of improving the furnace temperature uniformity is reduced. In addition, the method for fixing the heat shielding partition in the furnace is not particularly limited. Preferably, the heat shielding partition is airtightly connected to the upper end of the outer tube of the double tube, and is preferably held by the outer tube.

In the vacuum insulation provided in the second and third combinations of the present invention, the vacuum is
The pressure is below 0 ^-3 torr. By the way, since vacuum has a very low specific heat compared to the heat insulating material, the heat load is light, and the temperature is easy to be lowered during cooling. There is an advantage that it does not occur. Therefore, it is preferable not to use any heat insulating material that may contain a substance that contaminates the semiconductor. However, when the reaction temperature is low, a thin film of the heat insulating material may be attached to the inner wall of the vacuum heat insulating unit.

The second combination of the upper vacuum insulation section according to the present invention is permanently installed in the furnace and is located at a fixed position regardless of whether a wafer is inserted or removed. Therefore, the wafer is charged into the furnace by the jig after the upper vacuum heat insulating portion is heated to the reaction temperature.

In the second combination according to the present invention, the planar expansion of the vacuum heat insulating portion is equal to or larger than the size of the wafer at the portion closest to the wafer, and the vertical size of the vacuum heat insulating portion is four times the wafer arrangement interval. As described above, it is necessary to sufficiently secure the heat insulating effect of the vacuum. When the space between the vacuum heat insulating portion and the wafer is substantially equal to the wafer arrangement space, it is thermally equivalent to the provision of a dummy wafer having the thermal conductivity of the outer partition wall of the heat insulating portion.

The structure of the upper vacuum heat insulating portion according to the present invention uses a bottom plate having the same shape and size as the wafer and an extension extending upward from the entire periphery thereof, and the bottom plate, the vertical extension and other members are used to form an inner space. Can create a vacuum space inside. Further, the internal space can be created by extending the bottom plate horizontally to the inner wall of the outer tube without using the vertical extension.

On the other hand, the lower vacuum heat insulating part of the third combination according to the present invention is fixed to the lower part of the wafer mounting jig and is moved together with the jig into the furnace. The temperature is raised to 620 ° C. The heating time is usually about 10 to 30 minutes, and then the reaction is performed. In a vertical heating furnace, the temperature in the upper part rises and becomes stable due to convection, whereas the temperature in the lower part tends to change.
The lower vacuum heat insulating portion has an effect of stabilizing the temperature characteristics of the lower portion after the temperature is raised. A preferred structure of the lower vacuum heat insulating portion according to the present invention is a structure in which a ceiling plate having the same shape and size as the wafer, an extension extending downward from the entire peripheral edge thereof, and a bottom plate are hermetically bonded. More preferably, when the extension is vertically extended, a space is formed inside having a diameter substantially equal to that of the wafer. The dimensions of the concave space are as described for the second combination.

By a method satisfying the above conditions,
It is possible to use no dummy wafer or reduce the number of used wafers to one or less at the top and two or less at the bottom. In addition, it can be easily adapted to large diameter wafer and / or thin film growth.

Further, in the first to fourth combinations of the present invention, the uppermost and / or lowermost positions of the wafer apparatus jig are made of quartz or the like which does not substantially react with gas and have the same size as the wafer. By providing one or two plates (hereinafter referred to as "air conditioning plates") to the wafer and at regular intervals with respect to each other, the uniformity of the pressure in the furnace can be further improved. Conventional dummy wafers also have the function of equalizing the pressure and gas flow, but they need to be replaced each time they are processed because they react with the gas, and because the temperature characteristics in the furnace are not excellent, many wafers can be produced. Was needed. However, in the present invention, the air conditioning plate does not need to be replaced.

The substrate mounting jig according to the present invention does not include the vertical heating of the second combination, and the heating furnace itself may be a known one.

In the method for manufacturing a semiconductor manufacturing apparatus according to the present invention, a vacuum heat insulating surrounding portion is provided in a gas introduction pipe extending into a heating furnace to eliminate heat conduction by conduction and prevent decomposition of easily decomposable gas. To enable batch processing. The method of using gas in the method of the present invention includes: (a) separately introducing a readily decomposable gas and a hardly decomposable gas;
(B) Introduce a mixed gas of a readily decomposable gas and a hardly decomposable gas; (c) Use only one of the easily decomposable gas and the hardly decomposable gas; (2) Use both (a) and (b) And so on.
In these uses, at least the gas introduction pipe through which the easily decomposable gas flows is vacuum-insulated. As a mode of the gas introduction pipe, it is preferable that the gas be guided by a single pipe to the vicinity of the arrangement height of the plurality of wafers in order to perform batch processing, and then the gas be ejected laterally into the furnace. Specifically, for example, when processing 100 wafers, 20 to 10 ejection ports are provided in the vertical direction, and gas is supplied from one ejection port for every 3 to 5 wafers. In this specific embodiment, as the structure of the gas introduction pipe, the pipe from the gas supply source to the heating furnace does not need to be particularly vacuum-insulated,
It is necessary to vacuum insulate a tube extending in the furnace in the vertical direction and having the above-described 20 to 30 jet ports. In addition, there are an outlet formed by piercing a tube wall and an outlet formed by projecting from a tube wall. In the latter case, it is preferable that the protrusion is also vacuum-insulated. However, since it is difficult to vacuum insulate the protrusion from the viewpoint of machining, it is preferable that the jet port is formed by forming a pipe wall. Further, the entire furnace and the structure of the pipe become complicated, but the pipe from the gas supply source to the heating furnace is extended vertically outside the furnace, and then 20 to 30 gas introduction pipes are branched from this extension. Then, it may be made to enter the furnace, and the entry portion may be vacuum-insulated. It is preferable that the thickness of the vacuum heat insulating part is substantially equal to or larger than the inner diameter of the gas introduction pipe. It is preferable that a reflection plate is provided in the gas introduction pipe to reflect heat from inside the furnace and further prevent the decomposition of the gas. The reflecting plate is preferably provided concentrically in a vacuum space. The method of the present invention can be carried out in a single tube furnace or a known double tube furnace, and can also be carried out in the first to fourth combinations.

The gas inlet pipe provided with a vacuum heat insulating part around the pipe used in the method according to the present invention is capable of stably transporting easily decomposed gas to a pipe just before the pipe outlet by one pipe. It is also effective when forming a Si ₃ N ₄ film using NH _3, which is easily decomposed by the formula, as a reaction gas. In this case, the film pressure of the nitride film grown on 50 8-inch wafers can be kept within ± 1.0%. Further, PH ₃ can be stably transported during the formation of the P-doped polysilicon described in paragraph 0007, which is effective in making the P concentration uniform. In the batch processing (provided that the reaction temperature is 530 ° C. and the film pressure is 2000 angstroms), the film pressure can be kept within ± 2 to 3%.

The gas introduction pipe according to the present invention having a vacuum heat insulating portion provided around the pipe can be used in a conventional double tube type vertical furnace. When forming a P-doped polysilicon film described in paragraph 0007, a part of PH ₃ is introduced from the lower part of the reaction tube by a usual method, and the remaining PH ₃ is introduced from the center to the upper part by the gas introduction tube of the present invention. Then, the P concentration of the upper wafer can be increased. For example, in batch processing of 100 8-inch wafers, the P concentration distribution can be kept within ± 2 to 3%. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The left half of FIG. 1 shows a vertical double-tube heating furnace for performing low-pressure CVD, and embodies a fourth combination. The left graph of the two graphs shows the temperature distribution along the central axis of the furnace, and the right graph shows the furnace pressure on the line PP ′. In the drawing, 1 is a heating furnace, 2 is a furnace body made of refractory and heat insulating material, 3 is a heater in which a resistor divided into 6 zones is fixed to the furnace body 2 by a holding member (not shown), 5 is an inner tube, 6
Is an outer tube, 7 is an inlet of a reaction gas or a purge gas, 8 is a readily decomposable reaction gas introduction tube, 8a is a large number of gas outlets formed in the vertical direction, 9 is an annular exhaust passage between the outer tube and the inner tube,
10 is a reaction gas outlet, 23 is a rotating shaft, 24 is a bottom plate, 25
Is a seal ring and 26 is an O-ring, each of which is known.

The reaction gas introduction pipe 8 extends into the furnace to a dead end, and is used to feed easily decomposed reaction gas such as phosphine (PH ₃ ) from a plurality of gas outlets 8a formed in the middle. On the other hand, a reaction gas introduction pipe 7 is provided at the lower part of the furnace and is used for feeding a reaction gas such as silane (SiH ₄ ) which is difficult to decompose. Also, 13
Are wafers which are schematically represented by omitting the illustration of their thickness. These are, for example, disclosed in Japanese Patent Application Laid-Open No. 8-45861 of the present applicant.
They are arranged at regular intervals by jigs shown in Japanese Patent Application Laid-Open Publication No. H10 (FIGS. 3 to 5). The uppermost wafer 13 is the inner tube 5
Is located in a constant pressure region below the upper end of.

Numeral 11 denotes a baffle plate fixed to a substrate mounting jig above the uppermost wafer 13.
Reference numeral 4a is a heat shield plate made of quartz and fixed at the upper part of the heating furnace. These 11 and 14 have a diameter of 12 inches when processing a 12-inch wafer 13, for example.
The space between the heat shield plate 14a and the air conditioner 11 and the space between the air conditioner 11 and the uppermost wafer 13 are the same as the wafer arrangement space. The air conditioning plate 11 indicates the thickness, and the wafer 13
Does not show the thickness, so the spacing between 11 is uneven and the spacing between 11 and 13 is only due to the drawing technique according to the thickness (not shown). In such an array structure, the upward radiation from the uppermost wafer 13 is blocked by the air conditioning plate 11 and the heat shielding plate 14a, and the air conditioning plate 11 and the heat shielding plate 14a are heated and cooled similarly to the wafer. In addition, lateral reactant gas flows are added at two locations between the wafer 13 and the air conditioner 11 and between the air conditioner 11 and the heat shield 14a. As a result of combining these actions, the uniformity of the film thickness grown on the uppermost wafer 13 is improved.

In the heat shield plate 14a according to the present invention, the upper end of the outer tube 6 is extended so that the outer tube 6 and the heat shield plate 14a are integrally airtight. The side wall 14a of the ceiling 14 attached to the outer tube 6 extends vertically. 14c is 14a, 14
This is a curved portion integrated with b and 6. The internal space 14d communicates with the outside air through a gap between the outer tube 6 and the heater 3, and has a concave shape, and has a diameter substantially equal to that of the wafer 13. The internal space 14d is located in the heat equalizing region, and the pressure is a constant pressure that strikes against the outside air. Therefore,
The air conditioning plate 11, the heat shielding plate 14a and the internal space 14d have the function of a conventional dummy wafer.
d is fixed, and the air conditioner 11 is not made of Si. Therefore, the drawbacks of the conventional dummy wafer, which is made of the same material as the wafer forming the device and moves up and down together with the wafer forming the device, can be avoided.

Reference numeral 16 denotes a vacuum heat insulating portion fixed to a lower portion of the substrate transfer jig, which is assembled by welding a quartz plate so that the inside is a vacuum space 17. The outer diameter of the upper side wall 16b of the vacuum heat insulating part 16 is equal to the outer diameter of the wafer 13, and
Since the upper surface 16a has the same circular shape as the wafer, the internal vacuum space 17 is formed by artificially stacking wafers at regular intervals. Further, reflecting plates 18 and 19 made of aluminum or gold are placed in the vacuum space 17 by the pillars 2.
By supporting at 0a and b, the radiant heat from the heater 3 is reflected into the furnace, thereby improving the uniform heating characteristics of the lower part of the heating furnace.

Next, the pressure distribution in the furnace will be described. Constant pressure region between slightly and position P ₂ lower than slightly above the upper surface 16a of the vacuum adiabatic portion 16 above the position P ₁ and the heat shielding plate 14a is present. Gas pressure due to the influence of the reaction gas or purge gas flows from the inlet 7 is lower than the position P ₁ is high. Meanwhile P ₂ slightly pressure in the lower position P ₃ from between the upper end of the inner tube 5 is lowered, the pressure further descent is from P ₃ to the curved portion 14c.

FIG. 2 shows a vertical double-pipe heating furnace having a structure different from that of FIG. 1 and embodies the third combination of the present invention. That is, the upper extension of the outer tube 6 is a circular ceiling structure 6a, and these 6a and 14 are airtightly connected.
A vacuum space 15 is formed inside. This vacuum space 1
Numeral 5 has a heat insulating function as a whole, and the quartz plate is deformed into a concave shape so that several wafers simulate a vacuum space 14d stacked at equal intervals above the air conditioning plate 11 and the wafer 13. (14b).

FIGS. 3 and 4 show an embodiment of the third combination according to the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. The main difference is that the CVD reaction gas flows in parallel to the wafer 13 from the reaction gas introduction pipe 8 extending in the longitudinal direction through the inner recess 5a (FIG. 4) of the inner pipe 5 through the ejection port 8a. Then, the air is sucked into the exhaust passage 9 in parallel from the suction port 5a formed in the pipe wall of the inner pipe 5; the upper vacuum insulation section 15 occupies the entire upper space of the furnace, and the upper end of the inner pipe 5 is vacuum-insulated. It is airtightly joined to the bottom of the part 15. Further, a purge gas introduction pipe 29 is provided at the lower end of the furnace. In the devices shown in these figures, a gas introduction pipe (not shown) which is not normally vacuum-insulated can be provided. The O ₃ in the apparatus through the gas inlet tube 8, it is possible to implement O ₃ -TEOS method by conveying the TEOS from the normal of the gas inlet tube.

FIG. 5 shows an embodiment modified to use the combination of FIG. 4 for annealing. The reaction gas introduction pipe 8 for introducing an annealing gas such as N ₂ or Ar is connected to the bottom quartz plate 14b.
And the bottom quartz plate 14b and the air conditioning plate 11
Is the upper space 30 in which the wafer arrangement interval is six times or less. For this reason, the upper space 30 is stabilized against temperature fluctuations by the vacuum space 15 above it, and a larger amount of annealing gas is converted into a uniform gas flow in the upper space 30. Therefore, the uniformity of annealing is improved.
The vertical furnace is a single tube type.

FIG. 6 shows a method of manufacturing a semiconductor device according to the present invention in which the outer peripheral portion of the reaction gas introduction pipe 8 is vacuum-insulated to prevent decomposition of easily decomposable gases such as PH ₃ and O ₃ flowing in the pipe. It is a drawing showing an example. In the figure, a tube 36 constituting the vacuum heat insulating structure 35 surrounds the entire periphery in the lower half of the reaction gas introduction tube 8, and surrounds the portion other than the ejection port 8a in the upper half.
36a corresponds to a hollow portion and is a vacuum space. The reaction gas introduction pipe 8 shown in FIG. 6 is vacuum-insulated at the lower part all around, and the outlet 8a is opened only at the upper part (not shown).
By using in combination with another reaction gas introduction pipe whose upper part is vacuum-insulated all around and whose ejection port 8a is opened only at the lower part, a gas which can be easily decomposed to the whole wafer can be supplied in an undecomposed state. .

FIG. 7 shows a modification of FIG. 6, in which the jet port 8a is also a vacuum heat insulating structure 35, and the reflector 37 is provided inside the tube 36.
The heat insulation structure is further enhanced by arranging the entire length. According to this structure, the formation of the SiO ₂ film by O ₃ + TEOS can be performed by a batch method.

According to the embodiment of FIG. 7, when a normal-temperature oxygen gas containing 1 to 5% O ₃ flows at a flow rate of 500 to 1000 mL / min, the oxygen gas is discharged from the gas inlet tube into the furnace at 370 ° C. or lower. Can be. The reaction between TEOS and O ₃ is 0.5
It can be performed on 25 to 50 wafers under the conditions of 3 Torr and 400 ° C. In forming these films, a plate or foil of Al, Ti, Mo. W, Au, or the like can be used as the reflection plate 37. Of course, the method of the present invention need not be performed simultaneously with the first to fourth combinations.

[0039]

As described above, the first embodiment according to the present invention is described.
Since the temperature stability of the vertical heating furnace is improved by the combination of Nos. 1 to 5 and the substrate mounting jig method, it is possible to cope with a large-diameter wafer and / or thinning. Further, the method according to the present invention enables batch processing using a gas which is easily decomposed. Therefore, the present invention greatly contributes to the production of semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a fourth combination according to the present invention.

FIG. 2 is a diagram showing an example of a third combination according to the present invention.

FIG. 3 is a drawing showing another embodiment of the third combination according to the present invention.

4 is a view taken in the direction of arrows AA ′ in FIG. 3 (however, a furnace body and a heater are not shown).

FIG. 5 is a drawing of a reaction gas introduction pipe showing still another embodiment of the third combination of the present invention.

FIG. 6 is a drawing of a reaction gas introduction pipe according to the present invention.

FIG. 7 is a drawing of a reaction gas introduction pipe showing another embodiment different from FIG. 6;

[Explanation of symbols]

 Reference Signs List 1-heating furnace 2-furnace body 3-heater 4-double pipe structure 5-inner pipe 6-outer pipe 7-reaction gas or purge gas inlet, 8-reaction gas introduction pipe 9-annular exhaust passage, 10-reaction gas outlet 14, 16-thermal insulation

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/22 511 H01L 21/22 511J 21/31 21/31 B 21/324 21/324 G F term ( 4K030 CA04 CA12 GA02 JA01 JA03 KA04 KA05 KA12 KA23 5F045 AA06 AA20 AB03 AB32 AB33 AB35 AC01 AC07 AC11 AC12 AC19 DP19 EC01 EC02 EC07 EK06

Claims (14)

[Claims] 1. A semiconductor substrate, including or not including a dummy wafer, is removably laid horizontally from a jig and arranged at regular intervals in a vertical direction, and the semiconductor substrate is heated in a vertical heating furnace. In a combination of a substrate mounting jig for contacting a gas in a constant pressure region and a vertical heating furnace, the substrate placement jig is opposed to the semiconductor substrate arrangement region in a soaking region in a space above the furnace and is gas impermeable. A heat shielding portion is provided that is isolated from the furnace space by the conductive partition but communicates with the outside air, and its lower horizontal dimension is equal to or greater than the semiconductor substrate dimension, and its vertical dimension is equal to or greater than four times the constant interval. A combination of a substrate mounting jig for manufacturing a semiconductor device and a vertical heating furnace. 2. The gas-impermeable partition according to claim 1, wherein the vertical heating furnace is of a double tube type, and the upper end of the double tube outer tube is extended to form the gas impermeable partition. Combination of substrate mounting jig for semiconductor device manufacturing and vertical furnace. 3. At the top of the semiconductor substrate array region,
3. The substrate mounting device according to claim 1, wherein a disk having the same size as the semiconductor substrate and substantially non-reactive with respect to the gas is fixed to a substrate mounting jig. Combination of mounting jig and vertical heating furnace. 4. A semiconductor substrate including or not including a dummy wafer is removably laid horizontally from a jig, and is arranged at regular intervals in a vertical direction, and the semiconductor substrates are uniformly heated in a vertical heating furnace. In addition, in a combination of a substrate mounting jig which is brought into contact with a gas in a constant pressure region and a vertical heating furnace, a vacuum heat insulating portion opposed to the semiconductor substrate arrangement region in a soaking region in a space above the furnace. A substrate mounting jig for manufacturing a semiconductor device, wherein the horizontal dimension of the lower portion is equal to or greater than the dimension of the semiconductor substrate, and the vertical dimension is equal to or greater than four times the constant interval. Furnace combinations. 5. A semiconductor substrate including or not including a dummy wafer is removably laid horizontally from a jig, and arranged at regular intervals in a vertical direction, and the semiconductor substrate is uniformly heated in a vertical heating furnace. In a combination of a substrate mounting jig that is brought into contact with a gas within a constant pressure area and a vertical heating furnace,
Providing an upper vacuum heat insulating portion opposed to the semiconductor substrate array region in the heat equalizing region of the furnace upper space, and the lower vacuum heat insulating portion such that at least a portion is located in the heat equalizing space of the furnace lower space. Along with providing the semiconductor substrate arrangement region,
The dimensions of the upper and lower vacuum insulation portions are such that the lateral dimension at the portion closest to the semiconductor substrate is equal to or greater than the dimension of the semiconductor substrate, and the vertical dimension is equal to or greater than four times the constant interval. Combination of substrate mounting jig for semiconductor device manufacturing and vertical heating furnace. 6. A semiconductor substrate including or not including a dummy wafer is laid horizontally so as to be detachable from a jig, and arranged at predetermined intervals in a vertical direction, and the semiconductor substrate is uniformly heated in a vertical heating furnace. In a combination of a substrate mounting jig that is brought into contact with a gas within a constant pressure area and a vertical heating furnace,
A heat shielding portion which is opposed to the semiconductor substrate array region in the heat equalizing region of the upper space in the furnace and is separated from the space in the heating furnace by the gas impermeable partition but is communicated with the outside air,
A lower vacuum heat insulating portion is provided so as to face at least a part of the heat sink space in the furnace lower space so as to face the semiconductor substrate array region, and the dimensions of the heat shield portion and the lower vacuum heat insulating portion are set to the semiconductor substrate. A substrate mounting jig for manufacturing a semiconductor device, wherein a horizontal dimension at a closest portion is equal to or greater than a dimension of the semiconductor substrate, and a vertical dimension is equal to or greater than four times the predetermined interval. Furnace combinations. 7. A combination of a substrate mounting jig for manufacturing a semiconductor device and a vertical heating furnace according to claim 5, wherein a reflection plate is provided in the lower vacuum heat insulating portion. 8. One or both of an uppermost portion and a lowermost portion of the substrate mounting jig, at a position closest to the semiconductor substrate arrangement region, having the same size as the semiconductor substrate, and The substantially non-reactive disk is fixed to the substrate mounting jig by means of the above method.
A combination of the substrate mounting jig for manufacturing a semiconductor device according to any one of the above and a vertical furnace. 9. A semiconductor substrate including or not including a dummy wafer is removably laid horizontally from a jig, and arranged at regular intervals in a vertical direction, and the semiconductor substrate is uniformly heated in a vertical heating furnace. In a substrate mounting jig which is brought into contact with gas in a constant pressure area, a vacuum heat insulating portion is fixed below the substrate mounting jig at a portion closest to the semiconductor substrate arrangement area, and its lateral dimension is set to A substrate mounting jig for manufacturing a semiconductor device, wherein the jig has a dimension equal to or greater than a dimension of a substrate and a dimension in a vertical direction is equal to or greater than four times the predetermined interval. 10. The substrate mounting jig for manufacturing a semiconductor device according to claim 9, wherein a reflecting plate is provided inside said vacuum heat insulating portion. 11. The semiconductor device according to claim 1, wherein at one or both of an uppermost portion and a lowermost portion of the substrate mounting jig, at a position closest to the semiconductor substrate arrangement region, the substrate mounting jig has the same size as the semiconductor substrate, The substrate mounting jig for manufacturing a semiconductor device according to claim 9, wherein a substantially non-reactive disk is fixed by using the jig. 12. A semiconductor wafer including or not including a dummy wafer is removably placed laterally on a substrate mounting jig which moves vertically in a vertical heating furnace from the jig and has a predetermined interval in the vertical direction. In a method of manufacturing a semiconductor device in which a gas is brought into contact with a semiconductor substrate in a uniform temperature and constant pressure region in the vertical heating furnace, the gas is supplied by a gas introduction pipe provided with a vacuum heat insulating portion around the pipe. A method for manufacturing a semiconductor device, wherein the semiconductor device is guided in a vertical heating furnace. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the gas introduction pipe extends in the vertical furnace in a vertical direction, and the gas is jetted above the uppermost semiconductor substrate. . 14. The method for manufacturing a semiconductor device according to claim 12, wherein a reflection plate is provided in the gas introduction pipe.