JP2002248252A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine for reducing a load on the transmission of information of a game control means, and capable of continuing control on a put-out game medium even if failure is caused in a put-out control means. SOLUTION: Electric power is supplied to a winning ball count switch 301A from a main base board 31. Thus, even if failure is caused in a put-out control board 37, detection of a game ball put-out as a pachinko prize does not become impossible. Since a detecting signal of the winning ball count switch 301A is inputted to both the main base board 31 and the put-out control board 37, control based on the detecting signal can be executed in both the game control means and the put-out control means. The put-out control means controls put-out on the basis of a command from the game control means, and even if either condition of a plurality of conditions to stop the put-out is realized, the game control means transmits the same command to the put-out control means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine in which a player can play a predetermined game and pay out a prize game medium as a prize according to satisfaction of a predetermined condition. About.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is fired into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of game media are played. May be paid out to players as prizes. The payout of the game medium is performed by a payout mechanism. The payout mechanism is controlled by the payout control means. Accordingly, the game control means for controlling the game progress of the gaming machine instructs the payout control means mounted on the payout control board with the number of winning balls according to the winning. The payout control means controls to pay out a number of game media according to the instruction from the payout mechanism.

Generally, game media paid out as a prize to a player are stored on the back of the game machine. If the stored game media is exhausted, the payout of the game media cannot be performed. Therefore, when it is detected that the stored game media is exhausted, the game control means should pay out to the payout control means as a prize. Notifies that the storage game media has run out. Then, when the storage amount of the game medium to be paid out as a prize is restored to a predetermined amount or more, it is notified that there is a game medium to be paid out.

Further, a storage unit for storing the paid out game media is also provided. When a predetermined amount of game media is stored in the storage unit, and the game media as a prize is further paid out, the game media is discharged. When the situation overflows from the storage unit, the game control means notifies the payout control means of the situation. Then, when the storage amount of the storage unit becomes equal to or less than the predetermined amount, the fact is notified.

[0005] The paid-out game medium is detected by game medium detecting means such as a sensor or a switch. The detection signal of the game medium detecting means is input to the payout control means, and power for driving the game medium detecting means is supplied to the game medium detecting means from the payout control board on which the payout control means is mounted. You. The payout control means counts the number of payout game media based on the detection signal of the game medium detection means, and stops driving the payout mechanism when detecting that the expected number of game media have been paid out based on the count value. And so on.

However, in such a configuration, if a failure occurs in the payout control means in the gaming machine, it becomes impossible to control the counting of game media paid out from the payout mechanism.

[0007]

As described above, the game control means controls the shortage of the game media to be paid out as a prize and the excess storage of the game media paid out as a prize with respect to the game medium payout control. It is necessary to notify the payout control means. When receiving the notice, the payout control means stops the operation of the payout mechanism. That is, while the payout control means consequently performs the same operation, a plurality of types of notifications are sent from the game control means to the payout control means. It is desirable that information transmission from the game control means to the payout control means be as simple as possible from the viewpoint of saving program capacity in the game control means. This is because if the load required for information transmission is reduced, there is an advantage that the program capacity that can be used for game control increases accordingly.

[0008] Further, as described above, when a failure occurs in the payout control means, there is a problem in that it is impossible to control the game machine to count the number of game media paid out from the payout mechanism.

Therefore, the present invention can further reduce the load on information transmission relating to prize payout from the game control means to the payout control means, and continue to manage the paid out game media even if a failure occurs in the payout control means. It is an object of the present invention to provide a gaming machine capable of performing such operations.

[0010]

A gaming machine according to the present invention comprises:
A game machine in which a player plays a predetermined game and pays out a prize game medium as a prize according to satisfaction of a predetermined condition, wherein a game control means for controlling the progress of the game, and a payout of the game medium , A payout control means for controlling the payout means based on a command from the game control means, and a prize game medium detecting means for detecting the payout of the prize game medium, wherein the prize is provided in the game control means. The detection signal of the game medium detecting means is input, the payout state of the prize game medium can be specified, and the game control board equipped with the game control means has a power supply means for supplying power to the prize game medium detecting means. There is a plurality of prohibition conditions that prohibit payout of premium game media, and the game control means pays out premium game media even if any of the plurality of prohibition conditions is satisfied. And performing a process of transmitting a common dispensing prohibited state specifies command indicating to prohibit relative dispensing control means.

[0011] When the prohibition condition is released and none of the prohibition conditions is satisfied, the game control means determines whether the prize is free regardless of which of the plurality of prohibition conditions is satisfied. It may be configured to perform processing of transmitting a common payout permission state designation command indicating permission to pay out game media to the payout control means.

It is preferable that the detection signal of the premium game medium detecting means is input to both the game controlling means and the payout controlling means.

It is possible to pay out a lending game medium to be lent to a player in response to a lending request. The detection signal of the means is input, the payout state of the lending game medium can be specified, and the power supply means for supplying power to the lending game medium detection means is mounted on the payout control board on which the payout control means is mounted. It may be configured.

The game control means includes storage means for storing the number of prize game media for which payout has not been completed, and when a prize is generated, the expected payout number of the prize game medium according to the prize is stored in the storage means. May be added to the stored value, and the number of payouts of the prize game medium specified by the detection signal of the prize game medium detection means may be subtracted from the storage value stored in the storage means.

The game control means can transmit to the payout control means a command for designating the number of payouts of the prize game medium, and when the payout of the prize game medium based on the previously transmitted command for specifying the number of payouts is completed. Regardless of whether or not the command is issued, a command for designating a new payout number may be transmitted to the payout control means.

A storage state detecting means for detecting whether or not a predetermined amount or more of the game medium is stored in a storage portion in which the paid out game medium is stored, wherein the game control means comprises:
When the storage state detection means detects that a predetermined amount or more of game media is stored in the storage unit, it may be configured to determine that the prohibition condition is satisfied.

The game control means includes a game medium exhaustion detecting means for detecting whether or not a predetermined amount or more of the game medium supplied to the payout means is secured. It may be configured to determine that the prohibition condition is satisfied when it is detected that the above condition is not secured.

When the game control means transmits a command to the payout control means, the game control means may be configured to output the command only once so as to be receivable.

The command includes command data and a capture signal for instructing the capture of the command data, and the payout control means captures the command data in response to the capture signal being output from the game control means. It may be.

The game control means executes the game control process based on the occurrence of a timer interrupt that occurs periodically, and updates a counter used for controlling the game with a surplus time required for the game control process. Execute the process to
The configuration may be such that interrupt prohibition is set during the process of updating the counter with excess time.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine as viewed from the front, and FIG. 2 is a front view of the front of the gaming board with the glass door frame removed. In the following embodiments, a pachinko gaming machine will be described as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine, and may be, for example, a slot machine. Further, the present invention can be applied to an image-type gaming machine.

The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape and provided in a game frame so as to be openable and closable. The game frame includes a front frame (not shown) installed to be freely openable and closable with respect to the outer frame, a mechanism plate to which mechanical components and the like are attached, and various components attached to them (excluding a game board described later). And a structure including:

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray (upper tray) 3. A surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided below the hitting ball supply tray 3. Glass door frame 2
A game board 6 is detachably attached to the back of the game board. The game board 6 is a structure that includes a plate-like body constituting the board and various components attached to the plate-like body. A game area 7 is formed on the front of the game board 6.

In the vicinity of the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each of which variably displays a symbol as identification information. The variable display device 9 includes, for example, “left”, “middle”,
There are three “right” variable display sections (symbol display areas).
Below the variable display device 9, a start winning port 14 is provided. The winning ball that has entered the start winning port 14 is guided to the back of the game board 6 and detected by the starting port switch 14a. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. Variable winning ball device 1
5 is opened by a solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). Opening / closing plate 20
Is a means for opening and closing the special winning opening. One of the winning balls guided to the back of the game board 6 from the opening / closing plate 20 (V winning area)
The winning ball entered is detected by the V winning switch 22, and the winning ball from the opening / closing plate 20 is detected by the count switch 23. On the back of the game board 6, there is also provided a solenoid 21A for switching the route in the special winning opening. In addition, a start storage display 18 having four displays for displaying the number of effective winning balls in the start winning opening 14, that is, the number of start memories, is provided below the variable display device 9. In this example, the start storage display unit 18 increases the number of lit display units by one each time there is a valid start prize, with four as an upper limit. Then, each time the variable display of the variable display device 9 is started, the number of the lit display unit is reduced by one.

When a game ball wins at the gate 32, variable display of the display of the ordinary symbol display 10 by the 7-segment LED is started. When the stop symbol on the ordinary symbol display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined number of times and for a predetermined time. In the vicinity of the ordinary symbol display 10, an ordinary symbol start storage display 41 having four displays for displaying the number of winning balls entering the gate 32 is provided. In this example, each time there is a prize in the gate 32, the normal symbol start storage display 41 increases the number of lit display units one by one, with the upper limit being four. Then, each time the opening control of the variable winning ball device 15 is performed, the number of the lit display units is reduced by one.

The game board 6 has a plurality of winning ports 24, 29,
30 and 33 are provided, and the winning holes 24, 29 and 3 for the game balls are provided.
The prizes for 0 and 33 are determined by the prize opening switches 24a and 24a, respectively.
29a, 30a and 33a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A ceiling lamp 28 is provided on the outer periphery of the game area 7.
a, a left frame lamp 28b and a right frame lamp 28c. Further, decorative LEDs are installed around each structure (such as a special winning opening) in the game area 7.

In this example, the prize ball lamp 51 is turned on when there is a remaining prize ball near the left frame lamp 28b.
Is provided, and near the top frame lamp 28a, a ball-out lamp 52 that is turned on when the supply ball has run out is provided.
Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and that allows a ball to be lent by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is usable. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The game ball fired from the hitting ball launching device enters the game area 7 through the hitting ball rail, and then descends from the game area 7. When a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 14a, the special display starts variable display (variation) on the variable display device 9 if the variable display of the symbol can be started. If it is not in a state where the variable display of the symbol can be started, the number of start storages is increased by one.

The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of the special symbols at the time of stopping is a combination of the big hit symbols, the game shifts to the big hit game state. That is, the opening and closing plate 20
Is released until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the V winning area while the opening and closing plate 20 is open and is detected by the V winning switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of special symbols in the variable display device 9 at the time of stoppage is a combination of big hit symbols with a probability variation, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained.

When the ball hits the gate 32, the display number as the normal symbol on the ordinary symbol display 10 changes continuously. Also, when the stop symbol in the ordinary symbol display 10 is a predetermined symbol (hit symbol),
The variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the ordinary symbol display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIGS. FIG. 3 is a back view of the gaming machine as viewed from the back. FIG. 4 is a rear view of the mechanism plate to which various members are attached as viewed from the rear side of the gaming machine.

As shown in FIG. 3, on the rear side of the gaming machine, a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control board (mainly a game control microcomputer) on which a game control microcomputer and the like are mounted. (Substrate) 31 is provided. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control and the like is mounted. Furthermore, various decorations L provided on the game board 6
ED, special symbol start memory display 18, normal symbol start memory display 41, decorative lamp 25, top frame lamp 28a, left frame lamp 28b, right frame lamp 2 provided on the frame side
8c, a lamp control board 3 on which a lamp control means for controlling lighting of the prize ball lamp 51 and the ball out lamp 52 is mounted.
5. A sound control board 70 on which sound control means for controlling sound generation from the speaker 27 is also provided. Also, D
A power supply board 910 on which a power supply circuit for generating C30V, DC21V, DC12V and DC5V is mounted, and a launch control board 91 are provided.

A terminal board 160 having terminals for outputting various types of information to the outside of the gaming machine is provided above the gaming machine on the rear side. Terminal board 160
At least, a ball-out terminal for introducing the output of the ball-out detection switch and externally outputting the same, a prize-ball terminal for externally outputting a prize-ball information signal, and an externally output ball lending number signal. A ball lending terminal is provided. In the vicinity of the center, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is provided.

Further, storage contents holding means (for example, a backup RA which can hold the contents even when the power supply is stopped) included in each board (the main board 31, the payout control board 37, etc.).
A switch board 190 provided with a clear switch 921 as an operation means for clearing the backup data stored in M) is provided. Switch board 1
The 90 is provided with a clear switch 921 and a connector 922 connected to another substrate such as the main substrate 31.

The game balls stored in the storage tank 38 pass through the guide rail 39 and, as shown in FIG.
Through 86, it reaches a ball dispensing device covered with a prize ball case 40A. At the top of the ball payout device, a ball out switch 187 as a game medium out detecting means is provided. When the ball-out switch 187 detects the ball-out, the payout operation of the ball payout device stops. The ball out switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage. The ball out switch 167 for detecting a shortage of replenishment balls in the storage tank 38 is also provided in the upstream portion (the storage tank 38) of the guide rail 39. (A part close to). When the ball-out detection switch 167 detects a shortage of game balls, the replenishment mechanism provided on the game machine installation island supplies the game machines with game balls.

The ball out switch 187 is locked at a position where it is possible to detect the presence of about 27 to 28 game balls in the payout ball passage leading to the ball payout device. That is, the out-of-ball switch 187 outputs the maximum payout amount of one unit of the prize ball (15 in this embodiment) and the maximum payout amount of one unit of the ball lending (100 yen: 25 in this embodiment).
) Is installed at a position where it can be confirmed that the above is secured.

The game balls paid out from the ball payout device are guided to the hitting plate 3 provided on the front face of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball receiving tray 4 provided on the front of the pachinko gaming machine 1 is formed.

A large number of game balls as prizes based on winnings and game balls based on ball lending requests are paid out and the hitting ball supply tray 3 becomes full. Finally, after the game balls reach the contact 45, the game balls are further added. When paid out, the game balls are guided to the surplus ball tray 4 via the surplus ball passage 46. When the game balls are further paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detecting means, and the full tank switch 48 as the storage state detecting means is turned on. That is, the full tank switch 48 indicates that the storage amount in the surplus ball tray 4 as the player-side storage means exceeds the storage allowable amount.
Is detected by In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the driving of the firing device also stops.

As shown in FIG. 4, on the side of the ball dispensing device, a ball removing passage 191 is formed from a curve gutter 186 to a discharge port 192 at a lower portion of the gaming machine. Ball-free passage 19
A ball-pulling lever 193 is provided at the upper part of the game ball 1, and when the ball-pulling lever 193 is operated by a game clerk or the like, a game ball path is formed from the guide rail 39 to the ball-pulling path 191, and is stored in the storage tank 38. The game ball that has been played is discharged from the discharge port 192 to the outside of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of the ball payout device 97. In this example, a ball payout device 97 is formed inside three cases 140, 141, and 142 as the prize ball case 40A. Holes 170 and 171 communicating with the ball passage below the ball cut switch 187 are provided in the upper portions of the cases 140 and 141, and the game balls are provided in the holes 170
From 171, the ball flows into the ball payout device 97.

The ball payout device 97 includes a payout motor (for example, a stepping motor) 289 serving as a driving source. The rotational force of the payout motor 289 is transmitted to the gear 290 fitted on the rotation shaft of the payout motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted on the central axis of the gear 291. The game balls flowing from the holes 170 and 171 are dropped one by one into the ball passage 293 below the sprocket 292 by the concave portion of the sprocket 292.

The ball passage 293 is provided with a distribution member 311 for switching the flow path of the game ball. The distributing member 311 is driven by the solenoid 310, and when the prize ball is paid out, the game ball falls down on one of the flow paths in the ball path 293, and when the ball is lent, the game ball flows on the other flow path in the ball path 293. To fall. The payout motor 289 and the solenoid 310 are controlled by a payout control CPU mounted on the payout control board 37. Further, the payout control CPU includes a main board 31.
The payout motor 289 and the solenoid 310 are controlled in accordance with a command from a game control CPU mounted on the CPU.

A prize ball sensor (prize ball count switch) 301A for detecting a game ball paid out by the ball payout device is provided below the down flow path selected at the time of paying out the prize ball.
A ball lending sensor (ball lending count switch) 301B for detecting game balls paid out by the ball payout device is provided below the down flow path selected at the time of ball lending. The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on the detection signals.

In the periphery of the gear 291, there is formed a projection for forming a payout motor position sensor. The protrusion allows the light from the light emitting body (not shown) to pass through or block the light receiving unit (not shown) of the payout motor position sensor with the rotation of the gear 291, that is, the rotation of the payout motor 289. I do. The payout control CPU can recognize the position of the payout motor 289 based on the detection signal from the light receiving unit.

The ball payout device may be configured to perform both prize ball payout and ball lending, but a ball payout device for paying out prize balls and a ball payout device for lending balls are separately provided. It may be. Further, for example, the rotation direction of the sprocket may be changed to separate the prize ball payout and the ball lending, or a ball payout device having any structure other than the ball payout device 97 exemplified in the present embodiment. The present invention can be applied even when using.

FIG. 6 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 6 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a firing control board 91, and a symbol control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
, A gate switch 32a, a starting port switch 14a, a V winning switch 22, a count switch 23, a winning port switches 24a, 29a, 30a,
33a, full tank switch 48, ball out switch 187,
Prize ball count switch 301A and clear switch 9
Switch circuit 5 for providing a signal from circuit 21 to basic circuit 53
8, a solenoid 16 for opening and closing the variable winning ball device 15,
A solenoid 21 for opening and closing the opening / closing plate 20 and a solenoid circuit 59 for driving a solenoid 21A for switching a path in the special winning opening in accordance with a command from the basic circuit 53 are mounted.

Although not shown in FIG. 6, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the starting port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 24a, 29a, 30a,
33a, full tank switch 48, ball out switch 187,
Switches such as the award ball count switch 301A may be called sensors. That is, a game medium detecting means capable of detecting a game ball (in this example, a game ball detecting means)
If so, its name does not matter. The starting port switch 14a, the count switch 23, and the winning port switch 2
4a, 29a, 30a, and 33a are examples of winning detection means. The prize ball count switch 301A is an example of a payout detection unit, and a ball lending count switch 301B described later is an example of a lending detection unit.

Also, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of a jackpot, the effective start information indicating the number of start winning balls used for starting the variable display of symbols on the variable display device 9, and the probability fluctuation are obtained. An information output circuit 64 for outputting an information output signal such as probability change information indicating occurrence to an external device such as a hall computer is mounted.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, and an R as storage means (means for storing variation data) used as a work memory.
AM55, a CPU 5 that performs a control operation according to a program
6 and an I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 therein.
The OM 54 and the I / O port unit 57 may be externally mounted or built-in.

A part or all of the RAM (may be a CPU built-in RAM) 55 is a backup RAM that is backed up by a backup power supply created on the power supply board 910. That is, even if the power supply to the gaming machine is stopped,
Some or all of the contents of 55 are saved.

A hit ball launching device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is provided with the start memory display 18, the ordinary symbol start memory display 41 and the decorative lamp 25 provided on the game board. While performing display control, display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the award ball lamp 51, and the ball out lamp 52 provided on the frame side is performed. The display control of the variable display device 9 for variably displaying a special symbol and the ordinary symbol display 10 for variably displaying an ordinary symbol is controlled by a symbol control board 80.
This is performed by display control means mounted on the device.

FIG. 7 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 7, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port unit 57. The detection signal from the ball cut switch 187 is also input to the I / O port unit 57 of the main board 31 via the relay board 72 and the relay board 71.

The CPU 56 of the main board 31 checks whether the detection signal from the ball out switch 187 indicates that the ball is out.
Alternatively, if the detection signal from the full tank switch 48 indicates a full tank state, a payout control command indicating that the payout should be stopped is transmitted. When receiving the payout control command indicating that the payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the I / O port section 57 of the main board 31 via the relay board 72 and the relay board 71, and the payout control is performed via the relay board 72. It is input to the input port 372b of the substrate 37. Prize ball count switch 30
1A is provided in the payout mechanism portion of the ball payout device 97, and detects a prize ball payout ball actually paid out.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
, A payout control command indicating the number of winning balls is input. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. The payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 includes an I / O port 372a.
A payout control command is input via the, and the ball payout device 97 is driven in accordance with the payout control command to perform the prize ball payout. In this embodiment, the payout control CPU 371
A one-chip microcomputer, at least RA
M is built-in.

In the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside 70 and 571. As the buffer circuits 620 and 68A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal inputted from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 is connected to the output port 3
A ball lending number signal indicating the number of lending balls is output to the terminal board 160 via 72c. Further, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
Detection signals from a ball lending count switch 301B and a payout motor position sensor for detecting the rotational position of the payout motor 289 are input to the relay board 72b via the relay board 72. The ball lending count switch 301B is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid lending balls. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism of the ball payout device 97 via the output port 372c and the relay board 72, and the distribution solenoid 3
The drive signal to 10 is transmitted to the distribution solenoid 310 in the payout mechanism of the ball payout device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

The card unit 50 is equipped with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the operation of the player, a ball lending switch signal and a return switch signal are given via the payout control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is input port 372b and output port 3
It is exchanged via 72e.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connection state / non-connection state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the payout control board 37.

The payout control board 37 of the payout control board 37
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 and pays out a predetermined number of loaned balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 sets the card unit 5
The EXS signal for 0 falls. Thereafter, if the BRDY signal from the card unit 50 is not in the ON state,
The winning ball payout control is executed.

As described above, all signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, a power-off signal is also input from the power supply board 910 to the payout control board 37. The power-off signal is input to the non-maskable interrupt (NMI) terminal of the payout control CPU 371. Further, the payout control board 3
7 is backed up by a backup power supply created on the power supply board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is stored for a predetermined period.

FIG. 8 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31, a symbol control board 80, a sound control board 70, and a lamp control board 35.
And it is installed independently of the electric component control boards such as the payout control board 37 and generates voltages used by each electric component control board and mechanical components in the gaming machine. In this example, AC24
V, VSL (DC + 30V), DC + 21V, DC + 12
V and + 5V DC. A capacitor 916 serving as a backup power supply, that is, a memory holding unit, is
It is charged from C + 5V, that is, from a power supply line for driving an IC or the like on each substrate. Note that VSL is generated in the rectifier circuit 912 by rectifying and boosting 24 VAC with a rectifier. VSL is a solenoid drive power supply.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
C converter 913 includes one or more converters I
C922 (only one is shown in FIG. 8), and generates + 21V, + 12V, and + 5V based on VSL, and outputs it to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 922. Therefore, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as +30 V, +12 V, +5 V, etc., decreases relatively slowly. The connector 915 is connected to, for example, a relay board, and power of a voltage required for each electric component control board and a mechanical component is supplied from the relay board.

However, the power supply board 910 may be provided with each connector to each electric component control board, and the power supply board 910 may supply each voltage to each board without passing through the relay board. FIG. 8 shows one connector 9.
Although 15 is shown as a representative, a connector is provided for each electric component control board.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is a backup RAM of the electric component control board when the power supply to the gaming machine is stopped (RAM backed up by a power supply, that is, a backup storage unit that can be in a storage state even when the power supply is stopped).
Is a backup power supply that supplies power so that the storage state can be maintained. A backflow preventing diode 9 is provided between the + 5V line and the backup + 5V line.
17 is inserted. In this embodiment, +5 V for backup is applied to the main board 31 and the payout control board 3.
7 is supplied.

A power supply monitoring IC 902 as a power supply monitoring circuit is mounted on the power supply board 910. The power supply monitoring IC 902 detects the occurrence of a power supply stop to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, the VSL voltage is a predetermined value (in this example, +
22V) or less, a power cutoff signal is output on the assumption that power supply has stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. Power supply monitoring IC
The power cut-off signal from 902 is supplied to the main board 31, the payout control board 37, and the like. The game control means mounted on the main board 31 or the payout control means mounted on the payout control board 37 responds to the input of the power-off signal by the backup RA.
A power supply stop process, which is a process for protecting the storage contents of M, is executed.

The predetermined value for the power supply monitoring IC 902 to detect the stop of the power supply is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. The power supply monitoring IC 902 is a CPU
For driving circuit elements such as (+5 in this example)
V), and is configured to monitor the voltage immediately after conversion from AC to DC, so that the monitoring range can be extended for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Further, when VSL (+30 V) is used as the monitoring voltage, the voltage supplied to various switches of the gaming machine is +12 V
Therefore, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, by monitoring the voltage of the +30 V power supply, it is possible to detect a decrease in the voltage of +12 V generated after the generation of +30 V before the voltage starts to drop.

When the voltage of the +12 V power supply drops, the switch output comes to an on state. However, if the stop of the power supply is recognized by monitoring the +30 V power supply voltage that drops faster than +12 V, the switch output will turn on. It is possible to enter a state of waiting for power supply recovery before entering a state in which the switch output is not detected.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the power supply monitoring circuit can supply a power-off signal to the plurality of electric component control boards. No matter how many electrical component control boards require a power-off signal, it is sufficient that only one power supply monitoring means is provided. Even if the restoration control based on the backup storage contents is performed at the time of restoration, the cost of the gaming machine does not increase so much.

In the configuration shown in FIG. 8, the detection signal (power-off signal) of the power-supply monitoring IC 902 is supplied to the respective electrical component control boards (for example, the Although transmitted to the board 37), for example, a configuration in which one detection signal is transmitted to the relay board and the same signal is distributed from the relay board to each electric component control board may be employed. Further, a buffer circuit may be provided according to the number of substrates that require a power-off signal. Further, regarding the power-off signal output to the main board 31 and the payout control board 37,
The monitoring voltage of the power monitoring circuit that outputs the power-off signal may be different.

FIG. 9 is a circuit diagram showing an electrical control form of the prize ball count switch 301A and the ball lending count switch 301B. As shown in FIG. 9, various power supply voltages are supplied from the power supply board 910 to the main board 31 via the power supply connector 580. However, the switch circuit 58 of the main board 31 is connected to the winning ball count switch 301A. The power supply voltage (+12 V) is supplied via the power supply. In a portion of the switch circuit 58 related to the award ball count switch 301A, the +12 V voltage supplied to the award ball count switch 301A is stabilized by a diode 581, a capacitor 582 one of which is grounded, and a resistor 583 one of which is grounded. You. The detection signal of the prize ball count switch 301A is output from the Zener diode 5 of the switch circuit 58.
87, a buffer circuit 588 and a buffer circuit 589, which are input to the I / O port 57.
Noise is removed by a resistor 584 having one grounded, a capacitor 585 having one grounded, and a resistor 586 inserted between the capacitor 585 and the buffer circuit 589.

Although various power supply voltages are supplied to the payout control board 37 from the power supply board 910 via the power supply connector 380, the ball rental count switch 301B is provided with the switch circuit 382 of the payout control board 37. The power supply voltage (+12 V) is supplied via the power supply. The configuration of the portion of the switch circuit 383 related to the ball lending count switch 301B may be the same as the configuration of the portion related to the prize ball count switch 301A of the switch circuit 58 of the main board 31.

As described above, in this embodiment, the prize ball count switch 301A as a premium game medium detecting means.
Then, power is supplied from the main board 31. Therefore, even if a failure occurs in the payout control board 37, for example, it is not impossible to detect a game ball paid out as a prize. Further, since the detection signal of the prize ball count switch 301A is input to both the main board 31 and the payout control board 37, it is possible to execute control based on the detection signal in both the game control means and the payout control means. it can.

FIGS. 10 and 11 are explanatory diagrams showing the assignment of output ports in this embodiment. Figure 1
As shown by 0, the output port 0 is an output port for an INT signal of a control command transmitted to each electric component control board. Also, 8-bit data of the payout control command transmitted to the payout control board 37 is output from the output port 1,
The 8-bit data of the display control command transmitted to the symbol control board 80 is output from the output port 2, and the 8-bit data of the lamp control command transmitted to the lamp control board 35 is output from the output port 3. And FIG.
8, the 8-bit data of the sound control command transmitted to the sound control board 70 is output from the output port 4.

The output port 5 is connected to the information output circuit 6
4, various information output signals reaching the information terminal board 34 and the terminal board 160, that is, output data of information related to control are output. From the output port 6, a solenoid 16 for opening and closing the variable winning ball device 15, a solenoid 21 for opening and closing the opening and closing plate 2 of the special winning opening, and a solenoid 21 for switching a path in the special winning opening.
A drive signal for A is output.

As shown in FIG. 11, the payout control board 37,
An output port that outputs each INT signal (payout control signal INT, display control signal INT, lamp control signal INT, and sound control signal INT) output to the symbol control board 80, the lamp control board 35, and the sound control board 70. Output port 0), payout control signals CD0 to CD7 as command data of a payout control command, display control signals CD0 to CD7 as command data of a display control command, and lamp control signals CD0 to CD7 as command data of a lamp control command. Output ports (output ports 1 to 4) for outputting sound control signals CD0 to CD7 as command data of the sound control command are different ports.

Therefore, when outputting the INT signal, the payout control signals CD0 to CD7 and the display control signals CD0 to CD0 are erroneously output.
The possibility of changing CD7, the lamp control signals CD0 to CD7, and the sound control signals CD0 to CD7 is reduced. Further, when outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7, or the sound control signals CD0 to CD7,
The possibility of changing the T signal is reduced. As a result, a command from the game control means of the main board 31 to each electric component control board is transmitted more reliably. Further, all the INT signals are configured to be output from the output port 0.
The burden of NT signal output processing is reduced.

FIG. 12 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 12, bits 0 to 7 of the input port 0 include winning opening switches 33a, 24a, 29a, 30a,
The detection signals of the starting port switch 14a, the count switch 23, the V winning switch 22, and the gate switch 32a are input. The detection signals of the prize ball count switch 301A, the full tank switch 48, the ball out switch 187, the count switch short-circuit signal, and the clear switch 921 are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. As described above, the detection signal of the clear switch 921 is input to the same input port (8 bits) to which the detection signal of the switch for detecting the game ball is input.

Next, the operation of the gaming machine will be described. Figure 1
3 is a flowchart showing a main process executed by the game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When the power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts the main processing after step S1. In the main process, the CPU 56 first
Make the necessary initial settings.

In the initial setting process, the CPU 56 first sets interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and the stack pointer designated address is set to the stack pointer (step S3). Then, the internal device registers are initialized (step S4). After initializing a built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to an accessible state (step S6).

CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). Also, CTC has two external clock / timer trigger inputs CLK / TRG2, 3
And two timer outputs ZC / TO0,1.

CPU 5 used in this embodiment
6, the following three modes are prepared as maskable interrupt modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device that has issued the interrupt request receives an RST instruction (1 byte) or a CALL instruction (3 bytes).
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is the interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Next, the CPU 56 checks the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). If ON is detected in the confirmation, the CPU 56 executes a normal initialization process (steps S11 to S1).
5). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the ON state of the clear switch signal is at a high level (see FIG. 12). Also, for example, the game store clerk can use the clear switch 92.
By starting the power supply to the gaming machine while turning 1 on, the initialization process can be easily executed. That is, the RAM can be cleared.

When the clear switch 921 is not in the ON state, when power supply to the gaming machine is stopped, data protection processing for the backup RAM area (for example, processing for stopping power supply such as addition of parity data) is performed. It is confirmed whether or not it has been performed (step S8). In this embodiment, when the power supply is stopped, a process for protecting the data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that such a protection process has not been performed, the CPU 56 executes an initialization process.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop processing. For example, if “55H” is set in the backup flag area, it means that there is a backup (on state), and “55H” is set.
If a value other than "H" is set, it means that there is no backup (off state).

When the backup is confirmed, the CPU 5
No. 6 performs data check (parity check in this example) of the backup RAM area (step S9). In this embodiment, clear data (00) is set in a checksum data area, and a checksum calculation start address is set in a pointer. In addition, the number of checksum calculations corresponding to the number of data to be checked is set. Then, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the value of the pointer is increased by one, and the value of the number of checksum calculations is decremented by one. The above process is repeated until the value of the number of checksum calculations becomes zero. When the number of checksum calculation times becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area,
The inverted data is used as a checksum.

In the power supply stop processing, the checksum is calculated by the same processing as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. If power is restored after an unexpected power outage or other power outage, backup RA
Since the data in the M area should be stored, the check result (comparison result) becomes normal (match). If the check result is not normal, it means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state at the time of stopping the power supply, the initialization processing executed at the time of turning on the power other than the recovery from the stop of the power supply is executed.

If the check result is normal, the CPU 56
Performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state at the time of stopping the power supply (step S10). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to that address.

As described above, the backup RA using the backup flag and the check data such as the checksum is performed.
By confirming whether or not the data in the M area is stored, the gaming state can be accurately returned to the state at the time of stopping the power supply. That is, the reliability of the state restoration processing based on the data in the backup RAM area is improved. In this embodiment, whether or not the data in the backup RAM area is stored is confirmed by using both the backup flag and the check data. However, only one of them may be used. That is, one of the backup flag and the check data may be used as a trigger for executing the state restoration processing.

In the initialization process, the CPU 56 first sets R
An AM clear process is performed (step S11). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
Special symbol process flag, payout command storage pointer,
A work area setting process for setting an initial value to a flag for performing a process selectively according to a control state, such as a winning ball flag, a running out flag, and a payout stop flag, is performed (step S).
12). Further, a process of transmitting a payout stop release command (a payable state designation command) indicating that the payout from the ball payout device 97 is possible is performed to the payout control board 37 (step S13). Further, other sub-boards (lamp control board 35, sound control board 70, symbol control board 8
A process of transmitting an initialization command for initializing 0) to each sub-board is executed (step S14). As the initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing the prize ball lamp 51 and the ball out lamp 52 to be turned off (for the lamp control board 35) And).

In the initialization process, a payout possible state designation command is always transmitted to the payout control board 37. what if,
Even if the state of the gaming machine is a state in which the payout from the ball payout device 97 is not possible, in the game control processing executed immediately thereafter, the fact is detected, and the payout indicating that the payout is not possible is performed. There is no problem because the stop command (dispensing stop state designation command) is transmitted. In the process of transmitting the payout possible state designation command and the initialization command to other sub-boards, for example, an address of a table (ROM area) in which each command is set is set in a pointer, and the command setting process described later is performed. A simple processing routine may be called.

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S15). That is,
A value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the display random number updating process (step S17) and the initial value random number updating process (step S18) are repeatedly executed in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt is prohibited (step S16), and when the display random number update process and the initial value random number update process are completed, the interrupt is enabled. Is performed (step S19). The display random number is a random number for determining a symbol to be displayed on the variable display device 9, and the display random number update process is a process of updating the count value of a counter for generating the display random number. . The initial value random number updating process is a process of updating the count value of a counter for generating an initial value random number. The initial value random number is a random number for determining an initial value of a count value of a counter for generating a random number for determining whether or not to make a big hit (a random number generation counter for big hit determination). In the game control process described later, when the count value of the big hit determination random number generation counter makes one round, an initial value is set in the counter.

When the display random number update processing is executed, the interrupt is prohibited because the display random number update processing is also executed in the timer interrupt processing described later. This is to avoid competing with. That is, if a timer interrupt occurs during the process of step S17 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value is lost. There are cases. However, such an inconvenience does not occur if the interrupt is prohibited during the processing in step S17.

When a timer interrupt occurs, the CPU 56
After performing the register save processing (step S20), the game control processing of steps S21 to S32 shown in FIG. 14 is executed. In the game control process, the CPU 56 first
Through the switch circuit 58, detection signals of switches such as the gate switch 32a, the starting port switch 14a, the count switch 23, and the winning port switches 33a, 24a, 29a, 30a are input, and their states are determined (switch processing: Step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S23).
The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

Further, the CPU 56 performs a special symbol process (step S26). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S27). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. And the value of the normal symbol process flag is
It is updated during each process according to the game state.

Next, the CPU 56 sets a display control command relating to the special symbol in a predetermined area of the RAM 55 and transmits the display control command (special symbol command control process: step S28). Further, a process of setting a display control command relating to a normal symbol in a predetermined area of the RAM 55 and transmitting the display control command is performed (ordinary symbol command control process: step S29).

Further, the CPU 56 performs an information output process of outputting data such as big hit information, start information, and probability fluctuation information supplied to the hall management computer (step S30).

The CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). The solenoid circuit 59 drives the solenoids 16, 21 and 21A in response to a drive command in order to open or close the variable winning prize ball device 15 or the opening / closing plate 20 and to switch the game ball passage in the special winning opening. I do.

Then, the CPU 56 sets the winning opening switch 3
A prize ball process for setting the number of prize balls based on the detection signals of 3a, 24a, 29a, and 30a is executed (step S32). Specifically, the winning opening switches 33a, 24
A payout control command indicating the number of prize balls is output to the payout control board 37 in response to the winning detection based on the fact that a, 29a and 30a are turned on. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a payout control command indicating the number of winning balls. afterwards,
The contents of the register are restored (step S33), and the interrupt permission state is set (step S34).

With the above control, in this embodiment, the game control process is started every 2 ms.
In this embodiment, the game control process is executed in the timer interrupt process, but in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set.
The game control process may be executed in the main process.

FIG. 15 is a flowchart showing an example of a special symbol processing program executed by the CPU 56. The special symbol processing shown in FIG.
Is a specific process of step S26 in the flowchart of FIG. When performing the special symbol process process, the CPU 56 performs a variation reduction timer subtraction process (step S310), and then performs steps S300 to S300 according to the internal state.
309 is performed. The fluctuation shortening timer is a timer for setting the fluctuation time when the fluctuation time of the special symbol is shortened.

Special symbol change waiting process (step S30)
0): Start-up switch 14 after hitting the ball in the start-up prize port 14
Wait for 7 to turn on. When the starting port switch 14 is turned on, if the number of stored start winnings is not full, the number of stored starting winnings is incremented by one, and a random number for determining a jackpot is extracted.

Special symbol determination processing (step S301):
When the state in which the variable display of the special symbol can be started, the number of start winning prize stored is confirmed. If the starting prize memory number is not 0,
It is determined whether to make a big hit or an out according to the value of the extracted big hit determining random number.

Stop symbol setting processing (step S302):
The stop symbol of the left and right middle symbols is determined.

Reach operation setting processing (step S30)
3): It is determined whether or not the reach operation is performed based on the combination of the left and right stop symbols, and if the reach is determined, the fluctuation time at the time of the reach is determined according to the value of the fluctuation pattern determination random number. decide.

All symbol variation start processing (step S30)
4): Control is performed so that all symbols are started to change in the variable display section 9. At this time, with respect to the symbol control board 80,
The left and right middle final stop symbols and information instructing the variation mode are transmitted. When processing is completed, the internal state (process flag)
Is updated to shift to step S305.

All symbols stop wait processing (step S30)
5): When a predetermined time (time indicated by the fluctuation reduction timer in step S310) has elapsed, all the symbols displayed on the variable display section 9 are stopped. If the stop symbol is a combination of big hit symbols, the internal state (process flag) is updated so as to shift to step S306. Otherwise, the internal state is changed to step S300.
Update to move to.

Opening process of opening the special winning opening (step S30)
6): Control for opening the special winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. Also, a big hit flag (a flag indicating that a big hit is being made) is set. Upon completion of the process, the internal state (process flag) is updated so as to shift to step S307.

Processing during opening of the special winning opening (step S30)
7): Control for transmitting a display control command for the special winning opening round display to the symbol control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. When the final closing condition of the special winning opening is satisfied, the internal state is updated so as to shift to step S308.

Specific area effective time processing (step S30)
8): The presence or absence of the passage of the V winning switch 22 is monitored, and a process of confirming the establishment of the big hit game state continuation condition is performed. If the condition of the jackpot game state continuation is satisfied and there are still remaining rounds, the internal state is updated to shift to step S306. If the big hit game state continuation condition is not satisfied within the predetermined effective time, or if all rounds have been completed, the internal state is changed to step S
309 is updated.

Big hit end processing (step S309): A display for notifying the player that the big hit gaming state has ended is performed. When the display is completed, the internal state is updated so as to shift to step S300.

FIG. 16 is an explanatory diagram showing an example of a command form of a control command transmitted from the main board 31 to another electric component control board. In this embodiment, the command data of the control command has a 2-byte configuration, the first byte represents MODE (classification of command), and the second byte is E.
XT (command type). The first bit (bit 7) of MODE data is always "1", and the first bit (bit 7) of EXT data is always "0". As described above, the control command transmitted to the electric component control board is composed of a plurality of command data, and each command can be distinguished by the first bit. The command form shown in FIG. 16 is an example, and another command form may be used. For example, a control command composed of one byte or three or more bytes may be used.

FIG. 17 shows 8-bit control signals CD0 to CD constituting a control command for each electric component control means.
FIG. 7 is a timing chart showing the relationship between 7 (command data) and an INT signal (capture signal). As shown in FIG.
When a period indicated by A has elapsed since the ODE or EXT data was output to the output port (any one of the output ports 1 to 4), the CPU 56 outputs an INT signal which is a signal indicating data output. Set to high level (ON data). When the period indicated by B elapses therefrom, the INT signal is set to low level (off data). Further, when there is data to be transmitted next, that is, after MODE data transmission, the data of the second byte is output to the output port after a period indicated by C. Regarding the data of the second byte, the period of A and B is 1
This is the same as the case of the byte. Thus, the capture signal is output for each of the MODE and EXT data.

The period A is a period for the CPU 56 to prepare for command transmission, that is, a period required for processing for setting a control command in the buffer, and a period for stabilizing data on the control signal line. That is, after the control signals CD0 to CD7 are output on the control signal line, an INT signal is output as a capture signal after a lapse of a predetermined period (period A: a part of the off output period). Also,
The period B (ON output period) is a period for stabilizing the INT signal. The period C (a part of the off-output period) is a period set so that the electric component control means can reliably take in data. In periods B and C,
The data on the signal line does not change. That is, the data output is maintained until the periods B and C elapse.

In this embodiment, a payout control command to the payout control board 37, a display control command to the symbol control board 80, a lamp control command to the lamp control board 35, and a sound control command to the sound control board 70 are: It is transmitted using the same command transmission processing routine (common module). Therefore, the period of B and C, that is, the period from the rise of the INT signal for the first byte to the start of transmission of the second byte of data, is longer than the reception processing time in the electric component control means, which takes the longest time for command reception processing. Is also set to be longer.

Each electric component control means detects that the INT signal has risen, and starts a process of fetching 1-byte data by, for example, an interrupt process.

Since the periods B and C are longer than the reception processing time of the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing for each electric component control means by the common module. However, any of the electric component control means can reliably receive the control command from the game control means.

After a predetermined period has elapsed after the execution of the INT signal output processing, the CPU 56 is ready to transmit the next data. The predetermined period (period B and C) is set to IN.
It is longer than a period (period A) from transmission of data before the T signal output processing to start of output of the INT signal. As described above, the period A is a stabilization period in the command signal line, and the periods B and C are periods for securing the time required for the receiving side to capture data. Therefore, by making the period A shorter than the periods B and C, it is possible to obtain an effect that the receiving-side electric component control means can reliably receive a command, and to complete the transmission of one command. This also has the effect of shortening the time required.

FIG. 18 is an explanatory diagram showing an example of the content of the payout control command. In the example shown in FIG.
Command F of ODE = FF (H) and EXT = 00 (H)
F00 (H) is a payout control command (payout permission state designation command: hereinafter also referred to as a payout possible state designation command) indicating that payout is possible. MODE =
FF (H), command FF01 of EXT = 01 (H)
(H) is a payout control command (payout prohibition state designation command: hereinafter, instructing that the payout should be stopped).
Also referred to as a payout stop state designation command. ). Also,
The command F0XX (H) of MODE = F0 (H) is a payout control command for specifying the number of winning balls. "XX" which is EXT indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout control means stops the prize ball payout and ball lending.
When the payout control command of (H) is received, it becomes possible to pay out prize balls and lend a ball. Further, when a payout control command specifying the number of winning balls is received, prize ball payout control according to the number specified by the received command is performed.

In this embodiment, when the payout control means receives the payout stop state designation command, both the ball lending and the prize ball payout are stopped, and both the ball lending and the prize ball payout are performed according to the payout possible state designation command. To return to the possible state, the payout prohibition instruction for the prize ball and the payout prohibition instruction for the ball lending may be different commands, and the payout permission instruction for the prize ball and the payout permission instruction for the ball lending may be different commands. Even in this case, a common command is sent from the game control means to the payout control means even if the conditions for prohibiting / permitting prize balls are different. Can be sent from the game control means to the payout control means.

Each control command is transmitted only once so that the payout control means can recognize it. Recognizable means that the level of the INT signal changes in this example, and is transmitted only once so as to be recognizable means that in this example, the INT signal is changed according to the first byte and the second byte of the command data. That is, the INT signal is output only once in a pulse form (rectangular wave form).

Next, a specific example of the switch processing (step S21) in the main processing will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch has been turned on, and the processing corresponding to the switch-on is started. A switch timer is used to measure a predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state. As shown in FIG. 19, the switch timers are provided by the number N of the detection signals (excluding the detection signal of the clear switch 921). In this embodiment, N = 12. In the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (the order from the top to the bottom shown in FIG. 12).

FIG. 20 is a flowchart showing a processing example of the switch processing in step S21 in the game control processing. The switch process is first executed in the game control process as shown in FIG. In the switch processing, the CPU 56 first inputs data input to the input port 0 (step S101). Then
"8" is set as the number of processes (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, a switch check processing subroutine is called (step S104).

FIG. 21 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets the port input data, in this case, the input data from the input port 0 as a “comparison value” (step S121). Also, clear data (00) is set (step S1).
22). Then, the switch timer indicated by the pointer (the address of the switch timer is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S123).
124). The data of the input port 0 is set as the comparison value. In this case, the detection signal of the winning opening switch 33a is pushed out by the carry flag.

If the value of the carry flag is "1" (step S125), that is, if the detection signal of the winning opening switch 33a is on, the value of the switch timer is incremented by 1 (step S127). If the value after the addition is not 0, the added value is returned to the switch timer (step S128,
S129). When the value after the addition becomes 0, the added value is not returned to the switch timer. That is, if the value of the switch timer has already reached the maximum value (255), the value is not increased further.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 33a is in an OFF state, clear data is set in the switch timer (step S126). That is, if the switch is off, the value of the switch timer returns to zero.

Thereafter, the CPU 56 increments the pointer (address of the switch timer) by 1 (step S130) and decrements the number of processes by 1 (step S13).
1). If the number of processes is not 0, step S122
Return to Then, the processing of steps S122 to S132 is repeated.

The processes of steps S122 to S132 are repeated for the number of processes, that is, eight times. In the meantime, the detection signals of the switches input to the 8 bits of the input port 0 are sequentially turned on or off. A check process is performed, and if it is in the ON state, the value of the corresponding switch timer is incremented by one.

The CPU 56 executes the step S of the switch process.
At 105, the data input to the input port 1 is input. Next, "4" is set as the number of processes (step S106), and the address of the switch timer for the winning ball count switch 301A is set in the pointer (step S107). Then, a switch check processing subroutine is called (step S108).

In the switch check processing subroutine,
Since the processing described above is performed, steps S122 to S
The process of step 132 is repeated for the number of processes, that is, four times. During that time, the detection signal of the switch input to the 4 bits of the input port 1 is sequentially checked to determine whether it is on or off, If it is in the ON state, the value of the corresponding switch timer is increased by one.

In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

FIGS. 22 to 24 are flowcharts showing an example of the prize ball processing in step S32 in the game control processing. In this embodiment, in the prize ball processing, prize port switches 33a, 24a, 29a,
30a, count switch 23 and starting port switch 1
It is determined whether or not 4a has been reliably turned on, and when turned on, control is performed such that a payout control command indicating the number of winning balls is transmitted to the payout control board 37, and the full tank switch 48 and the ball out switch 187 are operated. It is determined whether or not the switch is reliably turned on, and if turned on, processing such as control is performed so that a predetermined payout control command is transmitted to the payout control board 37.

In the prize ball processing, the CPU 56 sets “1” as an offset of the input determination value table (step S150), and sets “9” as an offset of the address of the switch timer (step S151). The offset “1” in the input determination value table (see FIG. 26) is
This means that the second data “50” in the input judgment value table is used. Each switch timer is shown in FIG.
Since the input ports are arranged in the same order as the bit order of the input ports shown in (1), the offset “9” of the address of the switch timer means that the switch timer corresponding to the full switch 48 is designated. Then, the switch-on check routine is called (step S152).

The input determination value table is a table in which a determination value for determining how many consecutive ONs are detected for each switch to determine that the switch is ON is set.
This is the M area. FIG. 26 shows a configuration example of the input determination value table. As shown in FIG. 26, in the input determination value table, “2”, “50”, “250”, “30”,
Determination values of “250” and “1” are set. Also,
In the switch-on check routine, the judgment value set at the address determined by the start address of the input judgment value table and the offset value is compared with the value of the switch timer determined by the start address of the switch timer and the offset value. If so, for example, a switch-on flag is set.

One example of the switch-on check routine is shown in FIG. In the switch-on check routine, if the value of the switch timer corresponding to the full tank switch 48 matches the full tank switch-on determination value "50", the switch-on flag is set (step S153). (Step S
154). Although not explicitly shown in FIG. 22, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

The CPU 56 sets “2” as the offset of the input judgment value table (step S15).
6), “0A (H)” is set as the offset of the address of the switch timer (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 12, the offset “0A (H)” of the address of the switch timer is designated by the switch timer corresponding to the ball out switch 187. Means to be done. Then, the switch-on check routine is called (step S158).

In the switch-on check routine,
If the value of the switch timer corresponding to the out-of-ball switch 187 matches the out-of-ball switch-on determination value "250", the switch-on flag is set (step S1).
59), a ball out flag is set (step S16)
0). Although not explicitly shown in FIG. 22, a switch-off timer corresponding to the out-of-ball switch 187 is prepared, and when its value reaches 50, the out-of-ball flag is reset.

Then, the CPU 56 checks whether or not the payout is stopped (step S201). The dispensing stop state is a state after a dispensing stop state designation command, which is a dispensing control command for instructing the dispensing control board 37 to stop dispensing, is sent out. Is a state in which the payout stop flag is set. If it is not the payout stop state, it is checked whether the above-mentioned ball out-of-ball state flag or the full tank flag is turned on (step S202).

When either of them changes to the ON state,
A payout stop flag is set (step S20).
3) Set the command transmission table for the payout stop state designation command (step S204), and call the command setting process (step S205). In step S203, processing is executed to store data (a set payout stop flag) indicating that the payout control board 37 has been instructed to prohibit payout. In step S204, the head address of the command transmission table (ROM) storing the payout control command of the payout stop state designation command is set as the address of the command transmission table. The command transmission table relating to the payout stop state designation command includes I
NT data, data of the first byte of the payout control command,
The second byte of the payout control command is set. In step S202, when one of the flags is already in the ON state and the other flag is in the ON state, the processing of steps S203 to S205 is not performed.

If the payout is stopped, it is checked whether both the out-of-ball state flag and the full tank flag have been turned off (step S206). When both are turned off, the payout stop flag is reset (step S207), and a command transmission table relating to the payable state designation command is set (step S207).
208), a command set process is called (step S209). In step S207, the payout control board 37
A process of storing data (reset payout stop flag) to indicate that the side has been instructed to permit payout is executed. In step S208,
The head address of the command transmission table (ROM) storing the payout control command of the payable state designation command is set as the address of the command transmission table. In the command transmission table relating to the payout possible state designation command, INT data to be described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set.

Further, the CPU 56 sets "0" as an offset of the input judgment value table (step S22).
1), “0” is set as the offset of the address of the switch timer (step S222). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Since the switch timers are arranged in the same order as the bit order of the input port shown in FIG. 12, the switch timer address offset "0" designates the switch timer corresponding to the winning opening switch 33a. Means Also, “4” is set as the number of repetitions (step S223).
Then, the switch-on check routine is called (step S224).

In the switch-on check routine,
The CPU 56 sets the start address of the input determination value table (see FIG. 26) (Step S281). And
An offset is added to the address (step S28)
2) The switch-on determination value is loaded from the address after the addition (step S283).

Next, the CPU 56 sets the start address of the switch timer (step S284), adds an offset to the address (step S285), and loads the value of the switch timer from the address after the addition (step S286). Since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 12, the value of the switch timer corresponding to the switch is loaded.

Then, the CPU 56 compares the value of the loaded switch timer with the switch-on judgment value (step S287). If they match, a switch-on flag is set (step 128).

In this case, in the switch-on check routine, if the value of the switch timer corresponding to the winning opening switch 33a matches the switch-on determination value "2", the switch-on flag is set (step S2).
25). The switch check-on routine is executed for the number of repetitions initially set (Steps S228 and S229) while the offset of the address of the switch timer is updated (Step S230).
After all, the winning opening switches 33a, 24a, 29a, 30a
, The value of the corresponding switch timer is compared with the switch-on determination value “2”.

When the switch-on flag is set, "10" as the number of award balls to be paid out is set in the ring buffer (step S226). Then, 10 is added to the value stored in the total prize ball storage buffer (step S22).
7). When data is written to the ring buffer, the write pointer is incremented. When data is written to the last area of the ring buffer, the write pointer is updated to point to the first area of the ring buffer.

The total prize ball number storage buffer is a buffer for storing the cumulative value of the prize ball number instructed to the payout control means (however, it is subtracted when the payout is made).
It is formed in the backup RAM. In this embodiment, when data is written to the ring buffer, addition processing is performed on the stored value of the total prize balls storage buffer, but a payout control command indicating the number of prize balls to be paid out is output to the output port. At the time of output, the process of adding the number of prize balls corresponding to the payout control command to be output to the value stored in the total prize ball storage buffer may be performed.

Next, the CPU 56 sets "0" as an offset of the input judgment value table (step S23).
1), "4" is set as the offset of the address of the switch timer (step S232). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Since the switch timers are arranged in the same order as the bit order of the input port shown in FIG. 12, the switch timer address offset “4” specifies the switch timer corresponding to the start-up switch 14a. Means Then, the switch-on check routine is called (step S).
233).

In the switch-on check routine,
If the value of the switch timer corresponding to the starting port switch 14a matches the switch-on determination value "2", the switch-on flag is set (step S234). When the switch-on flag is set, "6" is set as the number of award balls to be paid out in the ring buffer (step S235). The value stored in the total prize balls storage buffer is 6
Is added (step S236).

Next, the CPU 56 sets "0" as an offset of the input judgment value table (step S24).
1), “5” is set as the offset of the address of the switch timer (step S242). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 12, the offset “5” of the address of the switch timer indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, the switch-on check routine is called (step S).
243).

In the switch-on check routine,
If the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value “2”, the switch-on flag is set (step S244). When the switch-on flag is set, "15" as the number of award balls to be paid out is set in the ring buffer (step S245). Also, 15 is added to the value stored in the total prize ball storage buffer (step S246).

If data exists in the ring buffer (step S247), the contents of the ring buffer indicated by the read pointer are set in the transmission buffer (step S248), and the value of the read pointer is updated (step S248). It is updated to point to the next area) (step S249), a command transmission table for the number of winning balls is set (step S250), and a command set process is called (step S251). The operation of the command set processing will be described later in detail.

In step S250, the head address of the command transmission table (ROM) in which the payout control command relating to the number of winning balls is stored is set as the address of the command transmission table. The command transmission table relating to the number of winning balls includes INT data (01
(H)), the first byte data (F
0 (H)) and the second byte of the payout control command. However, “80 (H)” is set as the data of the second byte.

As described above, when trying to output a payout control command instructing the number of winning balls from the game control means to the payout control board 37, the address setting of the command transmission table relating to the number of winning balls and the setting of the transmission buffer are performed. Is performed. Then, the payout control command is transmitted to the payout control board 37 based on the command transmission table relating to the number of winning balls and the setting contents of the transmission buffer by the command set processing. In step S247, it is possible to confirm whether or not there is data based on the difference between the write pointer and the read pointer. It may be confirmed whether or not.

Then, the content of the total prize balls storage buffer is 0.
If not, that is, if there is still a prize ball remaining, C
The PU 56 turns on the award ball payout flag (step S
252, S253).

When the award ball paying flag is on (step S254), the CPU 56 monitors the number of award balls actually paid out from the ball payout device 97 and stores the total number of award ball storage buffers. A winning ball number subtraction process of subtracting the value is performed (step S255). When the award ball paying flag changes from on to off, the lamp control board 3
5, a lamp control command instructing lighting of the prize ball lamp 51 is transmitted.

As described above, in this embodiment, when the shortage of the game balls to be paid out is detected (when the ball runs out) and when the game balls should not be paid out with the lower plate full. The payout stop state designation command, which is the same command, is notified from the game control means to the payout control means (see FIG. 28). That is, even if the conditions for stopping the payout are different, a common command is transmitted from the game control means to the payout control means. In other words, even if any of the plurality of payout stop conditions different from the completion of payout of the game medium is satisfied, the common control command instructs the payout control means that the payout is not in a state where payout is possible. You. Then, the payout control means stops the payout of the game balls when receiving the payout stop state designation command.

When any of the payout stop conditions is satisfied, a common control command can be used to instruct the payout control means that the payout is not possible, thereby reducing the load of information transmission from the game control means to the payout control means. Is done. As a result, there is an advantage that the program capacity in the game control means is reduced and the program capacity that can be used for game control is increased.

When the payout control means receives the payout stop state designation command, it stops both the payout of the ball as the prize ball and the payout of the ball as the ball lending. Also, when the payout possible state designation command is received, both the ball payout as a prize ball and the ball payout as a ball lending are made possible. However, the payout control command for stopping or resuming the ball payout as a prize ball and the payout control command for stopping or resuming the ball payout as a ball rental from the game control means to the payout control means are different control commands. May be transmitted.

Further, in this embodiment, even if the payout is stopped (steps S201, S206), step S201
Steps 221 to S251 are performed. That is, the game control means can transmit a payout control command for instructing the number of winning balls even in the payout stop state.
In other words, a command for instructing the number of winning balls is transmitted to the payout control means even in the payout stop state, and when the payout stop state is released, the payout ball payout can be started earlier. Further, the game control means does not require a large storage area for storing the number of winning balls based on winnings in the payout stop state.

Next, a method of transmitting a control command from the game control means to each electric component control means will be described. When an attempt is made to output a control command from the game control means to another electric component control board (sub board), the start address of a command transmission table is set. FIG.
FIG. 7A is an explanatory diagram illustrating a configuration example of a command transmission table. One command transmission table is composed of three bytes, and INT data is set in the first byte.
In the command data 1 of the second byte, MODE data of the first byte of the control command is set. Then, in the command data 2 of the third byte, EXT data of the second byte of the control command is set.

Although the EXT data itself may be set in the command data 2 area, the command data 2
May be set to data for specifying an address of a table in which EXT data is stored. For example, if bit 7 (work area reference bit) of command data 2 is 0, EX
Indicates that the T data itself is set. Also,
If bit 7 (work area reference bit) of the command data 2 is 1, data stored in an area indicated by an address in a predetermined address table (command extension data address table) is used as EXT data. Show. For example, in the case of a payout control command,
The work area reference bit is 1, and the contents of the transmission buffer are used as EXT data.

FIG. 27B is an explanatory diagram showing an example of the configuration of the INT data. Bit 0 in the INT data is
Indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that a payout control command should be sent. Therefore, the CPU 56
Sets "01 (H)" in the INT data in, for example, the prize ball processing (step S31 of the main processing). Bit 1 in the INT data indicates whether a display control command should be sent to the symbol display control board 80 or not. If bit 1 is "1", it indicates that a display control command should be sent. Therefore, the CPU 56 performs, for example, a special symbol command control process (step S27 of the main process).
, "02 (H)" is set in the INT data.

Bits 2 and 3 of the INT data are bits indicating whether or not a lamp control command and a sound control command are to be transmitted, respectively. The INT data, the command data 1 and the command data 2 are set in the command transmission table pointed to by the pointer in the symbol processing or the like. When these commands are transmitted, the corresponding bit of the INT data is set to “1”, and MOD is added to command data 1 and command data 2.
E data and EXT data are set.

In this embodiment, a ring buffer and a transmission buffer are prepared for the payout control command as shown in FIG. Then, in the prize ball processing, when the prize ball payout condition is satisfied, the number of prize balls according to the satisfied condition is sequentially set in the ring buffer. When sending out a payout control command relating to the number of winning balls,
One piece of data is transferred from the ring buffer to the transmission buffer. In the example shown in FIG. 27C, data corresponding to 12 payout control commands can be stored in the ring buffer. That is, there are 12 buffers. The number of buffers in the ring buffer may be a number corresponding to the number of winning ports for generating prize balls. This is because even in the case of simultaneous winning, data of a payout control command based on each winning can be stored.

FIG. 28 is a flowchart showing a processing example of the command set processing. The command set process is a process including a command output process and an INT signal output process. In the command setting process, the CPU 56 first saves the address of the command transmission table in a stack or the like (Step S331). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). Argument 1 is input information for a command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S333). Therefore, the address indicating the command transmission table matches the address of the command data 1.

Next, the CPU 56 sets the command data 1
Is read and set as argument 2 (step S334).
The argument 2 also becomes input information for a command transmission process described later. Then, a command transmission processing routine is called (step S335).

FIG. 29 is a flowchart showing a command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set in the argument 1, ie, the INT data, in the work area determined as the comparison value (step S351).
Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S352). Then, the address of port 1 is set to the IO address (step S353). In this embodiment, port 1
Are the addresses of output ports for outputting payout control command data, and the addresses of ports 2 to 4 are the addresses of output ports for outputting display control commands, lamp control command data, and sound control command data. is there.

Next, the CPU 56 shifts the comparison value one bit to the right (step S354). It is determined whether or not the carry bit has become 1 as a result of the shift processing (step S355). The fact that the carry bit has become 1 means that the rightmost bit in the INT data is “1”.
It means that it was. In this embodiment, four shift processes are performed. For example, when it is specified that a display control command is to be transmitted, the carry bit becomes 1 in the second shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (ie, MODE data) is output to the address set as the IO address (step S3
56). When the second shift processing is performed, the address of the port 2 is set in the IO address. At that time, the MODE data of the display control command is output to the port 2.

Next, the CPU 56 sets the IO address to 1
While adding (step S357), 1 is subtracted from the number of processes (step S358). If the port 2 is indicated before the addition, the IO address is set to the address of the port 3 by the addition processing for the IO address. Port 3 is a port for outputting a lamp control command. Then, the CPU 56 checks the value of the number of processes (step S359), and returns to step S354 if the value is not 0. The shift process is performed again in step S354.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" according to the value of bit 1. Therefore,
A check is made to determine whether the transmission of the display control command is specified. Similarly, in the third and fourth shift processes, it is checked whether or not transmission of the lamp control command and the sound control command is specified. As described above, when each shift process is performed, a command (payout control command, payout control command,
IO addresses corresponding to display control commands, lamp control commands, and sound control commands are set.

Therefore, when the carry flag becomes "1", the corresponding output port (port 1 to port 4)
Is sent to the control command. That is, one common module can perform a command transmission process (output process) to each electric component control unit.

As described above, it is determined which control control unit should output the control command by only the shift processing. Therefore, it is determined which control control unit should output the control command. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 storing the INT data before the start of the shift processing (step S360), and outputs the read data to the port 0 (step S361). In this embodiment,
The port 0 address is a port for outputting an INT signal for each control signal.
To 4 are a payout control INT signal and a display control IN, respectively.
A port for outputting a T signal, a lamp control INT signal, and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 becomes “1”. Has become. Therefore,
The INT signal corresponding to the control command (dispensing control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 is turned off (low level).

Next, the CPU 56 sets a predetermined value in the weight counter (step S362), and decrements by one until the value becomes 0 (steps S363 and S36).
4). When the value of the wait counter becomes 0, clear data (00) is set (step S365), and the data is output to port 0 (step S366). Therefore, the INT signal is turned off. Then, a predetermined value is set in the weight counter (step S362), and the value is decremented by 1 until the value becomes 0 (steps S368 and S368).
369).

As described above, the MODE data of the first byte of the control command is transmitted. Therefore, CPU5
No. 6 adds 1 to the value indicating the command transmission table in step S336 shown in FIG. Therefore, the area of the command data 2 in the third byte is specified. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S337). Further, it is determined whether the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S338). If it is not 0, the start address of the command extension data address table is set in the pointer (step S339), and the address is calculated by adding the value of bit 6 to bit 0 of the command data 2 to the pointer (step S340). Then, the data of the area indicated by the address is loaded into the argument 2 (step S341).

In the command extension data address table, EXT data that can be transmitted to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1” by the above processing, the EXT data in the command extension data address table corresponding to the content of the command data 2 is loaded into the argument 2 and the work area reference bit is set. If the value is “0”, the content of the command data 2 is loaded as it is into the argument 2. Even when EXT data is read from the command extension data address table, bit 7 of that data is “0”.

Next, the CPU 56 calls a command transmission processing routine (step S342). Therefore, M
EXT at the same timing as when transmitting ODE data
Data is sent. Thereafter, the CPU 56 returns the address of the command transmission table (step S34).
3) Update the value of the read pointer pointing to the command transmission table (step S344). If there is a command to be further transmitted (step S345), the process returns to step S331.

As described above, the 2-byte control command (dispensing control command, display control command, lamp control command, sound control command) is transmitted to the corresponding electric component control means. When detecting the level change of the INT signal, the electric component control means starts the control command fetching process, but in any of the electric component control means, a new signal from the game control means is received before the fetching process is completed. It is not output to the signal line. That is, in each electric component control means such as the display control means,
Reliable command reception processing is performed. The polarity of the INT signal may be reversed from that shown in FIG.

As described above, the command set process is a common module used when transmitting any of the display control command, the lamp control command, the sound control command, and the payout control command. Therefore,
The program capacity of the game control program executed by the game control means can be reduced.

Further, since the forms of the display control command, the lamp control command, the sound control command, and the payout control command are common, the processing for creating each control command can be easily modularized. In this embodiment, the command transmission table (see FIG. 27A) for each control command is set in the ROM in advance. However, the command transmission table may be created when each control command is transmitted. For example, after creating a command transmission table as shown in FIG. 27A in the RAM, the command set processing shown in FIG. 28 may be called.

Display control command, lamp control command,
Since the command transmission table for any of the sound control command and the payout control command is composed of the INT data, the command data 1 and the command data 1, any of the bits is set to “1” as a common module for creating the control command. If the common module is called using the INT data of "" and the data to be set in the command data 1 and 2 as input data, a command transmission table as shown in FIG. 27 is created for any control command. As such, a common module for creating control commands can be configured.

FIG. 30 is a flowchart showing step S2 shown in FIG.
It is a flowchart which shows an example of 55 winning ball number subtraction processing. In the winning ball number subtraction process, the CPU 56 first loads a value stored in the total winning ball number storage buffer (step S381). Then, it is determined whether or not the stored value is 0 (step S382). If it is 0, the process ends.

If it is not 0, the switch timer for the prize ball count switch is loaded (step S383), and the loaded value is compared with the ON determination value (in this case, "2") (step S384). If they match (step S38)
5) Assuming that the prize ball count switch 301A has certainly turned on, that is, one game ball has surely
7, the value stored in the total prize balls storage buffer is decremented by one (step S386).

When the value stored in the total prize ball count storage buffer becomes 0 (step S387), the flag for paying out prize balls is cleared (step S388), and in order to notify that there is no remaining prize ball count, After setting command data indicating turning off of the prize ball lamp 51 in the command transmission table for the lamp control command (step S389), a lamp control command transmission process is executed (step S390).

FIG. 31 is a flowchart showing a prize ball information signal output process. The prize ball information signal output process is shown in FIG.
Is a part of the information output process (step S30) in the game control process shown in FIG. In the prize ball information signal output processing, the CPU 56 loads a switch timer for a prize ball count switch (step S401), and compares the load value with an ON determination value (in this case, “2”) (step S402). If they match (step S403), it is determined that the prize ball count switch 301A has definitely turned on, that is, that one game ball has been correctly paid out from the ball payout device 97, and the value of the prize ball number information counter is incremented by one. (Step S404).

Then, the value of the prize ball number information counter is 10
If the value has reached the above value (step S405), the value of the winning ball information output counter is incremented by one (step S406), and the value of the winning ball number information counter is decreased by 10 (step S407). Further, an output process of the prize ball information signal is performed (step S408). The award ball information signal is output from the output port 5 (see FIG. 11), and is further output from the award ball terminal of the terminal board 160 to the outside of the gaming machine.

FIG. 32 is a timing chart showing an example of the output timing of the prize ball information signal externally output from the main board 31 via the terminal board 160. In this example, FIG.
By the process shown in FIG. 1, every time the number of awarded ball payouts reaches 10, the awarded ball information signal is set to a low level for 0.1 second, and subsequently to a high level for 0.1 second. That is,
For every 10 winning balls, "ON" is output for 0.1 second, and subsequently, "OFF" is output for 0.1 second. Note that the period of 0.1 second is set in the process of step S408.

Next, payout control means (payout control CPU 371 and ROM, R
The operation of peripheral circuits such as AM will be described. FIG. 33 is an explanatory diagram showing the assignment of output ports on the payout control board 37 in this embodiment. As shown in FIG. 33, the output port C (address 00H) is an output port for driving signals output to the payout motor 289. The output port D (address 01H) is an output port for a display control signal output to the error display LED 374, which is a 7-segment LED. The output port E (address 02H) is connected to a drive signal output to the distribution solenoid 310, an EXS signal to the card unit 50, and P
This is an output port for outputting an RDY signal.

FIG. 34 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 34, the input port A (address 06H) is an input port for receiving an 8-bit payout control signal of the payout control command transmitted from the main board 31. The detection signals of the prize ball count switch 301A and the ball lending count switch 301B are input to bits 0 to 1 of the input port B (address 07H), respectively. Bits 2 to 5 include a BRDY signal, a BRQ signal, a VL signal, and a clear switch 921 from the card unit 50.
Is input. When the payout control means does not use the clear switch 921, there is no need to input the detection signal.

FIG. 35 is a flowchart showing the main processing executed by the payout control means. In the main process, the payout control CPU 371 first makes necessary initial settings. That is, the payout control CPU 371 first sets interrupt prohibition (step S701). Next, the interrupt mode is set to the interrupt mode 2 (step S702), and a stack pointer designated address is set to the stack pointer (step S703). The payout control CPU 37
1 initializes a built-in device register (step S704), and initializes CTC and PIO (step S704).
After performing step 705), the RAM is set in an accessible state (step S706).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the internal device register setting process in step S704 and the process in step S705, a register setting for setting a channel to be used to the timer mode, a register setting for permitting interrupt generation, and a register for setting an interrupt vector The settings are made. Then, the interruption by the channel is used as a timer interruption. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set for the channel set in the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt processing. Specifically, the start address of the timer interrupt processing is specified by the value set in the I register and the interrupt vector.
In the timer interrupt process, a payout control process is executed.

Another channel of the built-in CTC (channel 2 in this embodiment) is used as an interrupt generation channel for receiving a payout control command from the game control means. Is used in the counter mode. Therefore, in the setting processing of the internal device register in step S704 and the processing in step S705, the register setting for setting the channel to be used to the counter mode, the register setting for permitting the interrupt generation, and the interrupt vector setting are performed. Is set.

The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the start address of the command reception interrupt process described later.
Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

In the present embodiment, the payout control CPU 3
At 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on the count-up of C can be used. Further, it is possible to set an interrupt processing start address according to the interrupt vector transmitted by the CTC.

The interrupt based on the count up of the channel 2 (CH2) of the CTC is an interrupt generated when the value of the timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as a specific register
The initial value “1” is set in LK / TRG2. further,
The count value of the timer counter register CLK / TRG2 as a specific register is decremented by -1 at the rise or fall of the signal input to the CLK / TRG2 terminal. You can make a selection. In this embodiment, at the rising edge of the signal input to the CLK / TRG2 terminal, the timer / counter register CLK / TRG
A setting is made so that the count value of 2 is decremented by one.

The interrupt based on the count-up of channel 3 (CH3) of CTC is an interrupt generated when the internal clock (system clock) of the CPU is counted down and the register value becomes "0". 2m to do
Used as s timer interrupt. Specifically, the CPU 3
A clock obtained by dividing the operation clock of 71 is supplied to the CTC, and the value of the register is subtracted by the input of the clock. When the value of the register becomes 0, a timer interrupt occurs.
For example, the register value of CH3 is 1 / system clock.
It is subtracted in 256 cycles. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, a value corresponding to 2 ms is set as an initial value in the register of CH3.

An interrupt based on the count-up of CH2 of the CTC has a higher priority than an interrupt based on the count-up of CH3. Therefore, when the count-up occurs at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process has priority.

Next, the payout control CPU 371 checks the state of the output signal of the clear switch 921 inputted via the input port B (see FIG. 34) only once (step S707). In the case where the ON is detected in the confirmation, the payout control CPU 371 executes a normal initialization process (steps S711 to S713). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 372, the ON state of the clear switch signal is at a high level. Further, the payout control means does not have to perform the determination in step S707.

In the same manner as the CPU 56 of the main board 31, the payout control CPU 371 also determines that the switch detection signal is on, for example, when the on state is at least two.
ms (when the detection signal is turned on immediately before the detection in the first processing of the processing started every 2 ms), the switch is not considered to be turned on unless it is continued. However, when the clear switch 921 is detected to be turned on, one switch is performed. ON / OFF is determined by the ON determination. That is, the initialization request detection determination period for the payout control CPU 371 to determine whether the clear switch 921 as the initialization operation means is in the predetermined operation state is a prize ball count switch or the like as the game medium detection means. Is different from the game medium detection determination period for determining that the game medium has been detected.

If the clear switch 921 is not on, the payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S708). For example, similarly to the processing of the CPU 56 of the main board 31, it is confirmed whether or not backup data exists by determining whether or not a backup flag that is set when power supply to the gaming machine is stopped is set. If the backup flag is set, it is determined that there is backup data.

After confirming that there is a backup, the payout control CPU 371 checks the data in the backup RAM area (parity check in this example). When the power supply is restored after the power supply is stopped due to an unexpected power failure or the like, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, the internal state cannot be returned to the state at the time of stopping the power supply. Therefore, an initialization process executed at the time of power-on, not at the time of recovery from a shortage of power failure or the like, is executed.

If the check result is normal (step S
709), the payout control CPU 371 performs a payout state restoring process for returning the internal state to the state at the time of stopping power supply (step S710). Then, the process returns to the address indicated by the PC (program counter) stored in the backup RAM area.

In the initialization processing, the payout control CPU 371
Performs RAM clear processing first (step S71).
1). A CTC provided in the payout control CPU 371 so that a timer interrupt is periodically performed every 2 ms.
Are set (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S701 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S713).

In this embodiment, the payout control CPU 3
The built-in CTC 71 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2
ms. And when a timer interrupt occurs,
As shown in FIG. 36, a timer interrupt flag indicating that a timer interrupt has occurred is set (step S772).
Then, when it is detected in the main processing that the timer interrupt flag is set (step S714), the timer interrupt flag is reset (step S714).
751), payout control processing (steps S752 to S76)
0) is executed.

In the timer interrupt, as shown in FIG. 36, the interrupt is initially set to the permission state (step S77).
1). Therefore, during the timer interrupt process, the interrupt is permitted, and the payout control command receiving process based on the input of the INT signal can be executed with priority.

In the payout control process, the payout control CPU
Reference numeral 371 denotes a prize ball count switch 301A or a ball lending count switch 3 input to the input port 372b.
It is determined whether a switch such as 01B has been turned on (switch processing: step S752).

Next, the payout control CPU 371 sets the payout stop state if the payout stop state designation command has been received from the main board 31, and releases the payout stop state if the payout possible state designation command has been received. (Payout stop state setting processing: step S753). Further, it analyzes the received payout control command and executes a process according to the analysis result (command analysis execution process: step S754). Further, a prepaid card unit control process is performed (step S755).

Next, the payout control CPU 371 performs control to pay out the lent ball in response to the ball lending request (step S756). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Further, the payout control CPU 371 performs prize ball control processing for paying out the prize balls of the number stored in the total number storage (step S757). At this time, the payout control CPU 371 sets the ball distribution member 311 to the winning ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism of the ball payout device 97 via the relay board 72c and the relay board 72, and a payout motor control process for rotating the payout motor 289 by a predetermined number of revolutions is performed (step S758). . In this embodiment, a stepping motor is used as the payout motor 289.

Next, error detection processing is performed, and a predetermined display is made on the error display LED 374 according to the result (error processing: step S759). In addition, processing such as outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S760).

The output port C shown in FIG. 33 is connected to the payout motor control processing (step S75) in the payout control processing.
8) is accessed. The output port D is accessed in an error process (step S759) in the payout control process. The output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

FIG. 37 is an explanatory diagram showing an example of use of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are respectively formed.
The total number storage stores the total number of awarded ball payouts instructed from the main board 31 side. The rental ball number storage stores the number of unpaid ball rentals. In addition,
R storing data used in the payout control process
All the AM areas may be backed up by power.

When the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means in, for example, the prize ball control process (step S757), the payout control CPU 371 stores the specified number in the total number storage. Increase. In the ball lending control process (step S756), the content is increased in the lending ball number storage by one unit (for example, 25) each time a ball lending request signal is received from the card unit 50. Further, the payout control CPU 3
71 is a prize ball count switch 3 in the prize ball control processing.
When 01A detects one prize ball payout, the value of the total number storage is reduced by one, and when the ball lending count switch 301B detects one lending ball payment in the ball lending control processing, the value of the lending ball number storage is reduced by one.

Therefore, the number of unpaid prize balls and the number of loaned balls are equal to the number of backup RAs that can hold the contents for a predetermined period.
It will be stored in the M area. Therefore, even if an unexpected power supply stop such as a power failure occurs, if the power supply is restored within a predetermined period, the prize ball processing and the ball lending processing can be restarted based on the contents stored in the backup RAM area. That is, even if the power supply to the gaming machine is stopped, if the power supply is resumed, the payout is performed based on the number of unpaid prize balls and the number of loaned balls at the time of the power supply stop, and is given to the player. The disadvantage can be reduced.

FIG. 38 is an explanatory diagram showing an example of the configuration of a receiving buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type receiving buffer capable of storing six payout control commands having a 2-byte configuration is used. Accordingly, the reception buffer is configured by a 12-byte area of the reception command buffers 1 to 12. Then, a command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

As described above, the payout control board 37 is provided with the receiving buffer area as a storage area capable of storing a plurality of received payout control commands simultaneously.
When the payout control command is stored in the reception command buffer in the reception buffer area, the command reception number counter corresponding to the storage address is updated. When the payout control command is stored in the last receive command buffer in the receive buffer area, the value of the command reception number counter is returned to 0. That is, the storage address is set to indicate the head address of the reception buffer area.

Note that the payout control CPU 371 reads out the payout control command in the reception buffer area based on the read address in the reception buffer area. And 1
When the payout control commands are read, the read address is updated. That is, it is updated to point to the next received command buffer. For example, when it is detected that the payout control command is stored in the reception buffer area in the payout stop state setting process and the command analysis execution process described later, the control process indicated by the readout payout control command is started. I do. Therefore, the payout control means reads out the payout control command from the specific receive command buffer designated by the read address in accordance with the order of reception, and starts the control processing according to the readout payout control command.

In this embodiment, the payout control command received from main board 31 is stored in the receive buffer area as it is, but only a part of the data of the received payout control command is stored in the receive buffer area. You may do so. For example, only the data indicating the number of payout control commands indicating the number of winning balls may be stored in the reception buffer area.

FIG. 39 is a flowchart showing a payout control command receiving process by the interrupt process. An INT signal for payout control from the main board 31 is supplied to a payout control CPU 371.
Are input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 rises, the payout control CPU 371 is interrupted, and the processing of receiving the payout control command shown in FIG. 39 is started. The payout control CP
U371 is a CPU having a structure in which, when an interrupt occurs, a maskable interrupt does not further occur unless the interrupt is permitted by software.

In this embodiment, CLK / TR
The initialization was performed such that the value of the timer counter register CLK / TRG2 is decremented by one when the input of the G2 terminal rises. That is, the initialization was performed such that an interrupt occurs at the rise of the INT signal. When the input of the CLK / TRG2 terminal falls, the timer counter register CLK
Initial setting may be performed such that the value of / TRG2 is set to -1. In other words, initialization may be performed such that an interrupt occurs at the falling edge of the INT signal.

That is, if an interrupt is generated at the level change timing (edge) of a pulse (rectangular wave) INT signal as a capture signal, the edge may be a rising edge or a falling edge. There may be. In any case, the configuration is such that an interrupt occurs at the level change timing (edge) of the pulse (rectangular wave) INT signal as the capture signal. By doing so, it becomes possible to receive a command as soon as possible when the command fetch is instructed. In addition, period A (FIG. 1)
7)), the output of the INT signal is on standby until the control signals CD0 to CD7 are output.
The output state of the command data on the line is stable. Therefore, the payout control command is favorably received by the payout control means.

In the process of receiving the payout control command, the payout control CPU 371 first saves each register in the stack (step S850). Next, the input port 3 assigned to the input of the payout control command data
72a (see FIG. 7) (step S)
851). Then, it is confirmed whether or not this is the first byte of the payout control command having the 2-byte structure (step S8).
52). Whether it is the first byte or not is confirmed by whether or not the first bit of the received command is “1”. The leading bit should be "1" in the MODE byte (the first byte) of the payout control command having the 2-byte structure (see FIG. 16). Therefore, if the first bit is “1”, the payout control CPU 371 determines that a valid first byte has been received, and stores the received command in the reception command buffer indicated by the command reception number counter in the reception buffer area (step). S85
3).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed based on whether or not valid data is set in the reception buffer (reception command buffer).

If the first byte has already been received,
It is checked whether the first bit of the received 1 byte is “0”. And if the first bit is “0”,
Assuming that the valid second byte has been received, the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The first bit should be “0” in the EXT byte (second byte) of the payout control command having the 2-byte configuration (see FIG. 16). If it is determined in step S854 that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not “0”. If "N" is determined in step S854, the process of step S856 is not performed, and the next received command is stored in the buffer area where the command received this time should have been stored. You.

In step S855, when the command data of the second byte is stored, 2 is added to the command reception number counter (step S856). Then, it is checked whether or not the command reception counter is 12 or more (step S857), and if it is 12, the command reception number counter is cleared (step S858). After that, the saved register is restored (step S859),
Finally, interrupt permission is set (step S859).

During the command reception interruption processing, interruption is prohibited. As described above, the interrupt is permitted during the 2 ms timer interrupt process. Therefore, if a command reception interrupt occurs during the 2 ms timer interrupt, the command reception interrupt process is executed with priority. You. Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since no other interrupt processing is executed during the command reception processing, the maximum time required for the command reception processing is determined. It is difficult to estimate the longest time required for the command receiving process if the configuration is such that another interrupt process can be executed during the command receiving process. Since the maximum time required for the command receiving process is determined, a period C in the command transmitting process of the game control means (see FIG. 17).
Can be accurately determined.

The payout control command has a 2-byte structure, and includes a first byte (MODE) and a second byte (EX).
T) is configured to be immediately distinguishable on the receiving side.
In other words, the receiving side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received.

In this embodiment, in the command reception interrupt processing, control for storing the received command in the reception buffer is performed. However, a payment stop state setting processing (see FIG. 41) described later and a command analysis execution processing (See FIG. 42)
May be executed in the command reception interrupt processing. As described above, when the command determination processing for determining the command in the reception buffer is also executed in the command reception interrupt processing, the determination of the command is also quickly performed.

FIG. 40 is a flowchart showing an example of the switch processing in step S752. In the switch processing, the payout control CPU 371 checks whether or not the winning ball count switch 301A indicates the ON state (step S752a). If it indicates the ON state, the payout control CPU 371 increments the winning ball count switch ON counter by one (step S752b). The prize ball count switch on counter includes the prize ball count switch 30.
This is a counter for counting the number of times the 1A ON state is detected.

Then, the value of the winning ball count switch on counter is checked, and if the value is 250 (step S752c), the winning ball clogging flag is set (step S752d). That is, when the ON state of the prize ball count switch 301A continues for a long time, the prize ball clogging flag is set.

When the value of the prize ball count switch on counter has reached 2 (step S752e), it is determined that the prize ball count switch 301A has been turned on without fail.
The award ball count switch on flag is set (step S752f).

If it is determined in step S752a that the prize ball count switch 301A is not on, the payout control CPU 371 resets the prize ball count switch on flag (step S752).
h), the award ball count switch on counter is cleared (step S752i). Then, it is determined whether or not the ball lending count switch 301B indicates the ON state (step S752j). If it indicates the ON state, the payout control CPU 371 increments the ball lending count switch on counter by one (step S752k). The ball lending count switch on counter is a counter for counting the number of times that the ball lending count switch 301B has been turned on.

Then, the value of the ball lending count switch on counter is checked, and if the value is 250 (step S752l), the ball lending jam flag is set (step S752m). That is, when the ball lending count switch 301B has been on for a long period of time, the lending ball clogging flag is set.

When the value of the ball lending count switch-on counter has become 2 (step S752n),
It is determined that the ball lending count switch 301B has been turned on, and the ball lending count switch on flag is set (step S752o).

If it is determined in step S752j that the ball lending count switch 301B is not on, the payout control CPU 371 resets the ball lending count switch on flag (step S75).
2p) The ball lending count switch on counter is cleared (step S752q).

FIG. 41 is a flowchart showing an example of the payout stop state setting process in step S753. In the payout stop state setting process, the payout control CPU 371
It is checked whether there is a reception command in the reception buffer (step S753a). If there is a reception command in the reception buffer, it is checked whether or not the received payout control command is a payout stop state designation command (step S).
753b). If the command is the payout stop state designation command, the payout control CPU 371 sets the payout stop state (step S753c).

If it is confirmed in step S753b that the received command is not a payout stop state designation command, it is checked whether the received payout control command is a payout possible state designation command (step S753d). If the command is a payable state designation command, the payout stop state is released (step S753e).

When setting the payout stop state,
For example, the drive of the payout motor 289 is stopped, and an internal flag (payout stop flag) indicating that the payout is stopped is set. When releasing the payout stop state, the driving of the payout motor 289 is restarted and the payout suspension flag is reset. That is, in step S753c, data indicating that the payout is prohibited (the payout suspension flag is set).
Is stored in a predetermined storage area, and in step S753e, a process of storing data (reset payout suspension flag) indicating that payment is permitted in a predetermined storage area is performed. It is running.

The payout suspension flag is stored, for example, in the backup RAM area. The payout suspension flag has, for example, a 1-byte configuration including bits D0 to D7. In this case, for example, if D0 is "1", the payout stop state may be set, and if D1 is "1", the payout stop state may be released. D2 is used, for example, to indicate a return waiting state after the payout suspension state is released. D3 to D7 are unused areas.

Here, the state of the payout suspension flag in the processing of FIG. 41 will be specifically described. Step S753c
In the process (1), the payout control CPU 371 sets the payout suspension flag D0 to “0” and sets D1 to “1”. In the process of step S753e, the payout control CPU 371 sets the payout suspension flag D0 to “1”, sets D1 to “0”, and sets D2 to “1”. When D2 is set to “1”, the payout control CPU 371 sets D2 to “0” after a lapse of a predetermined period (for example, 1 [s]). In this example, the payout suspension flag indicates that when D0 is “0” and D1 is “1”,
Indicates that the dispensing is stopped. Further, when D0 is “1” and D1 is “0”, it indicates that the payout is permitted (the payout stop state is released). Note that the payout suspension flag may have a configuration other than the 1-byte configuration, and each bit may be used in another manner (for example, by using only D0 and setting D0 to “ If it is "0", it indicates a payout stop state, and if D0 is "1", it may indicate a payout permission state.)

When the dispensing stop state is set, the dispensing motor 289 may be stopped immediately. However, instead of controlling the dispensing motor 289, the dispensing motor 289 is not required to be controlled.
May be stopped. For example, the payout of game balls may be executed in units of 25, and when the payout of one unit is completed, the payout motor 289 may be stopped, and the internal state may be set to the stoppage state. As mentioned above,
The ball out switch 187 is installed at a position where it is possible to detect the presence of about 27 to 28 game balls in the payout ball passage, so that even if the game control means of the main board 31 detects a ball out, From that point on, at least 25 payouts are possible. Therefore, no problem occurs even if the payout is stopped when the payout of one unit is completed. In addition, if the payout is stopped at one unit interval, control when payout is restarted becomes easy.

FIG. 42 is a flowchart showing an example of the command analysis execution processing in step S754. In the command analysis execution processing, the payout control CPU 371
It is determined whether or not there is a reception command in the reception buffer (step S754a). If there is a received command, it is confirmed whether or not the received payout control command is a payout control command for specifying the number of winning balls (step S7).
54b). Note that the payout control CPU 371 makes a determination in step S754b on the reception command stored at the address in the reception buffer indicated by the read pointer as the command instructing means. After the determination, the value of the read pointer is incremented by one. If the address pointed to by the read pointer exceeds the address of the receive command buffer 12 (see FIG. 38), the value of the read pointer is updated to point to the receive command buffer 1.

If the received payout control command is a payout control command for designating the number of winning balls, the number specified by the payout control command is added to the total number storage (step S754c). That is, the payout control CPU 371
Stores the number of winning balls included in the payout control command sent from the CPU 56 of the main board 31 in the backup RAM area (total number storage).

The payout control CPU 371 performs a command reception number counter subtraction and a reception command shift process in the reception buffer, if necessary. Further, the payout stop state setting process and the command analysis execution process may be configured to be repeated until the value of the read pointer matches the latest command storage position in the reception buffer. For example, if the difference between the value of the read pointer and the latest command storage position in the reception buffer is "3", there are three unprocessed received commands. , There are no unprocessed received commands. That is, the received commands stored in the reception buffer are all read out and processed in one process.

FIG. 43 is a flowchart showing an example of the prepaid card unit control processing in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not the VL signal input from the card unit control microcomputer has been detected (step S755a). If the VL signal has not been detected, the VL signal non-detection counter is incremented by 1 (step S755b). The payout control CPU 37
1 checks whether the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CP
U371 stops the emission control signal output to the emission control board 91 and stops the drive motor 94 (step S7).
55d).

With the above processing, 125 times (2 ms ×
(125 = 250 ms) If the OFF of the VL signal is detected continuously, the state is set to the ball firing prohibited state.

If the VL signal has been detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the output of the firing control signal has been stopped (step S755f), the payout control CPU 371 starts outputting the firing control signal to the firing control board 91 to make the drive motor 94 operable (step S755g). .

FIGS. 44 and 45 show steps S756.
It is a flowchart which shows an example of the ball lending control process.
In this embodiment, the maximum value of the number of consecutive payouts is one unit of the lending ball (for example, 25), but the maximum value of the number of consecutive payouts may be another number.

In the ball lending control process, the payout control CP
U371 confirms whether or not the ball lending is stopped (step S510). If stopped, the process ends.
Whether or not the ball lending is stopped is confirmed by checking whether or not the payout suspension flag set in the payout suspension state setting process shown in FIG. 41 is on.

If the ball lending is not stopped, the payout control CP
The U371 checks whether or not the lending ball is being paid out (step S511). If the lending ball is being paid out, the process shifts to a ball lending process shown in FIG. Whether or not the ball is being paid out is determined based on the state of a ball lending process flag described later. If the ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S512). Whether or not a prize ball is being paid out is determined by the state of a prize ball processing flag described later.

If neither a loaned ball is being paid out nor a prize ball is being paid out, the payout control CPU 371 checks whether or not a ball lending request has been issued from the card unit 50 (step S5).
13). If there is a request, the ball lending process flag is turned on (step S514), and 25 (the number of ball lending units: 100 yen here) is set in the lending ball number storage in the backup RAM area (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distributing solenoid 310 is driven to set the ball distributing member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout control CPU 371 sets the motor rotation time for paying out 25 game balls, or determines the number of output pulses according to the motor rotation time. Then, the payout motor 289 is turned on (step S51).
8), the process proceeds to the ball lending process shown in FIG.

[0270] Turning on the payout motor 289
Strictly, the BRQ signal is turned off to indicate that the card unit 50 has recognized the reception. Further, the ball lending process flag is set in the backup RAM area.

FIG. 45 is a flowchart showing processing during lending a ball in the payout control processing by the payout control CPU 371. The payout control CPU 371 confirms whether or not the rental ball passage waiting time is in progress (step S51).
9). If it is not during the lending ball passage waiting time, the motor position sensor is checked (step S520), and a lending count switch check process described later is performed (step S521).

In the checking process of the motor position sensor in step S520, the ON / OFF of the payout motor position sensor is monitored by a timer, but if the ON state or the OFF state continues for a predetermined time or more, the payout control CPU 371 is started.
Determines that a motor ball biting error has occurred.

Next, it is confirmed whether or not the driving of the payout motor 289 should be completed (whether one unit of the payout operation has been completed) (step S522). Specifically, it is confirmed whether or not a rotation time corresponding to a predetermined number of payouts has elapsed. When the rotation time corresponding to the predetermined number of payouts has elapsed,
The payout control CPU 371 stops driving the payout motor 289 (step S523), and sets the waiting time for passing a lent ball (step S524).

If it is during the lending ball passage waiting time in step S519, the payout control CPU 371 performs a ball lending count switch check process described later (step S525) and determines whether the lending ball passage waiting time has ended. Confirmation is performed (step S526). The lending ball passing waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the ball lending count switch 301B.

When confirming the end of the waiting time for passing the rental ball,
Since all the lending balls have been paid out, the EXS signal is turned off to indicate to the card unit 50 that the next ball lending request can be accepted (step S527). In addition, the distribution solenoid is turned off (step S528), and the ball lending processing flag is turned off (step S529). If the last payout ball has not passed through the ball lending count switch 301B before the passage of the ball lending wait time, a ball lending path error is determined. In this embodiment, the prize ball and the ball lending are performed by the same payout device.

[0276] The payout control means, besides storing the number of lent balls,
It is preferable to control a counter that counts the number of payouts of one lending ball. In that case, the counter is incremented by one each time the lending ball count switch 301B is turned on, and the count value of the counter is checked at the end of the lending ball passage waiting time. Then, when the count value is smaller than the number of lending balls per unit, the correction payout process may be executed. Specifically, returning to step S518,
The payout motor 289 is turned on again. then,
As the rotation time of the payout motor 289, a time is set that allows the shortage to be paid out. When the count value is larger than the number of lending balls per unit, for example, it may be determined that an abnormality has occurred in the lending ball count switch 301B and an error may be notified.

After the EXS signal indicating the acceptance of the ball lending request is turned off and the BRQ signal, which is the ball lending request signal, is turned on again within a predetermined period, the ball lending without turning off the sorting solenoid and the payout motor is performed. The processing may be continued. That is, a predetermined unit (100 yen unit in this example)
Instead of performing the ball lending process every time, the ball lending process may be performed continuously.

The contents of the number-of-lended-balls storage are retained by the backup power supply of the power supply board 910 for a predetermined period even when the power supply to the gaming machine is stopped. Therefore, when the power supply is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the lending ball number storage.

FIG. 46 shows steps S521 and S52.
It is a flowchart which shows the ball lending count switch check process performed in 5. The ball lending count switch check process is a process of monitoring the state of the ball lending count switch 301B and subtracting the lending ball number storage.

In the ball lending count switch check processing, the payout control CPU 371 first checks whether or not the ball lending count switch ON waiting flag is set (step S811). If the ball lending count switch ON waiting flag is set, the system waits until the ball lending count switch ON flag is turned on (step S812). The ball lending count switch-on flag is set in step S752o in the switch processing shown in FIG. If the timer T11 times out before the ball lending count switch on flag is turned on, the ball lending path error flag is set (steps S817 and S818). Ball rental count switch 3
When 01B is turned on, the timer T11 is stopped (step S813), and the ball lending count switch ON waiting flag is reset (step S814). Note that the timer T
Reference numeral 11 denotes a timer for checking whether or not the ball lending count switch 301B is turned on within a predetermined period.

When the ball lending count switch 301B is turned on, a ball lending count switch OFF wait flag indicating that the ball lending count switch 301B is in the off state is set in order to confirm that the ball lending count switch 301B is turned off ( Step S815).

Therefore, if the ball lending count switch OFF waiting flag is on (step S821), the payout control CPU 371 waits for the ball lending count switch on flag to turn off (step S824). When the ball lending count switch on flag is turned off, the ball lending count switch OFF waiting flag is reset (step S825). Then, it is determined that one game ball has been paid out, and the temporary counting counter is incremented by 1 (step S826). Also, a ball lending information output processing subroutine for outputting a ball lending number signal is started (step S827). Next, the rental ball number memory is reduced by -1.
(Step S828).

In step S821, if it is confirmed that the ball lending count switch OFF waiting flag is not on, the timer T11 is started (step S821).
822), a ball lending count switch ON waiting flag is set (step S823).

FIG. 47 is a flowchart showing the operation of a ball lending information output processing subroutine (step S827) started when the payout (lending) of one game ball is completed. In the ball lending information output subroutine, the payout control CPU 371 first checks whether the Tf timer is operating (whether the ball lending number signal is on) (step S781). If it is operating, it is checked whether or not a timeout has occurred (step S782). When the timeout occurs, the ball lending number signal is turned off (= 0) (step S783).

If the Tf timer is not operating, it is checked whether the value of the temporary counter is a multiple of N (25 in this example) (step S784). The value of the temporary counter is incremented by one when the payout of one game ball is completed.
N is the number of game balls lent for 100 yen. If the value of the temporary counter is a multiple of N, the ball lending number signal is turned on (= 1) (step S785), and the Tf timer is started (step S78).
6).

With the above processing, when a ball lending for 100 yen is performed, the ball lending number signal is turned on for a time (for example, 0.1 second) created by the Tf timer.
The ball lending number signal from the payout control CPU 371 is the same as the prize ball information signal from the main board 31, and the terminal board 1
60. Then, it is output from the ball lending terminal of the terminal board 160 to the outside of the gaming machine.

FIGS. 48 and 49 show steps S758.
It is a flowchart which shows an example of the award ball control processing. In this example, the maximum value of the number of continuous payouts is the same as one unit of the lending ball (for example, 25), but the maximum value of the number of continuous payouts may be another number.

In the prize ball control processing, a payout control CPU
The 371 first checks whether or not the award ball is stopped (step S530). If stopped, the process ends. Whether or not the ball lending is stopped is confirmed by checking whether or not the payout suspension flag set in the payout suspension state setting process shown in FIG. 41 is on.

If the prize ball is not stopped, the payout control CPU
The 371 checks whether or not the loaned ball is being paid out (step S531). If the ball is being paid out, the process ends. Whether or not the ball is being paid out is determined based on the state of the ball lending process flag. If the ball is not being paid out, it is checked whether or not the prize ball payout process has already been started, that is, whether or not the prize ball is being paid (step S53).
2). If it is during a prize ball, the processing moves to the processing during a prize ball shown in FIG. Whether or not a prize ball is being determined is determined by the state of a prize ball processing flag described later.

If the prize ball is not being paid out, the payout control CPU
371 checks whether or not the number of prize balls (the number of unpaid prize balls) stored in the total number memory is not 0 (step S5).
34). If the number of prize balls stored in the total number storage is not 0, the prize ball control CPU 371 turns on the prize ball processing flag (step S535), and the value of the total number storage is 2
It is checked whether the number is 5 or more (step S536). The award ball processing flag is set in the backup RAM area.

If the number of prize balls stored in the total number storage is 25 or more, the payout control CPU 371 controls the payout motor 289 to rotate the payout motor 289 until 25 game balls are paid out. In order to output a drive signal, a 25-piece payout operation is set (step S53).
7). Specifically, a motor rotation time for paying out 25 game balls is set, and the number of output pulses according to the motor rotation time is determined.

If the number of prize balls stored in the total number storage is not 25 or more, the payout control CPU 371 rotates the payout motor 289 until the game balls corresponding to the number stored in the total number storage are paid out. In order to output a drive signal so as to cause the total number payout operation, setting is performed (step S538). Specifically, a motor rotation time for paying out game balls is set, and the number of output pulses is determined according to the motor rotation time. Next, the payout motor 289 is turned on (step S539). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the winning ball side. Then, the processing shifts to a processing during payout of prize balls in a prize ball control processing shown in FIG.

FIG. 49 is a flowchart showing an example of processing during a prize ball in the payout control processing by the payout control CPU 371. In the processing during the prize ball, the payout control C
The PU 371 confirms whether or not the award ball passing waiting time is in progress (step S541). If it is not during the prize ball passage waiting time, the motor position sensor is checked (step S542), and a prize ball count switch check process described later is performed (step S543).

In the motor position sensor check process in step S542, the ON / OFF state of the motor position sensor is monitored by a timer. If the ON state or the OFF state continues for a predetermined time or longer, the payout control CPU 371 sets
It is determined that a motor ball biting error has occurred.

Then, the payout control CPU 371 determines whether the driving of the payout motor 289 should be terminated (25 or 25).
It is determined whether or not a predetermined number of payout operations is completed (step S544). Specifically, it is confirmed whether or not a rotation time corresponding to a predetermined number of payouts has elapsed. When the rotation time corresponding to the predetermined number of payouts has elapsed, the payout control CPU 371 stops driving the payout motor 289 (step S545) and sets a prize ball passing waiting time (step S546). The prize ball passing waiting time is a time from when the last payout ball is paid out by the payout motor 289 to when it passes through the prize ball count switch 301A.

If it is determined in step S541 that the award ball passage waiting time is in progress, the payout control CPU 371 performs an award ball count switch check process described later (step S541).
547) It is checked whether or not the waiting time for award ball passage has ended (step S548). When the prize ball passage waiting time ends, all the prize balls set in step S537 or step S538 have been paid out. Therefore, the payout control CPU 371 turns off the award ball processing flag (step S549). If the last payout ball has not passed through the prize ball count switch 301A before the prize ball passage waiting time elapses, it is determined that a prize ball path error has occurred.

Note that, in this embodiment, step S5
According to the judgment of 31, the ball lending is given priority over the prize ball processing, but the prize ball processing may be given priority over the ball lending.

It is preferable that the payout control means also controls a counter for counting the number of payouts set in step S537 or S538, in addition to storing the total number. In this case, the counter is incremented by one each time the winning ball count switch 301A is turned on, and the count value of the counter is checked at the end of the waiting time for passing the winning ball. If the count value is smaller than the number of payouts set in step S537 or S538, a corrected payout process may be executed. Specifically, returning to step S539,
The payout motor 289 is turned on again. then,
As the rotation time of the payout motor 289, a time is set that allows the shortage to be paid out. If the count value is larger than the payout number set in step S537 or S538, for example, the prize ball count switch 301
It may be determined that an abnormality has occurred in A and an error notification may be made.

FIG. 50 shows steps S543 and S54.
7 is a flowchart showing a prize ball count switch check process executed in Step 7. The prize ball count switch check process is a process of monitoring the state of the prize ball count switch 301A and subtracting the total number storage.

In the award ball count switch check processing, the payout control CPU 371 first checks whether or not the award ball count switch ON waiting flag is set (step S831). If the award ball count switch ON waiting flag is set, it waits until the award ball count switch ON flag is turned on (step S83).
2). Note that the prize ball count switch-on flag is
Step S752f in the switch processing indicated by 0
Set by If the timer T12 times out before the winning ball count switch on flag is turned on, the winning ball path error flag is set (step S837,
S838). When the award ball count switch 301A is turned on, the timer T12 is stopped (step S833), and the award ball count switch ON waiting flag is reset (step S834). The timer T12 is a timer for confirming whether or not the award ball count switch 301A is turned on within a predetermined period.

When the prize ball count switch 301A is turned on, a prize ball count switch OFF wait flag is set to indicate that the prize ball count switch 301A is turned off in order to confirm that the prize ball count switch 301A is turned off. Step S835).

Therefore, if the prize ball count switch OFF waiting flag is on (step S841), the payout control CPU 371 waits for the prize ball count switch on flag to turn off (step S844). When the award ball count switch on flag is turned off, the award ball count switch OFF waiting flag is reset (step S8).
45). Then, the total number storage is decremented by one (step S).
848).

If it is confirmed in step S841 that the award ball count switch OFF wait flag is not on, the timer T12 is started (step S841).
842), the award ball count switch ON waiting flag is set (step S843).

[0304] The contents of the total number storage and the number of lent balls storage are stored by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the payout control CP
U371 can continue the payout process based on the contents of the total number storage and the rental ball number storage.

The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number storage, but for each prize ball number (for example, 15, 10 or 6).
). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout corresponding to the number counter is performed, the number counter is decremented by one (in this case, the subtraction processing is performed in the payout control processing).
Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the payout control CPU 371
Can continue the award ball payout process based on the content of each number counter.

Next, error processing will be described. FIG.
Reference numeral 1 denotes an error type and an error display LED 374 (FIG. 7).
FIG. 9 is an explanatory diagram showing a relationship with the display of FIG. FIG.
2 and FIG. 53 are flowcharts showing an example of the error processing in step S760.

In this example, in the error processing, the payout control CPU 371 turns on the error display LED 37 when the winning ball path error flag is turned on (step S601).
4 is displayed as "0" (step S602). When the prize ball path error flag is turned off, the error display LE is displayed.
The display “0” of D374 is deleted (step S60).
3). The prize ball path error flag is set in step S838 shown in FIG. That is, it is set when the award ball count switch 301A is not turned on.

When the ball lending route error flag is turned on (step S604), "1" is displayed on the error display LED 374 (step S605). Also, when the ball lending path error flag is turned off, an error display LED
The display “1” of 374 is deleted (step S606).
The ball lending path error flag is set in step S818 shown in FIG. That is, it is set when the ball lending count switch 301B is not turned on.

If the award ball clogging flag is turned on (step S607), "2" is displayed on the error display LED 374.
Is displayed (step S608). Further, when the award ball clogging flag is turned off, the display “2” of the error display LED 374 is deleted (step S609). The prize ball jam flag is set in step S752d shown in FIG. That is, the prize ball count switch 301
Set when A did not turn off.

When the lending ball clogging flag is turned on (step S610), "3" is displayed on the error display LED 374 (step S611). Further, when the lending ball jam flag is turned off, an error display LED 37 is displayed.
The display “3” of 4 is deleted (step S612). Note that the loaned ball jam flag is set in step S752m shown in FIG. That is, it is set when the ball lending count switch 301B has not been turned off.

[0311] If a motor sensor output abnormality is detected (step S613), "4" is displayed on the error display LED 374 (step S614). Also, when the motor sensor output abnormality is released, an error display LED
The display “4” of 374 is deleted (step S615).
Note that the motor sensor output abnormality is determined in step S520 shown in FIG. 45 or step S542 shown in FIG.
It is detected when the motor position sensor has been on for more than a predetermined period or has been off for more than a predetermined period.

When the VL off detection flag is set (step S621), "5" is displayed on the error display LED 374 (step S622). When the VL off detection flag is reset, an error display L is displayed.
The display “5” of the ED 374 is deleted (step S62).
3). The VL off detection flag is set in step S755e shown in FIG.

When communication with the card unit 50 is executed at an irregular timing (step S6).
24) Assuming that a prepaid card unit communication error has occurred, "6" is displayed on the error display LED 374 (step S625). Further, when such an error is resolved, the display “6” of the error display LED 374 is deleted (step S626).

When the payout is stopped (step S627), "7" is displayed on the error display LED 374.
Is displayed (step S628). When the payout stop state is released, the display “7” of the error display LED 374 is erased (step S629). Note that the payout stop state is a state in which the payout stop state is set in step S753c in FIG. That is, this is the state after the payout prohibition is notified from the game control means by the payout stop state designation command.

In this embodiment, the ball payout device 9
7 performs both prize ball payout and ball lending, the payout suspension state is a state in which both prize ball payout and ball lending are stopped. However, if the payout device for paying out prize balls and the payout device for lending balls are provided independently, the LE for error display is provided.
In D374, the prize ball stop state and the ball lending stop state may be separately notified.

As described above, in this embodiment, even when the shortage of the game balls to be paid out is detected (when the ball runs out), and when the game balls should not be paid out with the lower plate full. Then, the payout stop state designation command, which is the same command, is notified from the game control means to the payout control means (see FIG. 22). That is, a common command is transmitted from the game control means to the payout control means even if the conditions for stopping the prize ball payout are different. In other words, even when any of the prize ball stop conditions is satisfied, a common control command instructs the payout control means that the prize ball can not be paid out.

Further, when the game balls can be paid out, the prize ball is sent to the payout control means by the common payable state designation command, regardless of the prize ball payout stop condition under any of the payout stop conditions. Instructs that the dispensing is possible. As a result, there is an advantage that a load relating to information transmission from the game control means to the payout control means is reduced, a program capacity in the game control means is reduced, and a program capacity which can be used for game control is increased. Also,
The number of commands transmitted from the main board 31 to the payout control board 37 can be reduced.

The same command is used for lending a ball even when a shortage of game balls to be paid out is detected (when the ball runs out) and when the game balls should not be paid out when the lower plate is full. The payout stop state designation command is notified from the game control means to the payout control means. In other words, a common command is transmitted from the game control means to the payout control means even if the conditions for stopping the ball lending are different. In other words,
Regardless of which ball lending stop condition is satisfied, a common control command instructs the payout control means that ball lending is not possible.

[0319] Further, when the game balls can be paid out, the ball lending can be performed to the payout control means by the common payable state designation command regardless of the ball lending stop condition under any of the payout stop conditions. Command that it is possible. Therefore, the load of information transmission from the game control means to the payout control means is reduced, and the program capacity of the game control means is reduced, and the program capacity for game control is increased. Further, the number of commands transmitted from the main board 31 to the payout control board 37 can be reduced.

Further, as described above, when the CPU 56 outputs the payout stop state designation command, the payout control board 3
7 to store the data (payout stop flag that has been set) to indicate that the payout is instructed to be prohibited, and to output the payout control board 37 when outputting the payable state designation command. By performing processing for storing data (reset payout stop flag) for indicating that permission has been instructed, the contents of the stored data (state of payout stop flag) are confirmed. With a simple process, the payout control board 37
The control state related to the dispensing of can be grasped.

Also, as described above, the payout control CPU
371 performs a process of storing data (payout suspension flag set) indicating that the payout is prohibited in response to receiving the payout stop state designation command, and responding to the reception of the payout possible state designation command. By performing processing for storing data indicating that the payout is permitted (reset payout suspension flag),
It is possible to determine whether or not to pay out the game media by a simple process of checking the content of each of the stored data (the state of the payout suspension flag). Therefore, the load on the payout control means in the payout control is reduced.

In the above embodiment, when the payout control means receives the payout stop state designation command, both the ball lending and the prize ball payout are stopped, and both the ball lending and the prize ball payout are performed according to the payout possible state designation command. Both are returned to a possible state, that is, the prize withdrawal prohibition state designation command and the lending prohibition state designation command are shared, and the prize withdrawal permission state designation command and the lending permission state designation command are shared. However, the payout prohibition instruction for the prize ball and the payout prohibition instruction for the ball lending may be different commands, and the payout permission instruction for the prize ball and the payout permission instruction for the ball lending may be different commands. Even in this case, a common command is sent from the game control means to the payout control means even if the conditions for prohibiting / permitting prize balls are different. Can be sent from the game control means to the payout control means.

However, when the payout control means receives the payout stop state designation command, both the ball lending and the prize ball payout are stopped. When the payout possible state designation command is received, both the ball lending and the prize ball payout become possible. That is, in other words, the ball lending and the prize ball payout are stopped by one command, and when the stopped state is released, the game control means is compared with the case of using the stop instruction command and the stop release instruction command for each. The load related to information transmission to the payout control means is further reduced.

In the above-described embodiment, the payout means is configured to be able to perform ball lending and prize ball payout. However, even if the mechanism for lending balls and the mechanism for paying out prize balls are independent. The present invention can be applied. In that case, even if the mechanism for lending the ball and the mechanism for paying out the prize ball are independent, as long as the payout control means is configured to control both mechanisms, as in the above embodiment, A common prize payout indicating that the game control means prohibits payout of game media as a prize from a mechanism for paying out prize balls in the payout means, even if any of a plurality of prize payout prohibition conditions is satisfied. A prohibition state designation command is transmitted to the payout control means, indicating that the lending of game media from the mechanism for lending a ball in the payout means is prohibited even if any of the plurality of lending prohibition conditions is satisfied. It can be configured to transmit a common lending prohibition state designation command to the payout control means.

In the above-described embodiment, the payout control means detects that the INT signal relating to the payout control signal has risen, and starts a process of fetching 1-byte data by, for example, an interrupt process. Since a receiving ring buffer (a receiving buffer in this example) capable of storing a plurality of payout control commands is provided, after the payout control command is received, the next payout control command is issued before control based on the command is started. Does not mean that the command is not received by the payout control means.

Also, as shown in the flowcharts of FIGS. 22 to 24, the game control means is configured to be able to execute the command set processing of step S251 even when the payout is stopped (step S201). Have been.
Therefore, even if the payout is stopped, a payout control command indicating the number of payouts is transmitted to the payout control means when a prize is detected.

[0327] In the payout control means, the interruption process is started even when the payout is stopped, so that the payout control means can receive the payout control command even when the payout is stopped. While the payout is stopped, the payout process according to the received payout control command is stopped. The paid-out control command does not disappear in the payout control means.

In the payout control means, a command reception number counter is used as address indicating means for indicating in which area of the receiving ring buffer the transmission command is stored. Therefore, it is easy to determine which area should be used.

Further, electric power is supplied from the main board 31 to the prize ball count switch 301A as a prize game medium detecting means. Therefore, even if a failure occurs in the payout control board 37, the detection function of the premium game medium detecting means does not become disabled due to the influence. Further, since the detection signal of the prize ball count switch 301A is input to both the main board 31 and the payout control board 37, it is possible to execute control based on the detection signal in both the game control means and the payout control means. it can. For example, the game control means can create information (prize ball information signal in the above example) related to the number of paid out game media based on the detection signal of the prize ball count switch 301A.

On the other hand, power is supplied from the payout control board 37 to the ball lending count switch 301B as lending game medium detecting means. Even if a failure occurs in the main board 31, it is not impossible to detect the rented game balls.

The payout control means is based on the detection signal of the prize ball count switch 301A, and the ball payout device 97
Can be determined whether or not an abnormality has occurred. That is, it is possible to determine whether or not a payout abnormality has occurred in the payout means based on the detection signal of the premium game medium detection means. For example, when the detection signal of the winning ball count switch 301A does not turn on, it is determined that a winning ball path error has occurred. Also, it is possible to determine whether or not a payout abnormality has occurred in the prize game medium detecting means based on the detection signal of the prize game medium detecting means. For example, when the ON state of the detection signal of the prize ball count switch 301A continues, it is determined that a prize ball count switch ball clogging error has occurred.

Further, it is possible to determine whether or not a payout abnormality of the payout means or a detection abnormality of the prize game medium detection means has occurred based on the number of payouts specified by the detection signal of the prize game medium detection means. That is, if the payout control means is configured to control a counter for counting the number of payouts in addition to the total number storage, the number of payout game media (count value of the counter) based on the detection signal of the premium game medium detection means ), It is possible to determine whether or not a payout abnormality of the payout means or a detection abnormality of the premium game medium detection means has occurred. For example, when the number of payouts specified by the detection signal of the prize game medium detecting means is larger than the original number of payouts, it is determined that the payout means of the payout means or the detection abnormality of the prize game medium detecting means has occurred. Is done.

In the above-described embodiment, the prize game medium detecting means, ie, the prize ball counting switch 301A, is exemplified as the payout detecting means, and the lending game medium detecting means, ie, the ball lending count switch 301A, is used as the lending detecting means.
However, these may be other detection means capable of detecting the payout state of the game medium, for example, a payout motor position sensor.

The pachinko gaming machine 1 according to the above-described embodiment mainly provides a predetermined game value when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a winning start becomes a predetermined symbol combination. Is a first-class pachinko gaming machine that can be awarded to a player, but a predetermined gaming value can be awarded to a player if there is a prize in a predetermined area of an electric accessory that opens based on a winning start. A predetermined right is generated or continued when there is a prize to a predetermined pachinko gaming machine or a predetermined electric accessory which is opened when a stop symbol of a symbol variably displayed based on a winning prize becomes a predetermined symbol combination. The present invention may be applied to a third-type pachinko gaming machine.

Further, the present invention is not limited to pachinko game machines whose game medium is a game ball, and the present invention can be applied to slot machines and the like. For example, the present invention can be applied to a slot machine in which at least a payout control board is provided in addition to the main board.

FIG. 54 is a front view of the front door of one example of the slot machine viewed from the front. As shown in FIG. 55, in the slot machine 500, a game panel 501 is detachably attached near the center. Also, the game panel 501
A variable display area 502 in which a plurality of types of symbols are variably displayed is provided near the center of. Variable display area 502
Bet lamp 503, two bet lamp 5
04 and three betting lamps 505 are provided. On the right side of the variable display area 502, a game over lamp 506, a replay lamp 507, a weight lamp 5
08, a start lamp 509 and a medal insertion instruction lamp 510 are provided.

Below the variable display area 502 are provided a 7-segment LED credit display 511, a 7-segment LED game count display 512, and a 7-segment LED payout display 513. In this embodiment, the variable display area 502 includes
There are three symbol display areas, "left", "middle", and "right", and symbol display reels 514a, 514b, 514c are provided corresponding to the respective symbol display areas.

At the lower part of the game panel 501, there is provided an operation table 520 on which various input switches for a player to perform various operations are arranged. Operation table 5
BET switch 521 for betting (betting) coins one by one on the back side of 20, and BET coins by the maximum number (for example, three) that can be bet in one game
A MAXBET switch 522, a settlement switch 523, and a coin insertion slot 524 are provided.
The coin inserted into the coin insertion slot 524 is detected by an inserted coin sensor (not shown). In this example,
Each time a coin is inserted from the coin insertion slot 524, the numerical value displayed on the credit indicator 511 is increased by one, for example, up to 50 coins. Then, each time the BET switch 521 is pressed and one coin is bet, the numerical value displayed on the credit indicator 511 is reduced by one. In addition, every time the MAXBET switch 522 is pressed and three coins are bet, the numerical value displayed on the credit indicator 511 is reduced by three.

On the front side of the operation table 520, a start switch 525, a left reel stop switch 526
a, a middle reel stop switch 526b, a right reel stop switch 526c, and a coin jam clearing switch 527 are provided. Lamps 528a and 528b are provided on the left and right sides of the operation table 520, respectively. A title panel 530 that is detachably attached is provided below the operation table 520. On the title panel 530, the model name of the slot machine is drawn. A speaker 531 for outputting a sound effect or the like is provided below the title panel 530.
Further, a coin storage plate 532 is provided below the title panel 530 to store more coins than the number that can be stored internally (for example, 50).

At the upper part of the game panel 501, there is provided a panel 540 which is detachably attached. In the vicinity of the center of the panel 540, an LCD (liquid crystal display) 541 for notifying a player of a game method, a game state, and the like is provided. For example, when a winning occurs, an image in which the character performs a predetermined operation is displayed on the LCD 541 to notify the player that a winning flag described later is set. On the upper part of the panel 540, lamps 542, 543, and 544 for notifying various information are provided. In addition, on the left and right sides outside the panel 540, two sound effects are emitted.
Two speakers 545a and 545b are provided. Further, game effect lamps 550, 551, 552, 553 are provided around the outside of the game panel 501.

In such a slot machine, a main board,
When an effect control board and a payout control board are provided and the payout control means mounted on the payout control board is configured to control the payout device based on a control command transmitted from the main board, The invention can be applied.

[0342]

According to the first aspect of the present invention, the detection signal of the prize game medium detecting means is inputted to the game machine and the game control means, and the payout state of the prize game medium can be specified. Is mounted on the game control board, which has power supply means for supplying power to the prize game medium detecting means, has a plurality of prohibition conditions for prohibiting payout of the prize game media, and the game control means has a plurality of prohibition conditions. Is configured to perform a process of transmitting a common payout prohibition state designation command indicating prohibition of payout of premium game media to the payout control means, regardless of which of the conditions is satisfied. The load related to the transmission of information relating to prohibition of payout of premium game media to the payout control means can be reduced, and the program capacity of the game control program can be reduced. Both the effect capable of managing the payout status of the prize game medium at the game controller.

In the invention according to claim 2, when the prohibition condition is released and none of the prohibition conditions is satisfied, the game control means establishes any one of the plurality of prohibition conditions. Regardless of whether or not the payout of the prize game media is performed, a process of transmitting a common payout permission state designation command indicating that the payout of the prize game medium is permitted to the payout control means is performed. The load on information transmission relating to cancellation of prohibition of payout of premium game media to the control means is further reduced.

In the invention according to claim 3, the detection signal of the prize game medium detecting means is configured to be input to both the game control means and the payout control means, so that a plurality of prize game medium payout states are provided. Can be managed by the control means.

[0345] According to the invention of claim 4, the detection signal of the lending game medium detecting means is input to the payout control means, the payout state of the lending game medium can be specified, and the payout control board on which the payout control means is mounted. In addition, since the power supply means for supplying power to the rental game medium detecting means is provided, the payout state of the rental game medium can be managed by the payout control means.

According to the fifth aspect of the present invention, the game control means includes storage means for storing the number of prize game media for which payout has not been completed, and when a prize is generated, the prize game medium is paid out in accordance with the prize. The scheduled number is added to the stored value stored in the storage means, and the number of payouts of the premium game media specified by the detection signal of the premium game medium detection means is subtracted from the stored value stored in the storage means. Therefore, the number of premium game media for which the payout has not been completed can be specified by the value stored in the storage means of the game control board.

In the invention according to claim 6, the game control means can transmit a command for designating the number of payouts of the prize game medium to the payout control means, and the prize based on the command for specifying the number of payouts transmitted last time. Regardless of whether or not the payout of the game media has been completed, a command for designating a new payout number is transmitted to the payout control means, so that the processing load on the payout of the game control means is reduced. In addition, the payout process of the premium game media can be quickly performed.

[0348] In the invention according to claim 7, the game control means determines that the prohibition condition is satisfied when the storage state detection means detects that a predetermined amount or more of game media is stored in the storage section. With such a configuration, it is possible to prevent an operation in which the payout control unit executes the payout process even when a predetermined amount or more of game media is stored in the storage unit.

According to the eighth aspect of the present invention, the game control means determines that the prohibition condition is satisfied when the game medium exhaustion detection means detects that the predetermined amount of game media is not secured. Therefore, it is possible to prevent an operation in which the payout control unit executes the payout process even though the predetermined amount of game media to be supplied to the payout unit is not secured.

According to the ninth aspect of the present invention, when the game control means transmits a command to the payout control means, it is configured to output the command only once in a receivable manner. There is an effect that control for transmission is simplified.

According to the tenth aspect, the command is:
Since the payout control means includes command data and a capture signal instructing the capture of the command data, and the payout control means is configured to capture the command data in response to the capture signal being output from the game control means, the command Can reliably receive the command.

According to the eleventh aspect of the present invention, the game control means executes the game control processing based on the occurrence of a timer interrupt that occurs periodically, and the remaining time required for the game control processing is expressed as: It is configured to execute the process of updating the counter used for game control, and to set the interrupt prohibition during the process of updating the counter with extra time. It is possible to prevent a problem from occurring and causing a problem in updating the counter.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view showing the front of the game board with the glass door frame removed.

FIG. 3 is a rear view of the gaming machine as viewed from the rear.

FIG. 4 is a rear view of the mechanism plate to which various members are attached, as viewed from the rear side of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of a ball payout device.

FIG. 6 is a block diagram showing a circuit configuration of a game control board (main board).

FIG. 7 is a block diagram illustrating a circuit configuration example of a payout control board.

FIG. 8 is a block diagram illustrating a circuit configuration example of a power supply board.

FIG. 9 is a circuit diagram showing an electrical control mode of a winning ball count switch and a ball lending count switch.

FIG. 10 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 11 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 12 is an explanatory diagram showing an example of bit assignment of an input port.

FIG. 13 is a flowchart showing a main process executed by a CPU on a main board.

FIG. 14 is a flowchart showing a 2 ms timer interrupt process.

FIG. 15 is a flowchart showing a special symbol process process.

FIG. 16 is an explanatory diagram illustrating an example of a command form of a control command.

FIG. 17 is a timing chart showing a relationship between an 8-bit control signal (command data) constituting a control command and an INT signal.

FIG. 18 is an explanatory diagram showing an example of the content of a payout control command.

FIG. 19 is an explanatory diagram showing an example of forming a switch timer in a RAM.

FIG. 20 is a flowchart illustrating an example of a switch process.

FIG. 21 is a flowchart illustrating an example of a switch check process.

FIG. 22 is a flowchart illustrating an example of a prize ball process.

FIG. 23 is a flowchart illustrating an example of a prize ball process.

FIG. 24 is a flowchart illustrating an example of a prize ball process.

FIG. 25 is a flowchart showing a switch-on check process.

FIG. 26 is an explanatory diagram showing a configuration example of an input determination value table.

FIG. 27 is an explanatory diagram showing a configuration example of a command transmission table and the like.

FIG. 28 is a flowchart illustrating a processing example of a command set process.

FIG. 29 is a flowchart illustrating a command transmission processing routine.

FIG. 30 is a flowchart showing a winning ball number subtraction process.

FIG. 31 is a flowchart showing a prize ball information signal output process.

FIG. 32 is a timing chart showing an example of an output timing of a prize ball information signal.

FIG. 33 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 34 is an explanatory diagram showing an example of bit assignment of an input port.

FIG. 35 is a flowchart showing a main process executed by a CPU in a payout control board.

FIG. 36 is a flowchart showing a 2 ms timer interrupt process of the payout control means.

FIG. 37 is an explanatory diagram showing one configuration example of a RAM in the payout control means.

FIG. 38 is an explanatory diagram showing a configuration example of a reception command buffer in the payout control means.

FIG. 39 is a flowchart illustrating an example of a command receiving process executed by a payout control CPU.

FIG. 40 is a flowchart illustrating an example of a switch process.

FIG. 41 is a flowchart illustrating an example of a payout stop state setting process.

FIG. 42 is a flowchart illustrating an example of a command analysis execution process.

FIG. 43 is a flowchart showing an example of a prepaid card unit control process.

FIG. 44 is a flowchart illustrating an example of a ball lending control process.

FIG. 45 is a flowchart illustrating an example of a ball lending control process.

FIG. 46 is a flowchart illustrating an example of a ball lending count switch check process.

FIG. 47 is a flowchart illustrating an example of ball lending information output processing.

FIG. 48 is a flowchart illustrating an example of a winning ball control process.

FIG. 49 is a flowchart illustrating an example of a winning ball control process.

FIG. 50 is a flowchart illustrating an example of a prize ball count switch check process.

FIG. 51 is an explanatory diagram showing the relationship between the type of error and the display of an error display LED.

FIG. 52 is a flowchart illustrating an example of an error process.

FIG. 53 is a flowchart illustrating an example of an error process.

FIG. 54 is a front view of the slot machine as viewed from the front.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 37 Payout control board 53 Basic circuit 56 CPU 301A Prize ball count switch 301B Ball lending count switch 371 CPU for payout control

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2C088 BA21 BA22 BA24 BA27 BA43 BC51 CA14 EB62

Claims (11)

[Claims] 1. A game machine in which a player plays a predetermined game and pays out a prize game medium as a prize in accordance with satisfaction of a predetermined condition, and a game control means for controlling the progress of the game. A payout means for paying out game media, a payout control means for controlling the payout means based on a command from the game control means, and a prize game medium detection means for detecting payout of prize game media, A detection signal of the prize game medium detecting means is input to the game control means, and a payout state of the prize game medium can be specified. The game control board on which the game control means is mounted includes the prize game medium. A power supply unit for supplying power to the detection unit is mounted, and there are a plurality of prohibition conditions for prohibiting payout of the prize game medium, and the game control unit includes any of the plurality of prohibition conditions. Even if the conditions are satisfied, the gaming machine, wherein a common dispensing prohibited state specifies command indicating to prohibit dispensing of the prize game media performs a process of transmitting to the payout control means. 2. The game control means releases the prohibition condition,
If neither prohibition condition is satisfied, a common payout permission indicating that the payout of premium game media is permitted regardless of which of the plurality of prohibition conditions is satisfied. 2. The gaming machine according to claim 1, wherein a process of transmitting the state designation command to the payout control means is performed. 3. The detection signal of the premium game medium detecting means is inputted to both the game controlling means and the payout controlling means.
Or the gaming machine according to claim 2. 4. It is possible to pay out a lending game medium to be lent to a player in response to a lending request, comprising: a lending game medium detecting means for detecting the lending of the lending game medium; A detection signal of the game medium detecting means is input, and a payout state of the rental medium can be specified. Power supply means for supplying power to the rental medium detection means on a payout control board on which the payout control means is mounted. The gaming machine according to claim 1, further comprising: 5. The game control means includes storage means for storing the number of prize game media for which payout has not been completed, and when a prize is generated, the expected payout number of prize game media according to the prize is stored. 5. The method according to claim 1, further comprising adding the number of payouts of the prize game medium specified by the detection signal of the prize game medium detection means to the storage value stored in the storage means. Gaming machine. 6. The game control means can transmit to the payout control means a command designating the number of premium game media to be paid out, and the payout of the premium game media based on the previously transmitted command designating the number of payouts is completed. 6. The gaming machine according to claim 1, wherein a command for designating a new payout number is transmitted to the payout control means regardless of whether or not the payout is performed. 7. A storage state detecting unit for detecting whether or not a predetermined amount or more of game media is stored in a storage unit in which the paid out game media are stored, wherein the game control unit includes: The gaming machine according to claim 1, wherein when a state detecting unit detects that a predetermined amount or more of game media is stored in the storage unit, it is determined that the prohibition condition is satisfied. 8. A game medium shortage detecting means for detecting whether or not a predetermined amount or more of game media supplied to the payout means is secured, and the game control means is provided by the game medium shortage detecting means. 8. The gaming machine according to claim 1, wherein it is determined that the prohibition condition is satisfied when it is detected that a predetermined amount or more is not secured. 9. The gaming machine according to claim 1, wherein the game control means outputs the command only once so as to be receivable when transmitting the command to the payout control means. 10. The command includes command data and a capture signal instructing capture of the command data, and the payout control means captures the command data in response to the capture signal being output from the game control means. The gaming machine according to claim 1. 11. A game control means for executing a game control process based on the occurrence of a timer interrupt that occurs periodically, and is used for controlling a game with a surplus time required for the game control process. The gaming machine according to claim 1, wherein a process of updating a counter is performed, and interrupt prohibition is set during the process of updating the counter with the remaining time.