JP2002246587A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow reduction of a semiconductor chip area by shrinking. SOLUTION: In a semiconductor device, emitter layers of a plurality of semiconductor elements comprising a collector layer, a base layer, and a emitter layer formed on a semiconductor substrate are connected together by an emitter common wiring 13, while the collector layers are connected together by a collector common wiring 9. The collector common wiring 9 is formed at an interlayer insulating film 8 of a first layer and covers a main surface of the semiconductor substrate. The collector layer is connected to the collector common wiring 9 through an opening provided at the interlayer insulating film 8 of the first layer. The emitter common wiring 13 is formed at the interlayer insulating film 12 of a second layer, and covers the interlayer insulating film 8 of the first layer and the collector common wiring 9. The emitter layer is connected to the emitter common wiring through an opening provided at the interlayer insulating film 8 of the first layer, and the interlayer insulating film 12 of the second layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technique effective when applied to a high-speed semiconductor device using a compound semiconductor.

[0002]

2. Description of the Related Art In recent years, in the field of communication and information, there has been a demand for semiconductor devices which operate at higher speeds in order to meet demands for expanding communication demands or increasing the capacity of processing information. Heterojunction Bipolar Transistor (Heterojunction Bipolar) using semiconductor with wide band gap as emitter as operable semiconductor element
Transistor) (hereinafter referred to as HBT). In the HBT, since the emitter has a wide band gap, the reverse injection of minority carriers from the base to the emitter is small, and the emitter injection efficiency is high, so that the current gain is high. Even if the base concentration is increased, a high current gain can be maintained. Therefore, since the base resistance can be reduced, ultra-high-speed operation with high current gain and high driving capability is possible. For this reason, it is used in mobile communication terminal devices and the like, such as mobile phones, which need to efficiently amplify high frequencies in the microwave range.

In a power amplifying transistor used in a transmission amplifier circuit or the like of such a mobile communication terminal device, it is necessary to increase the current in order to increase the transmission output. As a method for achieving this large current, it is common practice to increase the area of each junction surface in a bipolar transistor. For example, a plurality of bipolar semiconductor elements are arranged in parallel, and a stripe-shaped semiconductor element is formed. A multi-finger structure in which the emitter, base and collector are connected in parallel is used.

FIG. 1 is a plan view illustrating an essential part of a semiconductor device having a multi-finger structure, and FIG. 2 is a longitudinal sectional view taken along the line aa in FIG. This semiconductor device is a power HBT, and has a configuration in which a plurality of finger-shaped semiconductor elements shown in FIG. 1 are connected in parallel in order to normally operate with a large current.

[0005] Each unit finger of the semiconductor device of the present embodiment is, for example, a semiconductor substrate 1 made of semi-insulating GaAs.
An n- type collector layer 2 epitaxially formed thereon,
The bipolar transistor has a vertical structure including a p + type base layer 3 formed on the collector layer 2 and an n− type emitter layer 4 formed on the base layer 3. The emitter layer 4 is separated into each finger as a mesa shape.

The collector layer 2 is made of non-doped GaAs.
Buffer layer 2a, n + type GaAs subcollector layer 2
b, an n − -type GaAs collector layer 2 c is sequentially stacked, and the emitter layer 4 is an n − -type InGaP layer 4.
a, n − type GaAs emitter ballast resistance layer 4 b, n
An ohmic layer 4c in which + type InGaAs is stacked on n + -type GaAs is sequentially stacked.

A collector electrode 5, a base electrode 6, and an emitter electrode 7 are connected to the collector layer 2, the base layer 3, and the emitter layer 4, respectively, and are formed on the main surface of the semiconductor substrate 1 and the main surface of the semiconductor substrate 1, respectively. The collector electrode 5, the base electrode 6, and the emitter electrode 7 are covered with an interlayer insulating film 8 made of silicon oxide or the like, and are partially exposed by an opening provided in the interlayer insulating film 8, the collector electrode 5, the base electrode 6, and the emitter. The electrode 7 is connected to a common collector line 9, a common base line 10, and an emitter extraction line 11, respectively. Further, the collector common wiring 9, the base common wiring 10, and the emitter extraction wiring 11 are covered with an interlayer insulating film 12 made of silicon oxide or the like, and the emitter extraction wiring 1 partially exposed by an opening provided in the interlayer insulating film 12.
1 is connected to an emitter common wiring 13 (this section in FIG. 2 is shown in a cross section along the line bb in FIG. 1).

Next, a method of manufacturing the semiconductor device will be described for each process with reference to FIGS. First, MOCVD (MetalOxide) is formed on a semi-insulating GaAs semiconductor substrate 1.
An epitaxial layer serving as a collector layer 2, a base layer 3, and an emitter layer 4 is grown by, for example, an Rganic Chemical Vapor Deposition method, a metal film such as WSi is deposited, and the metal film is patterned by dry etching to form an emitter electrode 7. To form This state is shown in FIG.

Next, the emitter layer 4 is etched into a mesa shape using the patterned emitter electrode 7 as a mask. The etching of the emitter layer 4 is performed by isotropic etching, and the emitter layer 4 is side-etched so as to overhang the emitter electrodes 7 respectively. This state is shown in FIG.

Next, a metal film is formed on the patterned resist mask, and the base electrode 6 is patterned by a so-called lift-off method for removing both the resist mask and the metal film thereon. This state is shown in FIG.

Next, the base layer 3 is etched into a mesa shape to perform so-called base mesa etching for separating each finger, and a collector electrode 5 is formed on the collector layer 2 exposed by this etching. This state is shown in FIG. Next, the collector layer 2 is etched into a mesa shape to electrically separate the plurality of fingers. This state is shown in FIG.

Next, an interlayer insulating film 8 made of, for example, silicon oxide is deposited by a plasma CVD method, and a connection region of the collector electrode 5, the base electrode 6, and the emitter electrode 7 is exposed using a resist mask formed by photolithography. An opening is formed, a metal film made of, for example, AuMo is deposited on the entire surface, and a resist mask is formed by photolithography. Form. This state is shown in FIG.

Thereafter, an interlayer insulating film 12 made of, for example, silicon oxide is deposited by a plasma CVD method, and an opening for exposing a connection region of the emitter extraction wiring 11 is formed using a resist mask formed by photolithography. For example, a metal film made of AuMo is deposited,
A resist mask is formed by photolithography, and the emitter common wiring 13 is formed by patterning using the resist mask, and the state shown in FIG. 2 is obtained.

[0014]

SUMMARY OF THE INVENTION The collector common wiring 9,
In patterning of the base common wiring 10 and the emitter extraction wiring 11, processing by a physical reaction such as ion milling is a main method for processing gold. In such processing, in order to prevent processing residues of the metal film from remaining, it is necessary to provide a certain interval or more between patterns to be processed. For this reason, a layout rule for the minimum size that defines the distance between the patterns and the like is determined, and the layout of the wiring layers is determined according to the rule.

For this reason, the collector common wiring 9, the base common wiring 10, and the emitter extraction wiring 11, which are the wiring layers of the same layer, cannot be formed close to each other.
It is necessary to provide an interval of about m, and it has been difficult to reduce the area of the semiconductor chip by shrinking. In particular, in the power HBT, it is necessary to increase the thickness of the collector layer in order to secure the breakdown voltage between the base and the collector. For this reason, the step from the emitter electrode to the collector layer is usually 2 μm or more, and when the common wiring is formed close to the wiring, the wiring metal tends to remain on the step and the wiring is likely to be short-circuited.

An object of the present invention is to provide a technique capable of solving these problems and reducing the area of a semiconductor chip. The above and other problems and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. A semiconductor device having a collector layer, a base layer, and an emitter layer formed on a semiconductor substrate, wherein the emitter layers of the plurality of semiconductor elements are connected to each other by a common emitter wiring and the collector layers are connected to each other by a common collector wiring The collector common wiring is formed in the first interlayer insulating film covering the main surface of the substrate, and the collector layer and the collector common wiring are connected through an opening provided in the first interlayer insulating film. The emitter common wiring is formed in a second interlayer insulating film covering the interlayer insulating film and the collector common wiring. The emitter common wiring is formed through openings provided in the first interlayer insulating film and the second interlayer insulating film. The emitter common wiring is connected. Further, a base common wiring connecting the base layers of the plurality of semiconductor elements to each other is formed in the first interlayer insulating film as a wiring layer of the same layer as the collector common wiring.

In the same semiconductor device, the collector common wiring is formed in a first interlayer insulating film covering the main surface of the semiconductor substrate, and the collector common wiring is formed through an opening provided in the first interlayer insulating film. An interconnect is connected to the interconnect, and the emitter common interconnect is disposed so as to cross at least a part of a connection portion between the collector layer and the collector common interconnect in a plane.

In the method of manufacturing a semiconductor device described above,
The collector common wiring and the base common wiring are formed in a first interlayer insulating film covering the main surface of the semiconductor substrate, and a collector layer and a collector common wiring are formed through an opening provided in the first interlayer insulating film. Connecting the base layer and the base common wiring, respectively; forming the emitter common wiring on the second interlayer insulating film covering the first interlayer insulating film and the collector common wiring; Connecting the emitter layer and the common emitter wiring through openings provided in the interlayer insulating film and the second interlayer insulating film.

According to the present invention described above, since the emitter lead-out wiring is not provided, the common collector wiring and the common base wiring can be arranged close to the base electrode. Therefore, the occupied area of the unit finger is reduced.
Further, since the emitter common wiring is arranged on the emitter electrode without providing the emitter lead-out wiring, the area occupied by the unit finger can be further reduced. Furthermore,
Since the semiconductor chip can be shrunk by reducing the occupied area, the cost can be reduced.

Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0022]

(Embodiment 1) FIG. 9 is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention, and FIG. FIG. 3 is a longitudinal sectional view taken along line aa of FIG. The semiconductor device of the present embodiment
It is a power HBT, and has a configuration in which a plurality of finger-shaped semiconductor elements shown in FIG.

Each unit finger of the semiconductor device of the present embodiment is, for example, a semiconductor substrate 1 made of semi-insulating GaAs.
An n- type collector layer 2 epitaxially formed thereon,
The bipolar transistor has a vertical structure including a p + type base layer 3 formed on the collector layer 2 and an n− type emitter layer 4 formed on the base layer 3. The emitter layer 4 is separated into each finger as a mesa shape.

The collector layer 2 is made of non-doped GaAs.
Buffer layer 2a, n + type GaAs subcollector layer 2
b, an n − -type GaAs collector layer 2 c is sequentially stacked, and the emitter layer 4 is an n − -type InGaP layer 4.
a, n − type GaAs emitter ballast resistance layer 4 b, n
The structure is such that an ohmic layer 4c in which + InGaP is stacked on n + GaAs is sequentially stacked.

The layer structure of the epitaxial layer is such that an etching stopper layer of InGaP or the like is further disposed between the buffer layer 2a and the sub-collector layer 2b or between the sub-collector layer 2b and the collector layer 2c. It may be. Further, as the semiconductor substrate used in the present invention, in addition to a semiconductor substrate having a semiconductor layer such as an epitaxial layer formed on a semiconductor substrate, a semiconductor substrate formed of a single body, and a semiconductor layer formed on a semiconductor substrate via an insulating layer. It may include various forms such as a substrate (SOI substrate).

A collector electrode 5, a base electrode 6, and an emitter electrode 7 are connected to the collector layer 2, the base layer 3, and the emitter layer 4, respectively, and are formed on the main surface of the semiconductor substrate 1 and the main surface of the semiconductor substrate 1, respectively. The collector electrode 5, the base electrode 6, and the emitter electrode 7 are covered with an interlayer insulating film 8 of silicon oxide or the like, and openings 5b and 6 provided in the interlayer insulating film 8 are provided.
The common collector wiring 9 and the common base wiring 10 which are the same wiring layers are connected to the collector electrode 5 and the base electrode 6 which are partially exposed by b, respectively, and the common collector wiring 9 and the common base wiring 10 are oxidized. Interlayer insulating film 1 of silicon or the like
2 covered.

In the present embodiment, the collector common wiring 9,
Without providing an emitter extraction wiring in the same layer as the base common wiring 10, the collector common wiring 9, the base common wiring 10 and the emitter electrode partially exposed by the openings provided in the interlayer insulating films 8 and 12 are formed. Are connected to emitter common wirings 13 of different layers (partially cut away in FIG. 9).

In the semiconductor device of the present embodiment, since no emitter lead-out wiring is provided, the collector common wiring 9
In addition, the base common wiring 10 can be brought close to the base electrode 6. Therefore, the occupied area of the unit finger is reduced. Further, since the emitter common wiring is arranged on the emitter electrode without providing the emitter lead-out wiring, the occupied area of the unit finger is further reduced. In the unit finger shown in FIG. 9, the conventional unit finger shown in FIG. Approximately half the area occupied by the same function. In particular, in the present embodiment, in order to reduce the occupied area per unit finger, the emitter common wiring 13 is arranged so as to cross over the connection port 5b between the collector electrode 5 and the collector common wiring 9.

Subsequently, a method of manufacturing the semiconductor device will be described for each step with reference to FIGS. First, a collector layer 2, a base layer 3, and an emitter layer 4 are formed on a semi-insulating GaAs semiconductor substrate 1 by MOCVD or the like.
Is grown, a metal film such as WSi is deposited, and the metal film is patterned by dry etching to form the emitter electrode 7. This state is shown in FIG.

Next, the emitter layer 4 is etched into a mesa shape using the patterned emitter electrode 7 as a mask. The etching of the emitter layer 4 is performed by isotropic etching, and the emitter layer 4 is side-etched so as to overhang the emitter electrodes 7 respectively. This state is shown in FIG.

Next, a metal film is formed on the patterned resist mask, and the base electrode 6 is patterned by a so-called lift-off method for removing both the resist mask and the metal film thereon. This state is shown in FIG.

Next, the base layer 3 is etched into a mesa shape to perform so-called base mesa etching for separating each finger, and a collector electrode 5 is formed on the collector layer 2 exposed by this etching. This state is shown in FIG.

Next, the collector layer 2 is etched into a mesa shape to electrically separate a plurality of fingers. This state is shown in FIG. The collector layer 2 may be common to several fingers.

Next, an interlayer insulating film 8 made of, for example, silicon oxide is deposited by a plasma CVD method, and an opening for exposing a connection region between the collector electrode 5 and the base electrode 6 is formed using a resist mask formed by photolithography. A metal film made of, for example, AuMo is deposited on the entire surface;
A resist mask is formed by photolithography, and a collector common wiring 9 and a base common wiring 10 are formed by patterning such as ion milling using the resist mask.
To form FIG. 16 shows this state.

Thereafter, an interlayer insulating film 12 made of, for example, silicon oxide is deposited by a plasma CVD method, and an opening for exposing a connection region of an emitter electrode is formed using a resist mask formed by photolithography. A metal film made of AuMo is deposited, a resist mask is formed by photolithography, and the emitter common wiring 13 is formed by patterning such as ion milling using the resist mask, and the state shown in FIG. 10 is obtained.

(Embodiment 2) FIG. 17 is a plan view showing a main part of a semiconductor device according to another embodiment of the present invention. The semiconductor device of the present embodiment has a power HBT
In order to operate with a large current, a plurality of finger-shaped semiconductor elements shown in FIG. 17 are connected in parallel.

Each unit finger of the semiconductor device of the present embodiment is, for example, a semiconductor substrate 1 made of semi-insulating GaAs.
An n- type collector layer 2 epitaxially formed thereon,
The bipolar transistor has a vertical structure including a p + type base layer 3 formed on the collector layer 2 and an n− type emitter layer 4 formed on the base layer 3. The emitter layer 4 is separated into each finger as a mesa shape.

The collector layer 2 is made of non-doped GaAs.
Buffer layer 2a, n + type GaAs subcollector layer 2
b, an n − -type GaAs collector layer 2 c is sequentially stacked, and the emitter layer 4 is an n − -type InGaP layer 4.
a, n − type GaAs emitter ballast resistance layer 4 b, n
The structure is such that an ohmic layer 4c in which + InGaP is stacked on n + GaAs is sequentially stacked. Further, as the semiconductor substrate used in the present invention, in addition to a semiconductor substrate having a semiconductor layer such as an epitaxial layer formed on a semiconductor substrate, a semiconductor substrate formed of a single body, and a semiconductor layer formed on a semiconductor substrate with an insulating layer interposed therebetween. It may include various forms such as a substrate (SOI substrate).

A collector electrode 5, a base electrode 6, and an emitter electrode 7 are connected to the collector layer 2, the base layer 3, and the emitter layer 4, respectively, and are formed on the main surface of the semiconductor substrate 1 and the main surface of the semiconductor substrate 1, respectively. The collector electrode 5, the base electrode 6, and the emitter electrode 7 are covered with an interlayer insulating film 8 made of silicon oxide or the like, and each of the collector electrode 5, the base electrode 6 is partially exposed by an opening provided in the interlayer insulating film 8. Are connected to the same common wiring layer, that is, a common collector wiring 9 and a common base wiring 10, and the common collector wiring 9 and the common base wiring 10 are covered with an interlayer insulating film 12 such as silicon oxide.

In the present embodiment, the collector common wiring 9,
Without providing an emitter extraction wiring in the same layer as the base common wiring 10, the collector common wiring 9, the base common wiring 10 and the emitter electrode partially exposed by the openings provided in the interlayer insulating films 8 and 12 are formed. Are connected to emitter common wirings 13 of different layers (partially cut away in FIG. 9).

In the semiconductor device of the present embodiment, in order to reduce the area ratio of the base mesa region to the emitter area, the planar shape of the base layer 3 and the emitter layer 4 is basically circular. Since the area of the base mesa region corresponds to the junction area between the collector and the base, the negative feedback capacitance in the common-emitter base input type circuit is determined in proportion to this area. Therefore, the gain of the circuit can be increased by reducing the area ratio of the base mesa region, so that the output efficiency for power use can be improved.

The above-mentioned planar shape is based on a circular shape, and the above-mentioned object can be achieved even if it is not a perfect circular shape. In FIG. 17, since the base common wiring 10 is formed across the annular emitter layer 4, the collector common wiring 9 or the base common wiring 10 and the emitter common wiring 13
Are the same layer, the base layer 3 and the emitter layer 4
Becomes large, and it becomes difficult to reduce the collector-base junction area. In the present embodiment, such a problem is solved by forming the collector common wiring 9 or the base common wiring 10 and the emitter common wiring 13 in different layers.

As described above, the present invention has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Of course.

[0044]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, there is an effect that the emitter common line, the collector common line, and the base common line can be formed in different layers without the emitter lead-out line. (2) According to the present invention, the effect (1) has an effect that the collector common wiring and the base common wiring can be brought close to the base electrode. (3) According to the present invention, the effect (1) has an effect that an emitter common wiring can be arranged on the emitter electrode. (4) According to the present invention, the effects (2) and (3)
There is an effect that the occupied area of the unit finger can be reduced. (5) According to the present invention, the effect (4) has an effect that the manufacturing cost of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a partial plan view showing a main part of a conventional semiconductor device.

FIG. 2 is a longitudinal sectional view taken along lines aa and bb in FIG.

FIG. 3 is a longitudinal sectional view showing a main part of a conventional semiconductor device for each process.

FIG. 4 is a longitudinal sectional view showing a main part of a conventional semiconductor device for each process.

FIG. 5 is a longitudinal sectional view showing a main part of a conventional semiconductor device for each process.

FIG. 6 is a longitudinal sectional view showing a main part of a conventional semiconductor device for each process.

FIG. 7 is a longitudinal sectional view showing a main part of a conventional semiconductor device for each process.

FIG. 8 is a longitudinal sectional view showing a main part of a conventional semiconductor device for each process.

FIG. 9 is a partial plan view showing a main part of the semiconductor device according to one embodiment of the present invention;

FIG. 10 is a longitudinal sectional view taken along the line aa in FIG.

FIG. 11 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 12 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 13 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 14 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 15 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 16 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 17 is a partial plan view showing a main part of a semiconductor device according to another embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 2 ... Collector layer, 3 ... Base layer, 4 ...
Emitter layer, 5 ... Collector electrode, 6 ... Base electrode, 7 ...
Emitter electrodes, 8, 12 interlayer insulating film, 9 common collector wiring, 10 common base wiring, 11 emitter wiring, 13 common emitter wiring.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiaki Kitahara 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Yoshinori Imamura Josuihoncho, Kodaira-shi, Tokyo 5-20-1, Hitachi, Ltd. Semiconductor Group (72) Inventor Gen Nojima 5--20-1, Kamimizu Honcho, Kodaira, Tokyo F-term, Hitachi Semiconductor Group 4M104 AA05 AA09 BB09 BB16 BB28 CC01 DD06 DD16 DD43 DD65 DD68 EE08 EE14 FF03 GG06 GG18 HH00 5F003 BA92 BE05 BF06 BH01 BH94 BM02 5F033 GG02 HH13 HH20 HH28 JJ01 JJ13 JJ20 JJ28 KK01 Q04 UQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ either

Claims (5)

[Claims] 1. A semiconductor in which a plurality of semiconductor elements having a collector layer, a base layer, and an emitter layer formed on a semiconductor substrate are connected to each other by an emitter common line, and the collector layers are connected to each other by a common collector line. In the device, the collector common wiring is formed in a first interlayer insulating film covering the semiconductor substrate main surface, and a collector layer and a collector common wiring are connected through an opening provided in the first interlayer insulating film; The emitter common wiring is formed on the second interlayer insulating film covering the first interlayer insulating film and the collector common wiring, and is provided on the first interlayer insulating film and the second interlayer insulating film. A semiconductor device, wherein an emitter layer and an emitter common wiring are connected through an opening. 2. A semiconductor wherein a plurality of semiconductor elements having a collector layer, a base layer, and an emitter layer formed on a semiconductor substrate are connected to each other by an emitter common line, and the collector layers are connected to each other by a common collector line. In the device, the collector common wiring is formed in a first interlayer insulating film covering the semiconductor substrate main surface, and a collector layer and a collector common wiring are connected through an opening provided in the first interlayer insulating film; The semiconductor device, wherein the emitter common line is arranged so as to cross at least a part of a connection portion between the collector layer and the collector common line in a plane. 3. A semiconductor device according to claim 1, wherein a base common wiring connecting the base layers of the plurality of semiconductor elements to each other is formed in the first interlayer insulating film as a wiring layer of the same layer as the collector common wiring. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein the semiconductor device has an HBT. 5. The emitter layers of a plurality of semiconductor elements having a collector layer, a base layer, and an emitter layer formed on a semiconductor substrate are connected to each other by a common emitter wiring, and the collector layers are connected to each other by a common collector common wiring. In the method of manufacturing a semiconductor device, the collector common wiring and the base common wiring are formed in a first interlayer insulating film covering the semiconductor substrate main surface, and a collector layer is formed through an opening provided in the first interlayer insulating film. Connecting a base layer and a base common wiring to each other, and forming the emitter common wiring in the second interlayer insulating film covering the first interlayer insulating film and the collector common wiring. Connecting the emitter layer and the emitter common wiring through openings provided in the first interlayer insulating film and the second interlayer insulating film. The method of manufacturing a semiconductor device which is characterized in that.