JP2002246580A - Image sensor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a unit area of a photodiode with no degradation in integration degree. SOLUTION: At a unit pixel, an amplifying transistor 26 and a selecting transistor 28 are stacked over a reading transistor 24 and resetting transistor 22 with an interlayer insulating film 37 in between. So, with a prescribed design rule applied, an element separation film 32 is allowed to be away from the reading transistor 24. By reducing an occupation area of a transistor region like this way, an occupation area of a photodiode is increased with no degradation in integration degree for improved optical sensitivity characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a submicron C
CMOS using MOS (complementary metal oxide semiconductor) technology
The present invention relates to an image sensor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In addition to the existing image sensor market, a CMOS image sensor is a digital still camera (DS).
Demands in the fields of C), mobile phones, personal computers (PC), personal digital assistants (PDAs) and the like are rapidly expanding, and their technical importance is increasing.

The above-mentioned CMOS image sensor is a CCD (Charge Coup) which is widely used at present as an image sensor.
Compared to an image sensor (led Device), it has excellent features in single power supply, low voltage drive, and low power consumption. Further, the driving method is simple, and a versatile scanning method can be put to practical use, and the signal processing circuit can be integrated on a single chip, so that the product can be reduced in size and weight. Furthermore,
Since a CMOS technology similar to the logic process is used, a dedicated manufacturing line such as a CCD image sensor is not required even during manufacturing.

The above CMOS image sensor is also the above CCD.
In the same manner as described above, the number of pixels is increasing, and a configuration in which a photoelectric conversion element and a transistor are provided on the same substrate is employed. The signal charge generated by the photoelectric conversion element modulates the potential of the signal charge accumulating portion, and the potential modulates the amplifying transistor inside the pixel to provide an amplifying function inside the pixel.

[0005] As for the photodiode of the photoelectric conversion unit of the CMOS image sensor, similarly to the above-mentioned CCD,
In recent years, a structure embedded in a substrate and a structure in which a substrate surface portion of a photodiode is shielded with a P-type semiconductor layer is becoming mainstream. FIG. 6 shows a cross section of a unit pixel portion in a conventional CMOS image sensor. In FIG. 6, the unit pixel portion includes four transistors 4 to 7 and a photodiode 8 formed in a region defined by an element isolation region 3 in a P-type epitaxial layer 2 on a P ⁺ silicon substrate 1. You. The photodiode 8 includes a P-type semiconductor layer 9 on the substrate surface and an N ⁻
And an area 10. In addition, each transistor 4-7
Have N ⁺ regions 11 and 12 as source / drain regions.
Are formed.

In the CMOS image sensor having the above configuration,
As described above, since the surface of the photodiode 8 is shielded by the P-type semiconductor layer 9, it is possible to prevent a current generated from a defect level existing on the substrate surface of the photodiode 8 from flowing into the photodiode 8. As a result, defects such as white scratches can be greatly reduced.

Reference numeral 13 denotes a channel stopper region,
14 is a gate insulating film, 15 is a gate electrode,
16 is a CVD (Chemical Vapor Deposition) oxide film, and 17 is P
^- it is well.

[0008]

However, in the above-mentioned conventional CMOS image sensor, the buried photodiode 8 is formed in a certain area between the readout transistor 4 and the element isolation region 3, so that the buried photodiode 8 is formed. In order to increase the unit area of No. 8, there is a problem that the degree of integration must be reduced. In addition, since the area of the embedded photodiode 8 is reduced as the design rule is miniaturized, there is a problem that the sensitivity is significantly reduced with the miniaturization.

In order to increase the unit area without lowering the degree of integration, there has been proposed a photodiode formed along a wall surface of a trench formed in a semiconductor substrate.
(JP-A-2000-31455). However, in this case, there is a concern that junction leakage current may increase due to etching damage during the formation of the trench or stress due to an insulating film or the like filling the trench. Furthermore, it is difficult to accurately form a P / N / P junction on the concave / convex portion, and there is a problem in that when oblique ion implantation is used, the throughput is increased and the production efficiency is significantly deteriorated.

It is an object of the present invention to provide a CM capable of increasing the unit area of a photodiode using a predetermined design rule without lowering the degree of integration.
An object of the present invention is to provide an OS image sensor and a manufacturing method thereof.

[0011]

According to a first aspect of the present invention, a photoelectric conversion element formed on a semiconductor substrate and selection, amplification and reset of a signal charge generated by the photoelectric conversion element are performed. In the image sensor having at least three transistors as a unit pixel, each of the transistors includes a lower transistor formed on the semiconductor substrate and a semiconductor layer stacked on the lower transistor via an interlayer insulating film. It has a two-layer structure with the formed upper layer transistor.

According to the above configuration, in the unit pixel, at least three transistors for selecting, amplifying, and resetting the signal charge generated by the photoelectric conversion element include a lower transistor formed on the semiconductor substrate and a lower transistor formed on the semiconductor substrate. It has a two-layer structure with an upper layer transistor formed on the transistor. Therefore, if the same design rule as that of the conventional image sensor is applied, the area occupied by the transistor region is reduced, the area occupied by the photoelectric conversion element is increased, and the light sensitivity characteristics are improved. Alternatively, if the same light sensitivity characteristics as those of a conventional image sensor are obtained, the degree of integration is improved.

According to a first embodiment, in the image sensor of the first invention, an element isolation region for separating the unit pixels is formed on the semiconductor substrate, and the lower transistor A first channel region formed on the semiconductor substrate surface, a first gate insulating film formed on the semiconductor substrate including the first channel region, and a first channel region formed on the first gate insulating film. A first gate electrode; and a first high-concentration impurity region formed in the semiconductor substrate adjacent to the first channel region, wherein the upper transistor includes a second channel formed in the semiconductor layer. A second gate insulating film formed on the semiconductor layer including the second channel region; a second gate electrode formed on the second gate insulating film;
A second layer formed in the semiconductor layer adjacent to the channel region;
It has a high concentration impurity region, the photoelectric conversion element,
The photodiode is characterized by being formed at least on a junction of the first conductivity type and the second conductivity type on the semiconductor substrate.

According to this embodiment, the second channel region and the second high-concentration impurity region of the upper transistor are formed in the semiconductor layer laminated on the lower transistor via an interlayer insulating film. I have. Thus, a transistor having a two-layer structure can be easily formed by a conventional film forming technique, doping technique, photoetching technique, or the like.

According to a second embodiment, in the image sensor of the first embodiment, the photodiode is
A first conductive layer formed of a high-concentration impurity layer formed on the surface of the semiconductor substrate and not depleting the substrate interface;
A second conductive layer having a different conductivity type from the first conductive layer formed immediately below the conductive layer; and a third conductive layer having the same conductivity type as the first conductive layer formed immediately below the second conductive layer. It is characterized by being constituted.

According to this embodiment, the surface portion of the semiconductor substrate is shielded by the first conductive layer made of a high-concentration impurity layer that does not deplete the substrate interface. Therefore,
A current generated from a defect level existing on the surface of the semiconductor substrate is prevented from flowing into the photodiode, and defects such as white scratches are reduced.

According to a second aspect of the invention, there is provided a method of manufacturing an image sensor, comprising: forming an element isolation region formed of an insulating film on a surface of a semiconductor substrate; and forming a first channel region on the semiconductor substrate. Forming a first gate insulating film on the semiconductor substrate including the first channel region, forming a first gate electrode on the first gate insulating film, and adjoining the first channel region. Forming a first high-concentration impurity region in the semiconductor substrate, forming a semiconductor layer on the semiconductor substrate including the first gate electrode via an interlayer insulating film, and forming a second channel region in the semiconductor layer. Forming; forming a second gate insulating film on the semiconductor layer including the second channel region; forming a second gate electrode on the second gate insulating film; Adjacent to the region is characterized by comprising the step of forming a second high-concentration impurity regions in the semiconductor layer.

According to the above configuration, the transistor for selecting, amplifying, and resetting the signal charge generated by the photoelectric conversion element includes a lower transistor formed on the semiconductor substrate and an upper layer formed on the lower transistor. The transistor has a two-layer structure. Therefore, if the same design rule as that of the conventional image sensor is applied, the area occupied by the transistor region is reduced, the area occupied by the photoelectric conversion element is increased, and the light sensitivity characteristics are improved. Alternatively, if the same light sensitivity characteristics as those of a conventional image sensor are obtained, the degree of integration is improved.

In this case, the second channel region and the second high-concentration impurity region of the upper transistor are formed in the semiconductor layer laminated on the lower transistor via an interlayer insulating film. Thus, a transistor having a two-layer structure can be easily formed by a conventional film forming technique, doping technique, photoetching technique, or the like.

According to a third embodiment, in the method for manufacturing an image sensor according to the second invention, the formation of the second high-concentration impurity region in the semiconductor layer is performed by self-alignment with the second gate electrode. It is characteristically performed.

A fourth embodiment is directed to a method of manufacturing an image sensor according to the second invention, wherein the semiconductor layer and the second gate electrode are adjacent to at least one end of the second channel region. On the other hand, the method includes a step of forming a low concentration impurity region in a self-aligned manner.

According to these embodiments, the formation of the second high-concentration impurity region or the formation of the low-concentration impurity region in the semiconductor layer is performed in a self-aligned manner with respect to the second gate electrode. Thus, by using a relatively simple method, it is possible to easily cope with miniaturization.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a cross-sectional view illustrating a configuration of a unit pixel portion in a CMOS image sensor that is the image sensor according to the present embodiment. FIG. 2 is a circuit diagram of the unit pixel section.

As shown in FIG. 1, the CMOS image sensor according to the present embodiment mainly includes a semiconductor substrate 31.
An insulating film 32 for element isolation formed thereon, transistors 22 and 24 formed on the semiconductor substrate 31, a semiconductor layer 38 formed on the transistors 22 and 24 via an interlayer insulating film 37, It comprises thin film transistors 26 and 28 formed on the semiconductor layer 38 and a photodiode 25 formed on the surface of the semiconductor substrate 31 and having at least a junction of the first conductivity type and the second conductivity type.

The transistors 22 and 24 are
First channel region 33 formed in semiconductor substrate 31
, A first gate insulating film 34, and the first gate insulating film 3
4 and a first high-concentration impurity region 36 formed on the surface of the semiconductor substrate 31 so as to be adjacent to the first channel region 33. The thin film transistors 26 and 28 include a second channel region 38 a formed in the semiconductor layer 38, a second gate insulating film 39, a second gate electrode 40 formed on the second gate insulating film 39, A second high-concentration impurity region 38b is formed in the semiconductor layer 38 so as to be adjacent to the second channel region 38a.

The semiconductor substrate 31 is not particularly limited as long as it is a semiconductor substrate used in manufacturing a normal semiconductor device. For example, a semiconductor substrate of silicon, germanium, etc., SiC, GaAs, InGaAs, etc. And the like. Among them, a silicon substrate is preferable, and a substrate such as an SOI (silicon-on-insulator) substrate, a bonded SOI or SIMOX (separation by implanted oxygen) may be used.

The insulating film 32 formed on the semiconductor substrate 31 for element isolation may use either LOCOS (silicon selective oxidation) or a trench. However, the above LO
When COS is used, the oxide film thickness is 250 nm to 400 nm.
About nm is preferable. When the above-mentioned trench is used, the side wall may be formed to have a taper of about 75 to 85 degrees with respect to the substrate surface. Note that the depth of the trench can be appropriately adjusted depending on the element withstand voltage to be obtained and the like, and is preferably, for example, about 250 nm to 500 nm. After the trench is formed, it is desirable to perform oxidation of about 10 nm to 30 nm for the purpose of rounding the corners of the surface and the bottom to suppress the influence of electric field concentration and generation of crystal defects.

The first channel region 33 constitutes the read transistor 24 and the reset transistor 22, and is formed on the surface of the semiconductor substrate 31 on which the read transistor 24 and the reset transistor 22 are formed. The first channel region 33 can be appropriately set to a desired conductivity type by ion implantation or the like. Usually, the read transistor 24 and the reset transistor 2
In the case of No. 2, it is composed of an N-type depletion transistor having a negative threshold in order to increase the charge conduction efficiency.

The first gate insulating film 34 constitutes the read transistor 24 and the reset transistor 22 and is formed on the entire surface of the semiconductor substrate 31. Normal,
The gate insulating film can be formed by forming a material having a desired thickness by thermal oxidation or the like. The thickness at this time is desirably, for example, about 3 nm to 10 nm.

The first gate electrode 35 constitutes the read transistor 24 and the reset transistor 22 and is formed on the first gate insulating film 34 on the surface of the semiconductor substrate 31. The first gate electrode 35 may be formed of any material as long as it functions as an electrode.
It is desirable to form polysilicon having an impurity concentration on the order of E + 20 / cm ³ . The film thickness is
Although there is no particular limitation as long as it can function as a gate electrode, it is necessary to appropriately adjust the capacity of a transistor to be obtained, wiring resistance, and the like. First
The thickness of the gate electrode 35 is, for example, 100 nm to 20 nm.
About 0 nm is desirable.

It should be noted that a low-concentration impurity region may be formed between the first channel region 33 and the first high-concentration impurity region (source / drain region) 36 together with the formation of the sidewall by the CVD oxide film. it can.

The first high-concentration impurity region 36 includes the read transistor 24 and the reset transistor 2.
2 and the photodiode 25, and the source and the source of the read transistor 24 and the reset transistor 22
The drain region and the region of the photodiode 25 are formed respectively.

The semiconductor layer 38 on which the amplification transistor 26 and the selection transistor 28 are formed is formed via the interlayer insulating film 37 so as to be located on the read transistor 24 and the reset transistor 22. The thickness of the interlayer insulating film 37 is preferably, for example, about 100 nm to 300 nm. The semiconductor layer 38 may be formed of any material that functions as an active layer. For example, amorphous silicon is crystallized by annealing in nitrogen at 550 ° C. to 620 ° C. or laser annealing. A polysilicon layer is preferred. The thickness of the semiconductor layer 38 is preferably about 30 nm to 70 nm. The semiconductor layer 3
8, impurity doping corresponding to the threshold value of the transistor is performed in consideration of the performance and the like of the transistor. For example, in addition to ion implantation, impurity doping may be performed in-situ at the time of depositing amorphous silicon. An impurity concentration of about 1E + 17 / cm ^{3 to} 5E + 17 / cm ³ is appropriate. In addition, the semiconductor layer 38 includes
A second channel region 38a and a second high-concentration impurity region 38b serving as source / drain regions are formed.

The second gate insulating film 39 forms the amplification transistor 26 and the selection transistor 28,
It is formed so as to cover the surface of the semiconductor layer 38. The second gate insulating film 39 is usually formed mainly of a CVD silicon oxide film and has a desired thickness. The thickness of the second gate insulating film 39 is preferably, for example, about 20 nm to 50 nm. From the standpoint of electrical characteristics, in order to suppress leakage current, it is necessary to increase the film density under the highest possible temperature within a range that does not affect the characteristics of the underlying transistors (read transistor 24 and reset transistor 22). desirable. The temperature in that case is, for example, 700
C. to about 800.degree.

The second gate electrode 40 constitutes the amplification transistor 26 and the selection transistor 28,
It is formed on the gate insulating film 39. Second gate electrode 40
May be any material as long as it functions as an electrode, but is preferably formed of polysilicon having an impurity concentration on the order of about 1E + 20 / cm ³ . The thickness is not particularly limited as long as it can function as a gate electrode.
About 150 nm is desirable.

A second high-concentration impurity region 38b serving as a source / drain region of the amplification transistor 26 and the selection transistor 28 is formed in the semiconductor layer 38 using the second gate electrode 40 as a mask. The impurity concentration in that case is not particularly limited as long as the impurity concentration functions as a source / drain region, and 1E + 19
Impurity / cm ³ -1E + 20 impurities / cm ³ .

In the present CMOS image sensor, the transistors 22 and 24 formed on the semiconductor substrate 31 and the thin film transistors 26 and 28 formed on the semiconductor layer 38 on the transistors 22 and 24 have the first channel region 33 or It is desirable that the low concentration impurity region is formed adjacent to the second channel 38a. The impurity concentration in this low-concentration impurity region is not particularly limited as long as it can function as an offset region of the source / drain region.
An impurity concentration of about 8 / cm ^{3 to} 1E + 19 / cm ³ is desirable.

Further, the thin film transistors 26 and 28 formed in the semiconductor layer 38 may be constituted by a transistor having a bottom gate structure or a transistor having a double gate structure in addition to the transistor having a top gate structure as described above.

The photodiode 2 serving as a photoelectric conversion unit
Generally, an N ⁺ / P junction is widely used for 5, but its structure can be appropriately changed according to the purpose and device specifications. For example, a P ⁺ / N ⁻ / P structure in which the surface portion of the semiconductor substrate 31 is shielded by a P-type semiconductor layer may be used. In this case, by shielding with a P-type semiconductor layer, it is possible to prevent a current generated from a defect level existing on the substrate surface of the photodiode from flowing into the photodiode, and reduce defects such as white defects. You can do it.

Next, referring to FIG.
The operation of the MOS image sensor will be described. First,
The reset line 22 is turned on by setting the voltage level of the reset line 21 to “H”, and the charges remaining on the wiring are discharged to the drain line 23. After that, the reset transistor 22 is turned off. Next, by turning on the read transistor 24, the photodiode 25 is turned on.
The carriers generated by the photoelectric conversion flow into the gate of the amplification transistor 26. At this time, when the read transistor 24 is turned off, charges are accumulated in the gate of the amplification transistor 26, and the amplification transistor 26 is turned on. At the same time, when the level of the address line 27 is set to "H" to turn on the selection transistor 28, a signal is read out to the signal line 29.

Here, the semiconductor substrate 31 shown in FIG.
The transistors 22 and 24 formed above correspond to the read transistor 24 and the reset transistor 22 in FIG. Also, in FIG.
The thin film transistors 26 and 28 formed in the semiconductor layer 38 formed on the layers 2 and 24 via the interlayer insulating film 37 correspond to the amplification transistor 26 and the selection transistor 28 in FIG. Also, in FIG.
2 corresponds to the photodiode 25 in FIG.

Hereinafter, a method of manufacturing the CMOS image sensor having the above configuration will be described. As shown in FIG.
The MOS image sensor is formed in a P-type epitaxial layer 52 formed on a P ⁺ silicon substrate 51 having a specific resistance of 0.01 Ωcm to 0.1 Ωcm. The P-type epitaxial layer 52 has a specific resistance of 10 Ωcm to 20 Ωcm, and a thickness of 5 μm to 10 μm. P-type epitaxial layer 52
LOCOS device isolation film 53
It is formed with a thickness of 400 nm. Then, a silicon nitride film (not shown) used as a mask during selective oxidation and an insulating film
(Not shown) are sequentially removed.

Next, a silicon oxide film (not shown) serving as a mask at the time of implantation is formed on the surface of the P-type epitaxial layer 52.
Is formed to a thickness of 10 nm to 20 nm. Then, phosphorus ions of about 1E + 12 cm ^{−2 to} 1E + 13 cm ⁻² are implanted into a region where the read transistor 54 and the reset transistor 55 are to be formed to form first channel regions 56, 56. Next, after forming the first gate insulating films 57, 57 on the first channel regions 56, 56, the first gate electrodes 58, 57 are formed.
The polysilicon to be 58 is deposited by the CVD method.
Then, phosphorus is ion-implanted into the polysilicon to obtain 1E.
Doping is performed to an impurity concentration of about + 20 / cm ^{3 to} 5E + 20 / cm ³ . After that, the polysilicon is processed to form first gate electrodes 58, 58 of the read transistor 54 and the reset transistor 55, and a first CVD silicon oxide film is formed around the first gate electrodes 58, 58 by a known method. A sidewall 59 is formed.

Next, 1E + 15 at 40 keV to 90 keV is applied to the formation region of the read transistor 54 and the reset transistor 55 in the P-type epitaxial layer 52.
The first high-concentration impurity regions 60 serving as the source / drain are formed by ion-implanting a grinding element of about cm ^{−2 to} 5E + 15 cm ⁻² . Thereafter, a region of the photodiode 61 between the element isolation film 53 and the first channel region 56 of the read transistor 54 on the surface of the P-type epitaxial layer 52 is applied with 1E + 12 cm ^{−2 at} 100 keV to 200 keV.
The N ⁻ region 62 is formed by ion implantation of phosphorus of about 1E + 14 cm ⁻² . Further, 1E + at 20 keV to 50 keV
Boron fluoride (BF ₂ ) of about 13 cm ^{−2 to} 1E + 15 cm ⁻² is ion-implanted to form a P ⁺ region 63 on the surface of the N ⁻ region 62. Incidentally, 64 is a channel stopper region.

Next, as shown in FIG. 4, a second C film having a thickness of about 100 to 300 nm is formed on the entire surface as an interlayer insulating film 65.
A VD silicon oxide film is formed. After that, amorphous silicon is deposited in a thickness of about 30 nm to 70 nm by a CVD method as a semiconductor layer 68 to be an active layer of the amplification transistor 66 and the selection transistor 67, and nitrogen at 550 ° C. to 620 ° C. using a diffusion furnace. A polysilicon layer is formed by annealing in the inside or laser annealing. Then, the semiconductor layer (active layer) 68 is formed by photoetching, leaving a region located above the read transistor 54 and the reset transistor 55. The semiconductor layer 68 is doped with impurities corresponding to the threshold value of the transistor. In this case, the impurity doping is performed by using ion implantation or by depositing amorphous silicon.
This is performed by using in-situ doping. The second channel region 68a has an impurity concentration of, for example, about 1E + 17 / cm ^{3 to} 5E + 17 / cm ^3.
Is formed in the semiconductor layer 68.

Thereafter, a thickness of 20 nm to 5 nm is applied to cover the surface of the semiconductor layer 68 including the second channel region 68a.
A third gate oxide film 69 is formed by depositing a third CVD silicon oxide film with a thickness of about 0 nm. At this time, in order to reduce the interface state density between the second gate insulating film 69 and the polysilicon, before depositing the third CVD silicon oxide film, the surface of the semiconductor layer 68 made of polysilicon is reduced to 4 nm or more.
Oxidation of about 10 nm may be used as a part of the second gate insulating film 69. Then, after depositing a second polysilicon to a thickness of about 100 nm to 150 nm, the second polysilicon above the phosphorus of about 1E + 15cm ^-2 ~1E + 16cm ^-2 by ion implantation 1E + 20 atoms / cm ³ ~5E + 20 pieces
The impurity is doped to have an impurity concentration of about / cm ³ . After that, the second polysilicon is photoetched to form second gate electrodes 70,70.

Next, using the second gate electrodes 70, 70 as a mask, 1E + 13 cm ⁻² to 1E
About 14 cm ⁻² of phosphorus is ion-implanted to form a semiconductor layer 68.
Inside, a low-concentration impurity region 68b is formed adjacent to the second channel region 68a.

Next, as shown in FIG. 5, after forming a mask (not shown) with a photoresist on the low concentration impurity region 68b on one side which is to be the drain region of the amplification transistor 66 and the selection transistor 67, , Semiconductor layer 6
8 is ion-implanted with phosphorus of about 1E + 14 cm ⁻² to 1E + 15 cm ⁻² , and the second channel region 6 is formed in the semiconductor layer 68.
A second high-concentration impurity region 68c serving as a source region is formed adjacent to 8a. Thus, the low-concentration impurity region 68b can be formed in a self-aligned manner on the drain region side of the transistors 66 and 67. In forming the low-concentration impurity region 68b and the second high-concentration impurity region 68c, an impurity serving as an N-type dopant such as arsenic may be used instead of the phosphorus. Further, the low-concentration impurity region 68b may be appropriately formed according to the characteristics of a desired transistor or the like.

Next, a fourth CVD silicon oxide film 71 having a thickness of about 500 nm to 1000 nm is planarized over the entire surface including the above-mentioned amplification transistor 66 and the selection transistor 67. After that, a contact hole 72 is opened in the silicon oxide film 71, a metal layer such as aluminum is laminated on the entire surface, and then photoetching is performed to form a wiring 73.

As described above, in the unit pixel portion,
A CMOS image sensor having a structure in which the amplification transistor 66 and the selection transistor 67 are stacked on the reading transistor 54 and the reset transistor 55 via the interlayer insulating film 65 is formed.

As described above, in the present embodiment, the amplification transistors 26 and 66 are provided in the unit pixel portion.
And the select transistors 28 and 67 are connected to the interlayer insulating film 37,
It is arranged so as to be stacked on the read transistors 24 and 54 and the reset transistors 22 and 55 via 65. Therefore, when a predetermined design rule is applied, the element isolation films 32 and 53 and the read transistor 2
4 and 54 can be made wider than a conventional CMOS image sensor in which the read transistor 4, reset transistor 7, amplification transistor 5, and selection transistor 6 are arranged in the same layer as shown in FIG. As a result, the areas of the photodiodes 25 and 61 formed between the element isolation films 32 and 53 and the read transistors 24 and 54 can be widened, and the sensitivity can be improved.

That is, according to the present embodiment, if the same design rule as that of the conventional CMOS image sensor is applied, the area occupied by the transistor region can be reduced and the area occupied by the photodiode can be increased.
Light sensitivity characteristics can be improved. In addition, conventional CM
If the same light sensitivity characteristic as that of the OS image sensor is obtained, the degree of integration can be increased.

In this embodiment, the amplification transistors 26 and 66 and the selection transistors 28 and 6 are used.
The source / drain region 7 is composed of read transistors 24 and 54 and a reset transistor 2 located at the lower stage.
The interlayer insulating films 37, 65 formed by the presence of 2,55 are formed in the inclined portions at the steps. Therefore, there is an effect that the electrolytic concentration at the boundary between the source / drain region and the second channel region 38a, 68a is easily alleviated.

The layout of the above-mentioned four transistors can be freely set up and down or in combination as needed. That is, although the photodiodes 25 and 61 in the above embodiment are of the P / N / P junction type, they may be of the N / P junction type. In that case, the reading transistors 24 and 54 can be omitted. That is, in the present invention, a structure in which at least three transistors are stacked in a unit pixel may be used.

Although the preferred embodiment of the present invention has been described in the above embodiment, the present invention is not limited to the above embodiment and may be modified as appropriate. For example, formation of contact holes connecting the upper and lower transistors, annealing in a hydrogen atmosphere to improve the switching characteristics of the thin film transistors 26, 66; 28, 67 having the active layers 38, 68 made of polysilicon,
Annealing in a nitrogen atmosphere after ion implantation for suppressing junction leakage due to crystal defects or the like can be added.

[0056]

As apparent from the above description, the image sensor according to the first aspect of the present invention has at least three transistors for selecting, amplifying and resetting signal charges generated by a photoelectric conversion element, formed on the semiconductor substrate. The same design rules as the conventional image sensor are applied because the transistor has a two-layer structure consisting of a lower-layer transistor and an upper-layer transistor formed on a semiconductor layer stacked on the lower-layer transistor via an interlayer insulating film. Then, the area occupied by the transistor region can be reduced, the area occupied by the photoelectric conversion element can be increased, and the light sensitivity characteristics can be improved. Alternatively, if the same light sensitivity characteristics as those of a conventional image sensor are obtained, the degree of integration can be improved.

The image sensor of the first embodiment is
The lower layer transistor includes a first channel region formed on the semiconductor substrate surface, a first gate insulating film formed on the semiconductor substrate including the first channel region, and a first gate insulating film formed on the first gate insulating film. And a first high-concentration impurity region formed in the semiconductor substrate adjacent to the first channel region. The upper transistor is formed in the semiconductor layer. The second
A channel region, a second gate insulating film formed on the semiconductor layer including the second channel region, a second gate electrode formed on the second gate insulating film, adjacent to the second channel region. Then, since the semiconductor layer has the second high-concentration impurity region formed in the semiconductor layer, the transistor having the two-layer structure can be easily formed by a conventional film forming technique, doping technique, photo etching technique, or the like. be able to.

The image sensor according to the second embodiment has
A first conductive layer formed of a high-concentration impurity layer formed on a surface of the semiconductor substrate and not depleting a substrate interface; and the first conductive layer formed immediately below the first conductive layer. Since it is composed of a second conductive layer of a different conductivity type and a third conductive layer of the same conductivity type as the first conductive layer formed immediately below the second conductive layer, the second conductive layer is formed from a defect level existing on the surface of the semiconductor substrate. Can be prevented from flowing into the photodiode, and defects such as white scratches can be reduced.

Further, in the method of manufacturing an image sensor according to the second invention, a first channel region, a first gate insulating film, a first gate electrode, and a first high-concentration impurity region are formed on a semiconductor substrate. A semiconductor layer is formed on the semiconductor substrate including the one gate electrode via an interlayer insulating film, and a second channel region, a second gate insulating film, a second gate electrode, and a second high-concentration impurity region are formed on the semiconductor layer. Therefore, a transistor for selecting, amplifying, and resetting the signal charge generated by the photoelectric conversion element is divided into a lower transistor formed on the semiconductor substrate and an upper transistor formed on the lower transistor. Can have a layered structure.

Therefore, if the same design rule as that of the conventional image sensor is applied, the area occupied by the transistor region can be reduced, the area occupied by the photoelectric conversion element can be increased, and the light sensitivity characteristics can be improved. Alternatively, if the same light sensitivity characteristics as those of a conventional image sensor are obtained, the degree of integration can be improved.

Further, since the second channel region and the second high-concentration impurity region of the upper transistor are formed in the semiconductor layer laminated on the lower transistor via an interlayer insulating film, a two-layer structure is provided. The transistor can be easily formed by a conventional film forming technique, doping technique, photo etching technique and the like.

In the method of manufacturing an image sensor according to the third embodiment, the second high-concentration impurity region is formed in the semiconductor layer in a self-aligned manner with respect to the second gate electrode. In the method of manufacturing an image sensor according to the embodiment, a low-concentration impurity region is formed in the semiconductor layer in a self-aligned manner with respect to the second gate electrode, at least adjacent to at least one side end of the second channel region. By using a relatively simple method for forming the second high-concentration impurity region and the low-concentration impurity region, it is possible to easily cope with miniaturization.

[Brief description of the drawings]

FIG. 1 shows a CMOS as an image sensor according to the present invention.
FIG. 3 is a cross-sectional view of a unit pixel unit in the image sensor.

FIG. 2 is a circuit diagram of a unit pixel unit shown in FIG.

3 is a cross-sectional view of the CMOS image sensor shown in FIG. 1 in a certain manufacturing process.

FIG. 4 is a sectional view in the manufacturing process following FIG. 3;

FIG. 5 is a sectional view in the manufacturing process following FIG. 4;

FIG. 6 is a sectional view of a unit pixel portion in a conventional CMOS image sensor.

[Explanation of symbols]

22, 55 ... reset transistor, 23 ... drain line, 24, 54 ... readout transistor, 25, 61 ... photodiode, 26, 66 ... amplification transistor, 28, 67 ... selection transistor, 29 ... signal line, 31 ... semiconductor substrate, 32: insulating film for element isolation, 33, 56: first channel region, 34, 57: first gate insulating film, 35, 58: first gate electrode, 36, 60: first high-concentration impurity region, 37, 65 ... interlayer insulating film, 38,68 ... semiconductor layer, 38a, 68a ... second channel region, 38b, 68c ... second high concentration impurity region, 39,69 ... second gate insulating film, 40,70 ... second gate electrode , 51 ... ^{P +} silicon substrate, 52 ... P-type epitaxial layer, 53 ... isolation layer, 59 ... side wall, 62 ... N ^- region, 63 ... ^{P +} regions, 68b ... low concentration impurity Frequency, 71 ... silicon oxide film, 72 ... contact hole 73 ... wiring.

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Claims (13)

[Claims] A photoelectric conversion element formed on a semiconductor substrate and a signal charge generated by the photoelectric conversion element;
In an image sensor having at least three transistors for performing amplification and reset as a unit pixel, the transistor is laminated on a lower transistor formed on the semiconductor substrate via an interlayer insulating film on the lower transistor. An image sensor having a two-layer structure with an upper transistor formed in a semiconductor layer. 2. The image sensor according to claim 1, wherein the upper transistor is an amplification transistor and a selection transistor, and the lower transistor is a reset transistor. 3. The image sensor according to claim 2, wherein a readout transistor is added as the lower layer transistor. 4. The image sensor according to claim 1, wherein an element isolation region for separating the unit pixels is formed on the semiconductor substrate, and the lower transistor is formed on the surface of the semiconductor substrate. A first channel region formed on the first substrate, a first gate insulating film formed on the semiconductor substrate including the first channel region, a first gate electrode formed on the first gate insulating film, A first high-concentration impurity region formed in the semiconductor substrate adjacent to the first channel region, wherein the upper transistor includes a second channel region formed in the semiconductor layer; A second gate insulating film formed on the semiconductor layer including the region,
A second gate electrode formed on a gate insulating film; and a second high-concentration impurity region formed in the semiconductor layer adjacent to the second channel region. An image sensor comprising a photodiode formed on a substrate and having at least a junction of a first conductivity type and a second conductivity type. 5. The image sensor according to claim 4, further comprising a low-concentration impurity region formed in said semiconductor substrate adjacent to at least one side end of said first channel region. . 6. The image sensor according to claim 4, further comprising a low-concentration impurity region formed in said semiconductor layer adjacent to at least one side end of said second channel region. . 7. The image sensor according to claim 4, wherein the photodiode is formed on a surface of the semiconductor substrate and includes a first conductive layer including a high-concentration impurity layer that does not deplete a substrate interface; A second conductive layer having a different conductivity type from the first conductive layer formed immediately below the conductive layer; and a third conductive layer having the same conductivity type as the first conductive layer formed immediately below the second conductive layer. An image sensor, comprising: 8. A step of forming an element isolation region made of an insulating film on a surface of the semiconductor substrate, a step of forming a first channel region on the semiconductor substrate, and a step of forming a first channel region on the semiconductor substrate including the first channel region. Forming a first gate insulating film; forming a first gate electrode on the first gate insulating film; forming a first gate electrode on the semiconductor substrate adjacent to the first channel region;
Forming a high concentration impurity region, forming a semiconductor layer on the semiconductor substrate including the first gate electrode via an interlayer insulating film, and forming a second channel region in the semiconductor layer. Forming a second gate insulating film on the semiconductor layer including the second channel region, forming a second gate electrode on the second gate insulating film, adjoining the second channel region; Forming a second high-concentration impurity region in the semiconductor layer by the method described above. 9. The method for manufacturing an image sensor according to claim 8, further comprising a step of forming a photodiode having at least a junction between the first conductivity type and the second conductivity type on the surface of the semiconductor substrate. A method for manufacturing an image sensor, comprising: 10. The method for manufacturing an image sensor according to claim 8, wherein the step of forming the semiconductor layer comprises: depositing an amorphous silicon layer on the interlayer insulating film; A method for manufacturing an image sensor, comprising a step of crystallizing by phase growth. 11. The method for manufacturing an image sensor according to claim 8, wherein the step of forming the semiconductor layer includes a step of depositing an amorphous silicon layer on the interlayer insulating film and then crystallizing the layer by laser annealing. A method of manufacturing an image sensor. 12. The method for manufacturing an image sensor according to claim 8, wherein forming the second high-concentration impurity region in the semiconductor layer comprises:
A method for manufacturing an image sensor, wherein the method is performed in a self-aligned manner with respect to the second gate electrode. 13. The method for manufacturing an image sensor according to claim 8, wherein at least one side edge of the second channel region is adjacent to the second channel region.
Forming a low-concentration impurity region in the semiconductor layer in a self-aligned manner with respect to the second gate electrode.