JP2002246558A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein high precision can be simply and effectively realized when a viahole is formed for connecting a lower wiring layer connected with a lower electrode layer of a capacitance element of an MIMC structure with an upper wiring layer. SOLUTION: A TiN layer 18, a Ta2O5 layer 20 and a TiN layer 22 which are turned into a lower electrode, a dielectrics layer and an upper electrode of the capacitance element later, respectively, are deposited on a first lower wiring layer 12a via an SiO2 interlayer insulating film 14, and a TiN/Ta2O5/TiN laminated layer 24 is formed. After that, photoresist is spread on the whole surface of base substance by using a photolithography technique. Irradiation of an exposure light whose wavelength is 193 nm (ArF) is performed, and a resist pattern 28 wherein an aperture 26a for a viahole whose diameter is 0.2-2.0 μm is formed is formed above the first lower wiring layer 12a. At this time, the TiN/Ta2O5/TiN laminated layer 24 is made to act as a reflection protecting film whose reflectance for the exposure light is less than 10%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for forming a capacitor having a MIMC structure.

[0002]

2. Description of the Related Art Conventionally, a capacitive element formed on a Si (silicon) substrate has a MISC (Metal-Insulator-type) using a low-resistance diffusion layer formed in the Si substrate as a lower electrode layer.
Generally, a semiconductor capacitor (MIMC) (Metal-Insulator-Metal Capacitor) structure using a conductive layer formed on an insulating film provided on a Si substrate as a lower electrode layer is used. Considering the parasitic capacitance between these capacitors and the Si substrate, in the case of the MISC structure, the junction capacitance between the diffusion layer and the Si substrate becomes dominant, and the MIM
In the case of the C structure, the capacitance of the insulating film between the Si substrate and the conductive layer becomes dominant. For this reason, in general, the capacitance element having the MIMC structure can reduce the parasitic capacitance, and is particularly suitable for high frequency applications. In this manner, when a capacitive element having high capacitance, low parasitic capacitance, and low parasitic resistance is manufactured, the MIM
C structure is adopted.

By the way, in such a method of manufacturing a capacitor having a MIMC structure, a lower wiring layer connected to a conductive layer (hereinafter, referred to as a “lower electrode layer”) serving as a lower electrode of the capacitor is formed. When forming a via hole (Via Hole) for connecting to the upper wiring layer formed on the lower wiring layer via the interlayer insulating film, after applying a resist on the interlayer insulating film using a photolithography technique, The resist is irradiated with exposure light of a predetermined wavelength to form a resist pattern having an opening for a via hole.

However, when exposure is performed with exposure light having a predetermined wavelength, halation occurs due to irregular reflection of the lower wiring layer, and the interlayer insulating film is subjected to a smoothing process. Differences in the thickness of the photoresist,
There is a problem that the standing wave effect and the bulk effect in the exposure process are increased, the accuracy of the opening for the via hole in the resist pattern is deteriorated, and the accuracy of the via hole formed using this resist pattern is also deteriorated. there were.

In order to improve such a problem, there has been proposed a method using a photoresist containing a dye having a certain absorptivity for a predetermined exposure wavelength. However, this method has a limitation in improving the resolution of the photoresist, and is often not suitable for fine processing.

Further, a method has been proposed in which a metal compound having a high absorptance with respect to a predetermined exposure wavelength is deposited on the upper surface of the lower wiring layer to solve these problems.
However, in this case, there is a problem that although it is effective for irregular reflection from the upper surface of the lower wiring layer, it is not effective for irregular reflection from the side wall surface.

[0007] In addition, in the upper or lower layer of the photoresist,
The so-called TARC (Top Anti-Reflective Co.), which forms a film of a material that suppresses the reflection of exposure light of a predetermined wavelength,
ating) or BARC (Bottom Anti-Reflective Coatin)
Methods such as g) have also been proposed. But in that case,
After the exposure step, it is necessary to remove these layers, resulting in a problem that the number of steps is increased.

[0008]

As described above, in the conventional method of manufacturing a capacitor having the MIMC structure, the connection between the lower wiring layer and the upper wiring layer connected to the lower electrode layer of the capacitor is not required. When forming a via hole, there is a problem that the precision of the via hole opening of the resist pattern deteriorates, and although various proposals have been made for solving the problem, a simple and effective solution has not yet been shown. Had not been.

Accordingly, the present invention has been made in view of the above circumstances, and forms a via hole for connection between a lower wiring layer connected to a lower electrode layer of a capacitive element having an MIMC structure and an upper wiring layer. In this case, it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of easily and effectively realizing high precision.

[0010]

The above object is achieved by a method of manufacturing a semiconductor device according to the present invention described below. In other words, the method of manufacturing a semiconductor device according to claim 1 is a method of manufacturing a semiconductor device having a capacitive element in which an upper electrode layer is formed on a lower electrode layer via a dielectric layer, After forming an insulating film on the entire surface of the substrate on which the layer is formed, selectively removing the insulating film by etching to form an opening for exposing the surface of the lower wiring layer; and A second step of forming a laminated film in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated, and connecting the lower electrode layer of the laminated film to a lower wiring layer through an opening; Using technology, after applying a resist on the laminated film, irradiate exposure light of a predetermined wavelength,
A third step of forming a resist pattern having an opening for a via hole, and using the resist pattern as a mask, selectively removing the laminated film and the insulating film by etching to form a via hole exposing the surface of the lower wiring layer; And forming a conductive layer on the entire surface of the substrate, patterning the conductive layer and the laminated film into a predetermined shape, and forming a conductive layer on the lower electrode layer connected to the lower wiring layer via a dielectric layer. While forming a capacitive element in which the upper electrode layer is laminated,
Forming a first upper wiring layer made of a conductive layer connected to the upper electrode layer of the capacitive element and forming a second upper wiring layer made of a conductive layer connected to the lower wiring layer via a via hole; And a step.

As described above, in the method of manufacturing a semiconductor device according to the first aspect, when forming the via hole for connecting the lower wiring layer connected to the lower electrode layer of the capacitive element and the second upper wiring layer, After forming a laminated film in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated on the lower wiring layer via an insulating film, a resist is applied on the laminated film using a photolithography technique. Then, a lower electrode layer, a dielectric layer, and an upper electrode layer are formed on the insulating film above the lower wiring layer by irradiating exposure light of a predetermined wavelength to form a resist pattern having an opening for a via hole. In the state in which the laminated film composed of is formed, the resist applied on the laminated film is irradiated with exposure light of a predetermined wavelength to open an opening for a via hole. Predetermined Controlling the reflectance for the exposure light wavelength, the occurrence of standing waves in the halation occurs and the photoresist due to the diffused reflection top and side wall surfaces of the lower wiring layer lying below the laminated film is controlled. Accordingly, the opening accuracy of the via hole opening of the resist pattern is controlled, and the opening accuracy of the via hole itself is controlled.

Further, in this case, the laminated film for controlling the reflectance with respect to the exposure light having a predetermined wavelength comprises a lower electrode layer, a dielectric layer, and an upper electrode layer for forming a capacitive element. Since it is not necessary to separately form the above film, complication of the manufacturing process is suppressed.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a capacitive element having an upper electrode layer formed on a lower electrode layer via a dielectric layer. Forming an insulating film over the entire surface of the substrate on which the lower wiring layer is formed, and selectively removing the insulating film by etching to form an opening for exposing the surface of the lower wiring layer.
Step 1 and forming a laminated film in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated on the entire surface of the substrate, and connecting the lower electrode layer of the laminated film to the lower wiring layer through the opening. A second step of forming a resist pattern by coating a resist on the laminated film using photolithography technology and then irradiating exposure light of a predetermined wavelength to form a resist pattern having an opening for a via hole. A fourth step of selectively etching and removing the laminated film and the insulating film using the resist pattern as a mask to form a via hole exposing the surface of the lower wiring layer; After forming the first conductive layer, a fifth step of etching back the first conductive layer to form a plug layer made of the first conductive layer filling the via hole, and forming a second conductive layer on the entire surface of the substrate After this, this second The electric layer and the laminated film are patterned into a predetermined shape to form a capacitive element in which an upper electrode layer is laminated via a dielectric layer on a lower electrode layer connected to a lower wiring layer, and the capacitive element is formed. Forming a first upper wiring layer made of a second conductive layer connected to the upper electrode layer of the first and second upper wirings made of a second conductive layer connected to the lower wiring layer via a plug layer in a via hole And a sixth step of forming a layer.

Thus, in the semiconductor device according to the second aspect, in the same manner as in the first aspect, the lower wiring layer connected to the lower electrode layer of the capacitor and the second upper wiring layer are connected. When forming a via hole, after forming a laminated film in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated on the lower wiring layer via an insulating film, using photolithography technology, By applying a resist on the laminated film, irradiating exposure light of a predetermined wavelength, and forming a resist pattern having an opening for a via hole, the same effect as in the case of claim 1 is exerted. The opening accuracy of the via hole opening of the resist pattern is controlled, and the opening accuracy of the via hole itself is controlled.

Also in this case, the laminated film for controlling the reflectance with respect to the exposure light having a predetermined wavelength comprises a lower electrode layer, a dielectric layer, and an upper electrode layer for forming a capacitive element. Since it is not necessary to separately form a film for use, the production process is not complicated.

After forming a via hole for exposing the surface of the lower wiring layer, a plug layer made of a first conductive layer filling the via hole is formed, and connected to the lower wiring layer via the plug layer in the via hole. Forming a second upper wiring layer made of a second conductive layer to form a via hole for exposing the surface of the lower wiring layer, thereby forming a via hole through the conductive layer formed on the entire surface of the base body. In comparison with the case where the second upper wiring layer made of a conductive layer connected to the lower wiring layer through the via hole and buried through the via hole is formed, the via hole can be made finer than in the case of the first aspect.

In the semiconductor device according to claim 1 or 2, the laminated film is exposed to the light of the predetermined wavelength when forming a resist pattern having an opening for a via hole in the third step. It is preferable that the film be an antireflection film for light (claim 3). In this case, using a photolithography technique, a resist is applied to a laminated film in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated, and is irradiated with exposure light of a predetermined wavelength to form an opening for a via hole. When a resist pattern having an opening is formed, the laminated film serves as an anti-reflection film for exposure light having a predetermined wavelength, so that irregular reflection due to the upper surface and side wall surface of the lower wiring layer existing below the laminated film. The generation of halation and the generation of standing waves in the photoresist due to the above are suppressed. Therefore, the opening accuracy of the via hole opening of the resist pattern can be improved, and the via hole itself can be opened with high accuracy, which contributes to miniaturization and high reliability of the capacitive element.

In the method of manufacturing a semiconductor device according to the third aspect, it is preferable that the reflectance of the laminated film with respect to the exposure light having the predetermined wavelength is less than 10% (claim 4). In this case, since the laminated film has a reflectance of less than 10% for exposure light of a predetermined wavelength, the laminated film sufficiently functions as an antireflection film for exposure light of a predetermined wavelength. The same effect as in the case of item 3 is exhibited, the opening accuracy of the opening for the via hole of the resist pattern can be enhanced, and the via hole itself can be opened with high accuracy, and the miniaturization and high reliability of the capacitor element can be achieved. To contribute.

Further, in the method of manufacturing a semiconductor device according to the third aspect, it is preferable that the lower electrode layer constituting the laminated film serving as an antireflection film for exposure light of a predetermined wavelength is made of TiN. 5) It is preferable that the dielectric layer also constituting the laminated film is made of Ta ₂ O ₅ (Claim 6), and the upper electrode layer also constituting the laminated film is made of T
It is preferable that it consists of iN (claim 7).
In each of these cases, g-line 436 nm, i-line 365 nm, KrF 248 nm, ArF 193 n
Other exposure light wavelength, such as m, 157 nm of F ₂ that has been proposed as next-generation technology, effective functions as an antireflection film for the wavelength of the exposure light and EB of 13nm, etc. EUV (electron beam) It is exhibited in.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. (First Embodiment) FIGS. 1 to 7 show a first embodiment of the present invention.
FIG. 10 is a process cross-sectional view for describing the method of manufacturing the capacitive element having the MIMC structure according to the embodiment.

First, as shown in FIG.
After forming a metal layer mainly composed of an Al (aluminum) alloy to a thickness of about 300 to 1000 nm on an insulator layer 10 provided on a semiconductor substrate (not shown) such as a substrate, photolithography and RIE (Reactive Ion Etchi
Then, the metal layer is selectively patterned by using a reactive ion etching method to form first and second lower wiring layers 12a and 12b. Subsequently, for example, plasma C
VD (Chemical Vapor Deposition)
After depositing an SiO ₂ insulating film over the entire surface of the substrate using, for example, a smoothing process is further performed to form the SiO ₂ interlayer insulating film 14.

Then, as shown in FIG. 2, the SiO ₂ interlayer insulating film 14 on the first lower wiring layer 12a in the region where the capacitive element is to be formed is selectively etched by photolithography and RIE. , First lower wiring layer 12
a Opening 16 exposing the surface is formed.

Next, as shown in FIG.
Then, using a sputtering method or a CVD method,
The thickness of the TiN layer 18 serving as the lower electrode layer is about 5 to 100 nm.
Deposits every time. Also, a sputtering method is
Alternatively, using a CVD method, Ta as a dielectric layer₂O₅
The layer 20 is deposited to a thickness of about 10 to 100 nm. Furthermore,
This Ta₂O₅Sputtering or CVD on the layer 20
To form a TiN layer 2 which will later become the upper electrode layer of the capacitive element.
2 is deposited to a thickness of about 5 to 100 nm. Thus, the thickness
5-100 nm / 10-100 nm / 5-100 nm
TiN / Ta degree₂O₅/ TiN laminated film 24 is formed
I do. Here, this TiN / Ta ₂O₅/ Ti
The Ti layer 18 of the N laminated film 24 is
Is connected to the lower wiring layer 12a.

Next, as shown in FIG. 4, a photoresist is applied to the entire surface of the substrate using a photolithography technique, and then, for example, exposure light having a wavelength of 193 nm (ArF) is applied through a photomask on which a predetermined pattern is drawn. And further developed to obtain first and second lower wiring layers 12a,
A resist pattern 28 having via holes 26a and 26b having a diameter of, for example, 0.2 to 2.0 μm is formed at a predetermined position above 12b.

At the time of this exposure, a wavelength of 193 nm was used.
TiN / Ta ₂ O ₅ / T for exposure light of (ArF)
The reflectance of the iN laminated film 24 becomes less than 10%. That is,
The TiN / Ta ₂ O ₅ / TiN laminated film 24 has a wavelength of 193
It functions as an antireflection film for exposure light of nm (ArF). Accordingly, at the time of this exposure, the occurrence of halation and the occurrence of standing waves in the photoresist due to irregular reflection by the upper surface and the side wall surface of the first and second lower wiring layers 12a and 12b are suppressed. Since the effects of halation and standing wave effects are almost eliminated, the openings 26a and 26b for via holes in the resist pattern 28 are formed with high precision.

Next, as shown in FIG.
Using the resist pattern 28 as a mask and
TiN / T exposed in the openings 26a and 26b for the tool
a₂ O₅/ TiN laminated film 24 is selectively removed by etching.
And then continuously SiO₂Select interlayer insulating film 14
The first and second lower wiring layers 12 are removed by etching.
via holes 30a, 30b reaching the upper surfaces of
Open. After that, the resist pattern 28 is peeled off.
The size of these via holes 30a and 30b will be described later.
A metal layer mainly composed of Al alloy on the entire surface of the substrate
In this case, the metal layer is good in the via holes 30a and 30b.
The diameter should be small enough to be embedded in

Next, as shown in FIG.
On the entire surface of the substrate where the Ta ₂ O ₅ / TiN laminated film 24 is exposed and the via holes 30a and 30b are formed, a metal layer 32 mainly composed of an Al alloy is formed to a thickness of 300 to 1000 nm.
Formed to the extent.

Next, as shown in FIG.
By using lithography technology and RIE method,
Metal layer 32 as main component and TiN / Ta₂O₅/ T
The iN stacked film 24 is selectively patterned. Like this
The lower portion of the TiN connected to the first lower wiring layer 12a.
Electrode layer 18a, Ta on this TiN lower electrode layer 18a
₂O₅Dielectric layer 20a and this Ta₂ O₅Dielectric
Capacitive element comprising TiN upper electrode layer 22a on layer 20a
34, ie, the TiN upper electrode layer 22a and the TiN lower electrode layer
18a and Ta₂O₅With the dielectric layer 20a interposed
Is formed.

At the same time, a first upper wiring layer 32a connected to the TiN upper electrode layer 22a of the capacitive element 34, a second upper wiring layer 32b connected to the first lower wiring layer 12a via the via hole 30a, and Third upper wiring layer 3 connected to second lower wiring layer 12b via via hole 30b
2c are respectively formed. That is, TiN of the capacitive element 34
First upper wiring layer 32a connected to upper electrode layer 22a
And a second upper wiring layer 32 connected to the TiN lower electrode layer 18a of the capacitive element 34 via the first lower wiring layer 12a.
and b, respectively, to complete the capacitive element 34.

According to this embodiment as described above, the first and second lower wiring layer 12a made of a metal layer mainly composed of Al alloy, on the 12b, through the SiO ₂ interlayer insulation film 14, A thickness of 5 to 100, which will later become the lower electrode layer of the capacitor
nm and a thickness of 10 nm as a dielectric layer.
After forming a TiN / Ta ₂ O ₅ / TiN laminated film 24 in which a Ta ₂ O ₅ layer 20 of about 100 nm and a TiN layer 22 of about 5 to 100 nm thickness which will later become an upper electrode layer of the capacitive element are sequentially deposited Then, a photoresist is applied to the entire surface of the substrate by using a photolithography technique.
Irradiation with exposure light of 93 nm (ArF) is performed to
In a predetermined position above the lower wiring layers 12a and 12b, for example, an opening 26a for a via hole having a diameter of 0.2 to 2.0 μm,
By forming the resist pattern 28 having an opening 26b, TiN functioning as an antireflection film having a reflectance of less than 10% with respect to exposure light having a wavelength of 193 nm (ArF).
Since the photoresist on the / Ta ₂ O ₅ / TiN laminated film 24 is exposed to exposure light having a wavelength of 193 nm (ArF), the TiN / Ta ₂ O ₅ / TiN laminated film 2
4, first and second lower wiring layers 12a, 1
It becomes possible to suppress the occurrence of halation and the occurrence of standing waves in the photoresist due to irregular reflection by the upper surface and side wall surface of 2b. Therefore, the resist pattern 2
8, the opening accuracy of the via holes 26a, 26b can be improved, and the via holes 30a, 30b can be opened with high accuracy. As a result, the capacitance of the MIMC structure having high capacitance, low parasitic capacitance, and low parasitic resistance can be obtained. This can contribute to miniaturization and high reliability of the element 34.

In this case, the wavelength is 193 nm (Ar
F) TiN / Ta ₂ O ₅ / TiN laminated film 2 functioning as an anti-reflection film having a reflectance to exposure light of less than 10%
Reference numeral 4 denotes a TiN lower electrode layer 1 which forms a capacitive element 34 later.
Also consists _Ta 2 _{O 5} becomes a dielectric layer 20a _Ta 2 _{O 5} layer 20 Like TiN layer 22 serving as the TiN upper electrode layer 22a and the TiN layer 18 serving as 8a, there is no need to form an antireflection film separately Therefore, the complexity of the manufacturing process can be suppressed.

(Second Embodiment) FIGS. 8 to 14 are process sectional views for explaining a method of manufacturing a capacitor having an MIMC structure according to a second embodiment of the present invention. Note that the same components as those of the semiconductor device of the first embodiment shown in FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG.
After forming first and second lower wiring layers 12a and 12b having a thickness of about 300 to 1000 nm on an insulator layer 10 provided on a semiconductor substrate (not shown) such as a substrate, plasma CVD or the like is used. Then, an SiO ₂ insulating film is deposited on the entire surface of the substrate, and a smoothing process is performed on the SiO ₂ insulating film.
To form

Subsequently, a photolithography technique and RI
The openings 17a and 17b that selectively etch the SiO ₂ interlayer insulating film 14 on the first lower wiring layer 12a in the region where the capacitive element is to be formed by using the E method to expose the surface of the first lower wiring layer 12a , 17c. The width of these openings 17a, 17b, 17c will be described later.
7a, 17b, 17c TiN / T with irregularities
Since the W layer is buried in the concave portion of the a ₂ O ₅ / TiN laminated film, the width is set to a width that can sufficiently satisfactorily bury the W layer, for example, a width of about 0.25 to 1.2 μm.

Next, as shown in FIG.
Then, using a sputtering method or a CVD method,
TiN layer 1 having a thickness of about 5 to 100 nm serving as a lower electrode layer
9. Ta having a thickness of about 10 to 100 nm as a dielectric layer
₂O₅Layer 21, the thickness that will later become the upper electrode layer of the capacitive element
A TiN layer 23 of about 5 to 100 nm is sequentially deposited to a thickness
5-100 nm / 10-100 nm / 5-100 nm
TiN / Ta degree₂ O₅/ TiN laminated film 25 is formed
I do. And this TiN / Ta₂O₅/ TiN lamination
The film 25 has a shape in which irregularities are repeated, and the Ti layer
19 is the first through the openings 17a, 17b, 17c.
It is connected to the lower wiring layer 12a.

Next, as shown in FIG. 10, a photoresist is applied to the entire surface of the substrate using a photolithography technique, and then, for example, exposure light having a wavelength of 193 nm (ArF) is applied through a photomask on which a predetermined pattern is drawn. And further develop the first and second lower wiring layers 12
a, for example, 0.2 to 2.0 μm at a predetermined position above
A resist pattern 29 having openings 27a and 27b for via holes having a diameter of m is formed.

At the time of this exposure, a wavelength of 193 nm was used.
TiN / Ta ₂ O ₅ / T for exposure light of (ArF)
The reflectance of the iN laminated film 25 becomes less than 10%. That is,
The TiN / Ta ₂ O ₅ / TiN laminated film 25 has a wavelength of 193
It functions as an antireflection film for exposure light of nm (ArF). Accordingly, at the time of this exposure, the occurrence of halation and the occurrence of standing waves in the photoresist due to irregular reflection by the upper surface and the side wall surface of the first and second lower wiring layers 12a and 12b are suppressed. Since there is almost no influence by halation or standing wave effect, openings 27a and 27b for via holes of resist pattern 29 are formed with high precision.

Next, as shown in FIG.
Using the resist pattern 29 as a mask,
TiN exposed in the hole openings 27a and 27b /
Ta ₂O₅/ TiN laminated film 25 is selectively etched
Removed and then continuously ₂Select interlayer insulating film 14
To remove the first and second lower wiring layers 12
via holes 31a, 31b reaching the upper surfaces of
Open. After that, the resist pattern 29 is stripped.
The size of these via holes 31a and 31b will be described later.
When a W (tungsten) layer is deposited on the entire surface of the substrate,
W layer is well embedded in via holes 31a and 31b
The diameter should be small enough to fit.

Next, as shown in FIG. 12, the TiN / Ta ₂ O ₅ / TiN laminated film 25 having an uneven shape is exposed, and the entire surface of the substrate on which the via holes 31a and 31b are formed is formed by sputtering. , A Ti layer and a TiN layer as an adhesion layer and a barrier layer are continuously formed to form Ti / TiN
After forming the layer 36, a W layer is deposited using CVD.
Thus, the Ti / TiN is formed in the via holes 31a and 31b.
It is buried by the W layer via the layer 36. at the same time,
The concave portion formed by the uneven TiN / Ta ₂ O ₅ / TiN laminated film 25 is also filled with the W layer via the Ti / TiN layer 36.

Subsequently, the W layer on the substrate surface and the Ti / TiN
Layer 36 is etched back entirely. Thus, the W plugs 38a, 38 made of the W layer embedded in the via holes 31a, 31b via the Ti / TiN layer 36 connected to the first and second lower wiring layers 12a, 12b.
b is formed. At the same time, the uneven shape of TiN / Ta ₂ O
₅ / TiN laminated film 25 also has a TiN layer 23
Embedded through a Ti / TiN layer 36 connected to
A W plug 38c made of a layer is formed.

Next, as shown in FIG. 13, a metal layer 33 mainly composed of an Al alloy is formed on the entire surface of the substrate to a thickness of 300 mm.
It is formed to about 1000 nm.

Next, as shown in FIG.
By using lithography technology and RIE method, this Al alloy
Layer 33 containing Ti as a main component and TiN / Ta₂O₅/
The TiN laminated film 25 is selectively patterned. Like this
The lower portion of the TiN connected to the first lower wiring layer 12a.
Electrode layer 19a, Ta on this TiN lower electrode layer 19a
₂O₅Dielectric layer 21a and this Ta₂ O₅Dielectric
Capacitive element comprising TiN upper electrode layer 23a on layer 21a
35, that is, the TiN upper electrode layer 23a and the TiN lower electrode layer
Ta between 19a₂O₅With the dielectric layer 21a interposed
Is formed.

At the same time, the first upper wiring layer 33a and the first lower wiring layer 12a connected directly to the TiN upper electrode layer 23a of the capacitive element 35 or via the W plug 38c or the like.
Are connected via a W plug 38a or the like embedded in the via hole 31a, and are connected to the second lower wiring layer 12b via a W plug 38b or the like embedded in the via hole 31b. Third upper wiring layer 3
3c are respectively formed. That is, TiN of the capacitive element 35
First upper wiring layer 33a connected to upper electrode layer 23a
And a second upper wiring layer 33b connected to the TiN lower electrode layer 19a of the capacitor 35 via the first lower wiring layer 12a and the W plug 38a, respectively.
To complete.

As described above, according to the present embodiment, as in the case of the first embodiment, the first and second lower wiring layers 12a, 12a made of a metal layer containing an Al alloy as a main component.
on the b, through the SiO ₂ interlayer insulation film 14, a thickness of about 5~100nm serving as the lower electrode layer of the capacitor element after the TiN
Layer 19 and the thickness 10~100nm about _Ta 2 _{O 5} layer 21 and the thickness 5~100nm about TiN as the dielectric layer
TiN / Ta ₂ O ₅ / TiN sequentially deposited with a layer 23
After the formation of the laminated film 25, a photoresist is applied to the entire surface of the substrate using a photolithography technique, and is irradiated with, for example, exposure light having a wavelength of 193 nm (ArF) to form the first and second lower wiring layers 12a and 12b. An opening 27 for a via hole having a diameter of, for example, 0.2 to 2.0 μm is formed at a predetermined upper position.
By forming a resist pattern 29 having openings a and 27b, T functions as an antireflection film having a reflectance of less than 10% for exposure light having a wavelength of 193 nm (ArF).
Since the photoresist on the iN / Ta ₂ O ₅ / TiN laminated film 25 is exposed to exposure light having a wavelength of 193 nm (ArF), the first resist existing below the TiN / Ta ₂ O ₅ / TiN laminated film 25 is exposed. And second lower wiring layer 12
It is possible to suppress the occurrence of halation and the occurrence of standing waves in the photoresist due to irregular reflection by the upper surface and side wall surfaces of a and 12b. Therefore, it is possible to increase the opening accuracy of the via hole openings 27a and 27b of the resist pattern 29 and to open the via holes 31a and 31b with high accuracy.
This can contribute to miniaturization and high reliability of the capacitive element 35 having the MIMC structure with low parasitic resistance.

Also in this case, the wavelength is 193 nm (A
The TiN / Ta ₂ O ₅ / TiN laminated film 25 functioning as an anti-reflection film having a reflectance of less than 10% for the exposure light of rF) is composed of the TiN layer 19 which will later become the TiN lower electrode layer 19 a constituting the capacitor 35. since also consists _Ta 2 _{O 5} dielectric layer 21a to become _Ta 2 _{O 5} layer 21 Like TiN layer 23 serving as the TiN upper electrode layer 23a, it is not necessary to form the anti-reflection film separately, complication of the manufacturing process Can be suppressed.

The first and second lower wiring layers 12a,
After forming via holes 31a and 31b that expose the surface of 12b, W plugs 38a and 38b and the like are embedded in the via holes 31a and 31b, and the via holes 31a and 31b are formed.
Second and third wirings connected to the first and second lower wiring layers 12a and 12b via W plugs 38a and 38b in the base 31b.
By forming the upper wiring layers 33b and 33c, the via holes 31a and 31b of the present embodiment can be further miniaturized than the via holes 30a and 30b of the first embodiment.

In the first and second embodiments, the case where the exposure light having the wavelength of 193 nm (ArF) is used has been described. However, the exposure light is not limited to this wavelength. For example, in addition to the wavelength of 193 nm (ArF), a wavelength of 150 to 450 nm including a wavelength of 436 nm (g-line), a wavelength of 365 nm (i-line), a wavelength of 248 nm (KrF), and the like.
Exposure light may be used, or a wavelength of 157 nm (F ₂ ) and a wavelength of 13 nm (EU
It is also possible to use exposure light having a wavelength such as V) or EB.

[0048]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained. That is, according to the method of manufacturing a semiconductor device of the first aspect, when forming a via hole for connecting a lower wiring layer connected to the lower electrode layer of the capacitive element and the second upper wiring layer, the lower wiring layer is formed. After forming a laminated film in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated via an insulating film on the layer, a resist is applied on the laminated film using a photolithography technique, and a predetermined By irradiating exposure light having a wavelength of, and forming a resist pattern having an opening for a via hole, a laminate including a lower electrode layer, a dielectric layer, and an upper electrode layer on the insulating film above the lower wiring layer In a state in which the film is formed, the resist applied on the laminated film is irradiated with exposure light of a predetermined wavelength, and an opening for a via hole is opened. Wavelength exposure light Controlling the reflectance that, it is possible to control the occurrence of a standing wave in the halation occurs and the photoresist due to the diffused reflection top and side wall surfaces of the lower wiring layer lying below the multilayer film. Therefore, it is possible to control the opening accuracy of the via hole opening of the resist pattern, and to control the opening accuracy of the via hole itself.

Further, in this case, the laminated film for controlling the reflectance with respect to the exposure light having a predetermined wavelength is composed of a lower electrode layer, a dielectric layer, and an upper electrode layer for forming a capacitive element. Since it is not necessary to separately form the above film, complication of the manufacturing process can be suppressed.

According to the method of manufacturing a semiconductor device of the second aspect, as in the case of the first aspect, the lower wiring layer connected to the lower electrode layer of the capacitor and the second upper wiring layer are formed. When forming a via hole for connection, after forming a laminated film in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated on the lower wiring layer via an insulating film, using photolithography technology By applying a resist on the laminated film and irradiating exposure light of a predetermined wavelength to form a resist pattern having an opening for a via hole, the same effect as in the case of claim 1 can be obtained. In other words, it is possible to control the opening accuracy of the via hole opening of the resist pattern, thereby controlling the opening accuracy of the via hole itself.

Also in this case, the laminated film for controlling the reflectance with respect to the exposure light having a predetermined wavelength comprises a lower electrode layer, a dielectric layer, and an upper electrode layer for forming a capacitance element. Since it is not necessary to separately form a film for use, it is possible to suppress complication of the manufacturing process.

After forming a via hole for exposing the surface of the lower wiring layer, a plug layer made of a first conductive layer filling the via hole is formed, and connected to the lower wiring layer via the plug layer in the via hole. By forming the second upper wiring layer made of the second conductive layer, the via hole can be further miniaturized as compared with the case of the first aspect.

According to the third aspect of the present invention, a resist is applied on a laminated film in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated by photolithography. When a resist pattern having an opening for a via hole is formed by irradiating exposure light having a wavelength of, the laminated film serves as an antireflection film for exposure light having a predetermined wavelength. It is possible to suppress the occurrence of halation and the occurrence of standing waves in the photoresist due to irregular reflection by the upper surface and side wall surface of the lower wiring layer existing in the substrate. Therefore, the opening accuracy of the opening for the via hole in the resist pattern can be improved, and the via hole itself can be opened with high accuracy. As a result, the miniaturization of the capacitive element of the MIMC structure with high capacitance, low parasitic capacitance, and low parasitic resistance It can contribute to high reliability.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view (part 1) for describing a method for manufacturing a capacitive element having an MIMC structure according to a first embodiment of the present invention.

FIG. 2 is a process sectional view (part 2) for explaining the method for manufacturing the capacitive element having the MIMC structure according to the first embodiment of the present invention.

FIG. 3 is a process sectional view (part 3) for describing the method for manufacturing the capacitive element having the MIMC structure according to the first embodiment of the present invention.

FIG. 4 is a process sectional view (part 4) for explaining the method for manufacturing the capacitive element having the MIMC structure according to the first embodiment of the present invention.

FIG. 5 is a process sectional view (part 5) for explaining the method for manufacturing the capacitive element having the MIMC structure according to the first embodiment of the present invention.

FIG. 6 is a process sectional view (part 6) for explaining the method for manufacturing the capacitive element having the MIMC structure according to the first embodiment of the present invention.

FIG. 7 is a process sectional view (part 7) for explaining the method for manufacturing the capacitive element having the MIMC structure according to the first embodiment of the present invention.

FIG. 8 is a process sectional view (part 1) for explaining the method of manufacturing the capacitive element having the MIMC structure according to the second embodiment of the present invention.

FIG. 9 is a process cross-sectional view (part 2) for explaining the method for manufacturing the capacitive element having the MIMC structure according to the second embodiment of the present invention.

FIG. 10 is a process sectional view (part 3) for explaining the method for manufacturing the capacitive element having the MIMC structure according to the second embodiment of the present invention.

FIG. 11 is a process sectional view (part 4) for explaining the method of manufacturing the capacitive element having the MIMC structure according to the second embodiment of the present invention.

FIG. 12 is a process sectional view (part 5) for explaining the method of manufacturing the capacitive element having the MIMC structure according to the second embodiment of the present invention.

FIG. 13 is a process sectional view (part 6) for describing the method for manufacturing the capacitive element having the MIMC structure according to the second embodiment of the present invention.

FIG. 14 is a process cross-sectional view (part 7) for explaining the method for manufacturing the capacitive element having the MIMC structure according to the second embodiment of the present invention.

[Explanation of symbols]

10 ... insulator layer, 12a ... first lower wiring layer, 12
b: second lower wiring layer, 14: SiO ₂ interlayer insulating film, 16, 17a, 17b, 17c: opening, 18, 1
9 Ti layer, 18a, 19a Ti lower electrode layer, 2
0,21 ...... _Ta 2 _{O 5} layer, 20a, 21a ...... Ta
₂ O ₅ dielectric layer, 22, 23 ... TiN layer, 22a,
23a ... TiN upper electrode layer, 24, 25 ... TiN /
Ta ₂ O ₅ / TiN laminated film, 26a, 26b, 27a,
27b ... opening for via hole, 28, 29 ... resist pattern, 30a, 30b, 31a, 31b ... via hole, 32, 33 ... metal layer mainly composed of Al alloy, 32a, 33a ... first Upper wiring layer, 32b, 33
b: second upper wiring layer, 32c, 33c: third upper wiring layer, 34, 35: capacitive element, 36: Ti / T
iN layer, 38a, 38b, 38c... W plug.

Continued on front page F-term (reference) 5F033 HH09 HH33 JJ01 JJ09 JJ18 JJ19 JJ33 KK09 KK33 MM05 NN06 NN07 PP06 PP15 QQ03 QQ08 QQ09 QQ10 QQ13 QQ31 QQ37 QQ46 RR03 RR04 SS15 VV10 XX03 AC18 XX03 AC18 XX03 AC18 XX08 PA13

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device having a capacitive element in which an upper electrode layer is formed on a lower electrode layer via a dielectric layer, the method comprising: After forming an insulating film, a first step of selectively removing the insulating film by etching to form an opening exposing the surface of the lower wiring layer, a lower electrode layer, a dielectric layer, And a second step of forming a laminated film in which the upper electrode layer is sequentially laminated, and connecting the lower electrode layer of the laminated film to the lower wiring layer through the opening, using a photolithography technique, After applying a resist on the laminated film, a third step of irradiating exposure light of a predetermined wavelength to form a resist pattern having an opening for a via hole is formed, and the laminating is performed using the resist pattern as a mask. Film and said insulation A fourth step of forming a via hole for exposing the surface of the lower wiring layer by selectively etching away, forming a conductive layer on the entire surface of the substrate, and then patterning the conductive layer and the laminated film into a predetermined shape. And forming a capacitive element in which the upper electrode layer is laminated via the dielectric layer on the lower electrode layer connected to the lower wiring layer, and connecting to the upper electrode layer of the capacitive element Forming a first upper wiring layer made of the conductive layer, and forming a second upper wiring layer made of the conductive layer connected to the lower wiring layer via the via hole. A method for manufacturing a semiconductor device, comprising: 2. A method for manufacturing a semiconductor device having a capacitive element in which an upper electrode layer is formed on a lower electrode layer via a dielectric layer, the method comprising: After forming an insulating film, a first step of selectively removing the insulating film by etching to form an opening exposing the surface of the lower wiring layer, a lower electrode layer, a dielectric layer, And a second step of forming a laminated film in which the upper electrode layer is sequentially laminated, and connecting the lower electrode layer of the laminated film to the lower wiring layer through the opening, using a photolithography technique, After applying a resist on the laminated film, a third step of irradiating exposure light of a predetermined wavelength to form a resist pattern having an opening for a via hole is formed, and the laminating is performed using the resist pattern as a mask. Film and said insulation A fourth step of forming a via hole for exposing the surface of the lower wiring layer by selectively etching away the first conductive layer, forming a first conductive layer on the entire surface of the base, and then etching back the first conductive layer. Forming a plug layer made of the first conductive layer filling the via hole, forming a second conductive layer on the entire surface of the base, and then forming the second conductive layer and the laminated film. Is patterned into a predetermined shape,
Forming a capacitive element in which the upper electrode layer is laminated via the dielectric layer on the lower electrode layer connected to the lower wiring layer, and forming the second capacitive element connected to the upper electrode layer of the capacitive element Forming a first upper wiring layer made of a conductive layer of the above, and forming a second upper wiring layer made of the second conductive layer connected to the lower wiring layer via the plug layer in the via hole. 6. A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the forming of the resist pattern in which a via hole opening is formed in the third step includes the step of forming the laminated film into the predetermined shape. A method for manufacturing a semiconductor device, comprising: an antireflection film for exposure light having a wavelength. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the reflectance of the laminated film with respect to the exposure light having the predetermined wavelength is less than 10%. 5. The method for manufacturing a semiconductor device according to claim 3, wherein said lower electrode layer of said laminated film is made of TiN. 6. The method of manufacturing a semiconductor device according to claim 3, wherein said dielectric layer of said laminated film is made of Ta ₂ O ₅ . 7. The method of manufacturing a semiconductor device according to claim 3, wherein said upper electrode layer of said laminated film is made of TiN.