JP2002246418A5 - - Google Patents

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JP2002246418A5
JP2002246418A5 JP2001040357A JP2001040357A JP2002246418A5 JP 2002246418 A5 JP2002246418 A5 JP 2002246418A5 JP 2001040357 A JP2001040357 A JP 2001040357A JP 2001040357 A JP2001040357 A JP 2001040357A JP 2002246418 A5 JP2002246418 A5 JP 2002246418A5
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semiconductor element
hole
semiconductor
conductive sheet
electrode
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JP2001040357A
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JP2002246418A (en
JP3748779B2 (en
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半導体素子と回路形成体との間に、上記半導体素子の電極上に形成された外部電極端子に対応する箇所に貫通穴を有する熱可塑性若しくは熱硬化性のシートを介在させ、
上記半導体素子の上記電極上に形成された上記外部電極端子と上記回路形成体の電極とを上記シートの上記貫通穴を介して電気的に接続して上記半導体素子と上記回路形成体とを接合することを特徴とする半導体素子の実装方法。
Between a semiconductor element and a circuit forming body, a thermoplastic or thermosetting sheet having a through hole at a position corresponding to the external electrode terminal formed on the electrode of the semiconductor element is interposed,
The external electrode terminal formed on the electrode of the semiconductor element and the electrode of the circuit forming body are electrically connected through the through hole of the sheet to join the semiconductor element and the circuit forming body. A method for mounting a semiconductor element, comprising:
上記外部電極端子と上記回路形成体の電極とを電気的に接続するとき、上記半導体素子の上記電極上に形成された上記外部電極端子としてのめっきバンプと上記回路形成体の上記電極とを上記シートの上記貫通穴を介して電気的に接続して上記半導体素子と上記回路形成体とを接合する請求項1に記載の半導体素子の実装方法。When the external electrode terminal and the electrode of the circuit forming body are electrically connected, the plating bump formed as the external electrode terminal formed on the electrode of the semiconductor element and the electrode of the circuit forming body are The method for mounting a semiconductor element according to claim 1, wherein the semiconductor element and the circuit forming body are joined by being electrically connected through the through hole of the sheet. 上記外部電極端子と上記回路形成体の電極とを電気的に接続するとき、上記半導体素子の上記電極上にワイヤボンディング法により形成された上記外部電極端子としての突起バンプと上記回路形成体の上記電極とを上記シートの上記貫通穴を介して電気的に接続して上記半導体素子と上記回路形成体とを接合する請求項1に記載の半導体素子の実装方法。When the external electrode terminal and the electrode of the circuit forming body are electrically connected, the bump bump as the external electrode terminal formed on the electrode of the semiconductor element by the wire bonding method and the above of the circuit forming body The method for mounting a semiconductor element according to claim 1, wherein the semiconductor element and the circuit formed body are joined by electrically connecting an electrode to the sheet through the through hole of the sheet. 上記外部電極端子と上記回路形成体の電極とを電気的に接続するとき、上記半導体素子の上記電極上に形成された上記外部電極端子と上記回路形成体の上記電極とを、上記シートの、上記半導体素子の上記電極上に形成された上記外部電極端子部に一対一に対応した位置に配置された貫通穴を介して電気的に接続して上記半導体素子と上記回路形成体とを接合する請求項2又は3に記載の半導体素子の実装方法。When the external electrode terminal and the electrode of the circuit forming body are electrically connected, the external electrode terminal formed on the electrode of the semiconductor element and the electrode of the circuit forming body are The semiconductor element and the circuit forming body are joined by being electrically connected to the external electrode terminal portion formed on the electrode of the semiconductor element through a through hole arranged at a one-to-one correspondence. The method for mounting a semiconductor element according to claim 2. 上記外部電極端子と上記回路形成体の電極とを電気的に接続するとき、上記半導体素子の上記複数個の電極上に形成された上記複数個の外部電極端子と上記回路形成体の上記複数個の電極とを、上記シートの長穴形状に形成された貫通穴を介して電気的に接続して上記半導体素子と上記回路形成体とを接合する請求項2又は3に記載の半導体素子の実装方法。When the external electrode terminals and the electrodes of the circuit forming body are electrically connected, the plurality of external electrode terminals formed on the plurality of electrodes of the semiconductor element and the plurality of circuit forming bodies 4. The semiconductor element mounting according to claim 2, wherein the semiconductor element and the circuit forming body are joined by electrically connecting the electrodes to each other through a through hole formed in a long hole shape of the sheet. Method. 上記熱可塑性若しくは熱硬化性のシートは、熱可塑性若しくは熱硬化性の樹脂と金属粒子とを有する導電性のシートである請求項1〜5のいずれか1つに記載の半導体素子の実装方法。The method for mounting a semiconductor element according to claim 1, wherein the thermoplastic or thermosetting sheet is a conductive sheet having a thermoplastic or thermosetting resin and metal particles . 請求項1〜6のいずれか1つに記載の半導体素子の実装方法により上記半導体素子が上記回路形成体に実装された回路形成部品。  The circuit formation component by which the said semiconductor element was mounted in the said circuit formation body by the mounting method of the semiconductor element as described in any one of Claims 1-6. 受光素子が形成された半導体演算回路チップと、受光素子光路用の貫通穴を持つ基板に発光素子が埋め込まれた発光素子アレイと、回折型光学素子を持つ回折型光学素子付き基板とを一体化した光情報処理装置において、
上記半導体演算回路チップと上記発光素子アレイとの間に、上記受光素子の光路用貫通穴を設けた、熱可塑性若しくは熱硬化性の第1導電性シートを介在させて上記半導体演算回路チップと上記発光素子アレイとが接合されているとともに、上記発光素子アレイと上記回折型光学素子との間に、上記受光素子の光路用貫通穴を設けた、熱可塑性若しくは熱硬化性の第2導電性シートを介在させて上記発光素子アレイと上記回折型光学素子とを接合することを特徴とする光情報処理装置。
A semiconductor arithmetic circuit chip on which a light receiving element is formed, a light emitting element array in which a light emitting element is embedded in a substrate having a through hole for a light receiving element optical path, and a substrate with a diffractive optical element having a diffractive optical element are integrated. Optical information processing apparatus
Between the semiconductor arithmetic circuit chip and the light emitting element array, a thermoplastic or thermosetting first conductive sheet provided with an optical path through hole of the light receiving element is interposed, and the semiconductor arithmetic circuit chip and the above A thermoplastic or thermosetting second conductive sheet having a light-emitting element array bonded thereto and an optical path through hole for the light- receiving element provided between the light-emitting element array and the diffractive optical element. the by interposing an optical information processing apparatus characterized by bonding the light emitting element array and said diffractive optical element.
上記第1導電性シート及び第2導電性シートは、上記発光素子の光路を確保する貫通穴を有する請求項8に記載の光情報処理装置。The optical information processing apparatus according to claim 8, wherein the first conductive sheet and the second conductive sheet have a through hole that secures an optical path of the light emitting element. 上記第1導電性シート及び第2導電性シートのうちの少なくとも一方は、熱可塑性若しくは熱硬化性の樹脂と金属粒子とを有する異方導電性の導電性シートである請求項8又は9に記載の光情報処理装置。  10. At least one of the first conductive sheet and the second conductive sheet is an anisotropic conductive sheet having a thermoplastic or thermosetting resin and metal particles. Optical information processing equipment. 受光素子が形成された半導体演算回路チップと、受光素子光路用の貫通穴を持つ基板に発光素子が埋め込まれた発光素子アレイと、回折型光学素子を持つ回折型光学素子付き基板とを一体化した光情報処理装置を製造する光情報処理装置の製造方法において、
上記半導体演算回路チップと上記発光素子アレイとの間に、上記受光素子の光路用貫通 穴を設けた、熱可塑性若しくは熱硬化性の第1導電性シートを介在させるとともに、上記第1導電性シートにより上記半導体演算回路チップと上記発光素子アレイとを接合する一方、
上記発光素子アレイと上記回折型光学素子との間に、上記受光素子の光路用貫通穴を設けた、熱可塑性若しくは熱硬化性の第2導電性シートを介在させるとともに、上記第2導電性シートにより上記発光素子アレイと上記回折型光学素子とを接合することを特徴とする光情報処理装置の製造方法。
A semiconductor arithmetic circuit chip on which a light receiving element is formed, a light emitting element array in which a light emitting element is embedded in a substrate having a through hole for a light receiving element optical path, and a substrate with a diffractive optical element having a diffractive optical element are integrated. In an optical information processing apparatus manufacturing method for manufacturing an optical information processing apparatus,
A thermoplastic or thermosetting first conductive sheet provided with an optical path through hole for the light receiving element is interposed between the semiconductor arithmetic circuit chip and the light emitting element array, and the first conductive sheet. While joining the semiconductor arithmetic circuit chip and the light emitting element array by,
Between the light emitting element array and the diffractive optical element, there is interposed a thermoplastic or thermosetting second conductive sheet provided with an optical path through hole for the light receiving element, and the second conductive sheet. A method of manufacturing an optical information processing apparatus, comprising: bonding the light emitting element array and the diffractive optical element by:
上記第1導電性シート及び第2導電性シートとして、上記発光素子の光路を確保する貫通穴を設けた導電性シートを使用する請求項10に記載の光情報処理装置の製造方法。The method of manufacturing an optical information processing apparatus according to claim 10, wherein a conductive sheet provided with a through hole that secures an optical path of the light emitting element is used as the first conductive sheet and the second conductive sheet . 半導体素子と回路形成体との間に、上記半導体素子の電極上に形成された外部電極端子に対応する箇所に、上記半導体素子の上記電極上に形成された上記外部電極端子と上記回路形成体の電極とを電気的に接続する貫通穴を有する熱可塑性若しくは熱硬化性のシート。The external electrode terminal formed on the electrode of the semiconductor element and the circuit formed body at a location corresponding to the external electrode terminal formed on the electrode of the semiconductor element between the semiconductor element and the circuit formed body. A thermoplastic or thermosetting sheet having a through hole for electrically connecting the electrode.
JP2001040357A 2001-02-16 2001-02-16 Semiconductor element mounting method and thermoplastic or thermosetting sheet Expired - Fee Related JP3748779B2 (en)

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JP2002246418A5 true JP2002246418A5 (en) 2005-05-26
JP3748779B2 JP3748779B2 (en) 2006-02-22

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JP4670697B2 (en) * 2006-03-24 2011-04-13 株式会社デンソー Manufacturing method of sensor device
JP5141545B2 (en) * 2008-12-26 2013-02-13 株式会社デンソー Mechanical quantity sensor device
JPWO2011093405A1 (en) * 2010-02-01 2013-06-06 有限会社Mtec Optical semiconductor device with chip size package
JP5998450B2 (en) * 2011-10-19 2016-09-28 住友ベークライト株式会社 Optical waveguide module, optical waveguide module manufacturing method, and electronic apparatus
CN103811593B (en) 2012-11-12 2018-06-19 晶元光电股份有限公司 The production method of semiconductor optoelectronic element
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