JP2002243821A - Skew adjustment method for lsi tester and skew adjustment program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a skew adjustment method for an LSI tester that can resolve a tester skew problem independently of a test environment by obtaining skew detecting information before actual measurement for every test. SOLUTION: Information of minimum resolution and a maximum skew value of the tester to use from a tester information library e are obtained. A test pattern f and a test program g for skew detection suited for a measured LSI are created based on the minimum resolution, the maximum skew value, circuit connection information d and a test program c. A skew value of each pin of the tester is calculated from a result h measured by the test pattern f and the test program g created, and a test program i for an actual test is created by reflecting the skew value in the original test program c. The measured LSI is measured using the test program i and the test pattern b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a skew adjustment method for an LSI tester for measuring an LSI using a test pattern and a test program.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a conventional skew adjustment method for measuring (testing) a circuit to be measured such as an LSI. In the skew adjustment method shown in FIG. 9, a test program and a test pattern are given to a tester to measure (test) an actual LSI, and when a skew problem is suspected at the time of occurrence of a defect, a manual trial and error is performed on the test program. This is to adjust the timing and find out the conditions for passing.

FIG. 10 is a diagram showing a conventional skew adjustment method for performing a simulation using a netlist of a circuit to be measured and a test pattern. The skew adjustment method shown in FIG. 10 uses a netlist and a test pattern, performs a simulation taking into account expected timing (skew) information, and adjusts the timing by trial and error when a failure occurs to verify the validity. It is.

[0004]

The measurement (test) of an LSI is performed by giving a test program and a test pattern to a tester. In this case, even if a test pattern is given, the test pattern is stored inside the actual LSI. There is a time lag before it arrives, which causes a problem that the LSI does not operate properly. The tester itself has a skew, and the skew is different for each terminal of the tester, so that the test pattern reaches the inside of the LSI with a time difference, so that the tester does not operate even though the circuit is actually created correctly. Things happen.

FIG. 11 is a diagram showing an example of an LSI to be measured, a timing chart when testing the LSI to be measured, and an example of a test program. The timing chart shown in FIG. 11 shows a case where there is no skew in the terminals of the tester, and shows a state where the LSI to be measured is operating properly.

FIG. 12 shows an LSI to be measured and a timing chart when the skew value s1 is attached to the data signal D1 of the tester and the skew value s2 is attached to the clock signal CLK2. In the timing chart shown in FIG.
The signals described as (correct) and O2 (correct) must be output. However, when the data signal D1 and the clock signal CLK2 from the tester are skewed, the LSI under test malfunctions and O1 (wrong), O
A signal described as 2 (wrong) is output.

As described above, a circuit that should normally operate correctly does not operate properly due to the skew of the signal output from the tester terminal, and it is determined that the circuit is not correctly created. The timing of the signal output from the tester terminal must be adjusted for each test environment.

In the skew adjustment method shown in FIG. 9 described above, time is required because the timing adjustment is manually performed by trial and error. In addition, the condition that should have been set once may be broken due to a change in the test environment.

Further, in the skew adjustment method shown in FIG. 10 described above, it takes a long time for a simulation as the circuit becomes large-scale. If the prediction is disappointed, a re-simulation is required, which takes more time. The dependence on the test environment is the same as the skew adjustment method shown in FIG.

An object of the present invention is to provide a skew adjustment method for an LSI tester that can adjust the timing of a signal output from a tester terminal in a short time without depending on a test environment.

[0011]

SUMMARY OF THE INVENTION The present invention relates to an LSI for measuring an LSI using a test pattern and a test program.
In the tester skew adjustment method, a skew detection test pattern tailored to the LSI for each test environment is provided based on the test program, the circuit connection information of the LSI, and information of a minimum resolution and a maximum skew value of the LSI tester. A skew detection test program is generated. From the result of measuring the LSI using the generated skew detection test pattern and the skew detection test program,
A skew value of a signal given to the LSI is calculated, and the calculated skew value is reflected on the test program.

Further, the present invention provides a skew detection test adapted to the LSI for each test environment based on a test program, LSI circuit connection information, and information on an LSI tester's minimum resolution and maximum skew value. A procedure for generating a pattern and a skew detection test program, a procedure for calculating a skew value of a signal given to the LSI from a result of measuring the LSI using the generated skew detection test pattern and the skew detection test program, Reflecting the calculated skew value in the test program.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

A skew adjustment method for an LSI tester according to the present invention generates a skew detection test pattern and a test program for each test environment and uses the skew detection test pattern and the test program to measure the skew detection test pattern and the test program. The skew value of the tester is detected, and the detected skew value of the tester is reflected in a test program for the main test.

FIG. 1 is a flowchart showing an embodiment of a skew adjusting method for an LSI tester according to the present invention. The operation flow at the time of design is shown above the dotted line, and the operation flow at the time of test is shown below the dotted line.

In FIG. 1, first, a test circuit is inserted into circuit connection information a to generate circuit connection information d (step 101).

The circuit connection information a is connection information of the LSI to be measured. The circuit connection information d is connection information of a circuit in which a test circuit has been inserted into the LSI to be measured. FIG. 2 shows an example of a circuit in which a test circuit is inserted into an LSI to be measured.
In FIG. 2, a portion drawn by a bold line is the measured LSI obtained from the circuit connection information a. The portion drawn by the thin line is the inserted test circuit portion. Test circuit, flip-flop circuit 11 ₁ to 11 ₄ and the selector 1
It is constituted by 2 _{1-12 4.}

This test circuit is already incorporated when a boundary scan inspection device is used.
At this time, it is not necessary to insert a test circuit.

Next, the test program c, the circuit connection information d of the LSI under test into which the test circuit is inserted, and the information of the minimum resolution time and the maximum skew value of the tester to be used are given to the tester, and the test pattern is given. (For detection) f,
Generate a test program (for detection) g (Step 1)
02).

The generation of the test pattern (for detection) f and the test program (for detection) g are realized by execution processing of software (program) by an arithmetic processing unit (not shown).

The test program c is a program in which tester instructions are written. FIG. 3 shows an example of the test program c. It should be noted that the test program shown in FIG. 3 shows the concept and the format and contents (items) are completely different from those of the actual program.

The minimum resolution time and the maximum skew value of the tester to be used are stored in the tester information library e in advance for each tester model.

FIG. 4 is a diagram showing an example of the generated test pattern (for detection) f. Here, the time of the minimum resolution of the tester used is t, and the maximum skew value is D.

In the test pattern shown in FIG. 4, the test clock signal T-CLK is first raised at the seventh pattern with the skew value t of the minimum resolution, and
This time, at the 14th pattern, the test clock signal T-CLK rises with a skew value 2t twice the minimum resolution, and in the next 21 pattern, rises with a skew value 3t three times the minimum resolution. Is started by increasing the skew value in the minimum resolution unit every 7th pattern,
Finally, the skew value mt at the N-7 pattern (7m pattern)
(M is a natural number, mt ≧ D).

In FIG. 4, the test clock signal T
−CLK is started by increasing the skew value in minimum resolution units every (number of skew adjustment target terminals of the LSI to be measured + 1) clock number. However, the present invention is not limited to this, and the test clock signal is not limited to this. The T-CLK may be started by increasing the skew value in minimum resolution units at least for each clock number equal to the number of skew adjustment target terminals of the LSI to be measured.

FIG. 5 is a diagram showing an example of the generated test program (for detection) g. Data signals D1, D2
The delay values of the clock signals CLK1 and CLK2 are all 0.

Next, a test pattern f for skew detection and a test program g are given to a tester to actually measure LS
A measurement (tester) is performed at I, and a result h is obtained (step 1)
03). FIG. 6 shows the measurement result h.

Next, based on the measurement result h, the data signal D
FIGS. 2 and 6 show how to detect skew values of clock signals CLK1, CLK2 and clock signals CLK1, CLK2.
This will be described with reference to FIG.

In the seventh pattern in FIG. 6, the control signal T-SE
L makes the selector 12₁Selects the data signal D1
Therefore, the data signal D1 is supplied to the flip-flop circuit
11 ₁Latched. In addition, the control signal T-SEL
Selector 12_TwoNow, the clock signal CLK1 is selected.
And selector 12_ThreeSelects the data signal D2 and
Lecter 12_FourNow, the clock signal CLK2 is selected and
And the clock signal CLK1 is a flip-flop.
Circuit 11_TwoAnd the data signal D2 is flipped.
Flip-flop circuit 11_ThreeAnd the clock signal CL
K2 is the flip-flop circuit 11_FourLatched.

Here, the data signal D1 has a minimum resolution t.
And a skew value s1 equal to
LK2 has a skew value s2 if it is larger than the minimum resolution t.
, Respectively, so that the test clock signal T-CL which rises at time t of the minimum resolution at the seventh pattern
At K, the rising state of the data signal D1 and the clock signal CLK2 cannot be detected. Accordingly, the output of the flip-flop circuit 11 ₁ is 0, the output of the flip-flop circuit 11 ₂ is 1, the flip-flop circuit 11
The output of ₃ 1 and the output of the flip-flop circuit 11 ₄ is zero. This 7 pattern eyes, a test output signal T-OUT is 0 from the flip-flop circuit 11 _1.

In the eighth pattern, the test clock signal T
Since -CLK has not risen, the output value 0 of the flip-flop circuit 11 ₁ does not change, the test output signal T-
OUT remains at 0.

At the ninth pattern, the control signal T-SEL
As a result, the selector 12 ₁ causes the flip-flop circuit 11 ₂
Is selected, the test clock signal T
Output values of the flip-flop circuit 11 ₂ by -CLK 1
There is latched by the flip-flop circuit 11 _1.

Similarly, the selector 12_TwoWith flip flop
Circuit 11_ThreeIs selected, and the selector 12_ThreePretend
Flip-flop circuit 11_FourOutput is selected,
The flip-flop is generated by the test clock signal T-CLK.
Circuit 11_ThreeOutput value 1 of the flip-flop circuit 11
_TwoAnd the flip-flop circuit 11_FourOutput value of
0 is the flip-flop circuit 11_ThreeLatched. free
Flip-flop circuit 11 _FourIs the test input signal T-IN
Latch the signal value 0. In this 9th pattern, flip
Flop circuit 11₁Test output because the output value of is 1.
The signal T-OUT becomes 1.

Similarly, at the tenth pattern, the flip-flop circuit 11 is driven by the test clock signal T-CLK.
_Second output value 1 is latched by the flip-flop circuit 11 _1, the output value 0 of the flip-flop circuit 11 ₃ is latched by the flip-flop circuit 11 _2, the output value 0 of the flip-flop circuit 11 _4, the flip-flop circuit 11
Latched at _three . Flip-flop circuit 11 ₄ latches the signals values 0 of the test input signal T-IN. This one
The 0 pattern th, the output value of the flip-flop circuit 11 ₁ is 1 test output signal T-OUT is 1.

[0035] In the 11 patterns th by a test clock signal T-CLK, the output value 0 of the flip-flop circuit 11 ₂ is latched in the flip-flop circuit 11 _1, the output value 0 of the flip-flop circuit 11 _3, the flip-flop It is latched by circuit 11 _2, flip-flop circuits 1
The output value 0 of 1 ₄ is latched by the flip-flop circuit 11 _3. Flip-flop circuit 11 ₄ latches the signal value 0 the test input signal T-IN. This 11 pattern th output value of the flip-flop circuit 11 ₁ is the test output signal T-OUT is 0 since it is zero.

Since the twelfth pattern operates in the same manner as the eleventh pattern, the test output signal T-OUT becomes 0 and 1
3 pattern th, since no rises test clock signal T-CLK, the output value 0 of the flip-flop circuit 11 ₁ is not changed, the test output signal T-OUT remains zero.

At the 14th pattern, the control signal T-SE
L makes the selector 12₁Selects the data signal D1
Therefore, the data signal D1 is supplied to the flip-flop circuit
11 ₁Latched. The selector 12_TwoOK
The clock signal CLK1 is selected and the clock signal CLK1
Is a flip-flop circuit 11_TwoLatched. Sele
Kuta 12_ThreeSelects the data signal D2 and the data signal
D2 is a flip-flop circuit 11_ThreeLatched.
Selector 12_FourSelects the clock signal CLK2,
The clock signal CLK2 is supplied to the flip-flop circuit 11_Four
Latched.

The data signal D1 and the clock signal CLK2
Have a skew value s1 and a skew value s2, respectively.
However, here, the skew value s1 is smaller than 2t,
Since the skew value s2 is equal to 2t, 14 patterns
Test clock signal that rises 2t time later
T-CLK detects the rising state of data signal D1
Yes, but the rising state of the clock signal CLK2 is detected.
I can't get out. Therefore, the flip-flop circuit 11₁
Is 1 and the flip-flop circuit 11 _TwoOutput
Becomes 1 and the flip-flop circuit 11_ThreeOutputs 1 and
And the flip-flop circuit 11₁Is 0.
In the 14th pattern, the flip-flop circuit 11₁of
Since the output value is 1, the test output signal T-OUT becomes 1
Become.

[0039] In the 15 patterns first, because it does not stand up the test clock signal T-CLK, the output value 1 of the flip-flop circuit 11 ₁ does not change, the test output signal T
−OUT remains at 1.

At the 16th pattern, the control signal T-SE
L, the selector 12 ₁ causes the flip-flop circuit 11
Since the output of ₂ is selected, an output value 1 of the flip-flop circuit 11 ₂ is the test clock signal T-CLK, is latched by the flip-flop circuit 11 _1.

Similarly, the selector 12_TwoWith flip flop
Circuit 11_ThreeIs selected, and the selector 12_ThreePretend
Flip-flop circuit 11_FourOutput is selected,
The flip-flop is generated by the test clock signal T-CLK.
Circuit 11_ThreeOutput value 1 of the flip-flop circuit 11
_TwoAnd the flip-flop circuit 11_FourOutput value of
0 is the flip-flop circuit 11_ThreeLatched. free
Flip-flop circuit 11 _FourIs the test input signal T-IN
Latch the signal value 0. In this 16th pattern,
Flip-flop circuit 11₁Test output because the output value of
The force signal T-OUT becomes 1.

Similarly, at the seventeenth pattern, the flip-flop circuit 11 is driven by the test clock signal T-CLK.
_Second output value 1 is latched in flip-flop circuit 11 _1, the output value 0 of the flip-flop circuit 11 ₃ is latched by the flip-flop circuit 11 _2, the output value 0 of the flip-flop circuit 11 _4, the flip-flop circuit 11
Latched at _three . Flip-flop circuit 11 ₄ latches the signal value 0 the test input signal T-IN. This one
The 7 pattern eyes, the output value of the flip-flop circuit 11 ₁ is 1 test output signal T-OUT is 1.

[0043] In the 18 patterns th by a test clock signal T-CLK, the output value 0 of the flip-flop circuit 11 ₂ is latched in the flip-flop circuit 11 _1, the output value 0 of the flip-flop circuit 11 _3, the flip-flop It is latched by circuit 11 _2, flip-flop circuits 1
The output value 0 of 1 ₄ is latched by the flip-flop circuit 11 _3. Flip-flop circuit 11 ₄ latches the signal value 0 the test input signal T-IN. This 18 pattern th output value of the flip-flop circuit 11 ₁ is the test output signal T-OUT is 0 since it is zero.

Since the nineteenth pattern operates in the same manner as the eighteenth pattern, the test output signal T-OUT becomes 0 and 2
0 pattern th, since no rises test clock signal T-CLK, the output value 0 of the flip-flop circuit 11 ₁ is not changed, the test output signal T-OUT remains zero.

At the 21st pattern, the control signal T-SE
L makes the selector 12₁Selects the data signal D1
Therefore, the data signal D1 is supplied to the flip-flop circuit
11 ₁Latched. The selector 12_TwoOK
Since the clock signal CLK1 is selected, the clock signal
CLK1 is the flip-flop circuit 11_TwoLatched in
You. Selector 12_ThreeIn the data signal D2 is selected
Therefore, the data signal D2 is supplied to the flip-flop circuit 11
_ThreeLatched. Selector 12_FourThen, the clock signal C
LK2 is selected, and the clock signal CLK2 is flip-flopped.
Flop circuit 11_FourLatched.

Here, the data signal D1 and the clock signal C
LK2 has a skew value s1 and a skew value s2, respectively.
The skew value s1 and the skew value s2 are
Since it is smaller than 3t, the rising state of the data signal D1 and the clock signal CLK2 can be detected from the test clock signal T-CLK which has risen after 3t time at the 21st pattern, and the test output signal T-OUT is at the 21st pattern. It becomes 1.

[0047] In the 22 patterns first, because it does not stand up the test clock signal T-CLK, the output value 1 of the flip-flop circuit 11 ₁ does not change, the test output signal T
−OUT remains at 1.

At the 23rd pattern, the control signal T-SE
L, the selector 12 ₁ causes the flip-flop circuit 11
Output ₂ is selected, the output of the flip-flop circuit 11 ₃ is selected by the selector 12 _2, the output of the flip-flop circuit 11 ₄ is selected by the selector 12 _3,
The test clock T-CLK, the output value 1 of the flip-flop circuit 11 _2, flip-flop circuit 11
Is latched by _1, the output value 1 of the flip-flop circuit 11 ₃ is latched by the flip-flop circuit 11 _2, the output value 1 of the flip-flop circuit 11 ₄ is latched by the flip-flop circuit 11 _3. Flip-flop circuit 11 ₄
Latches the signal value 0 of the test input signal T-IN.
This 23 pattern eyes, the output value of the flip-flop circuit 11 ₁ is 1 test output signal T-OUT is 1.

Similarly, in the 24th pattern, the test
Flip-flop circuit 11 according to the_Two
Is output from the flip-flop circuit 11₁Latched in
And the flip-flop circuit 11_ThreeOutput value 1
Flip-flop circuit 11_TwoLatched by a flip-flop
Circuit 11_FourOf the flip-flop circuit 11 _Three
Latched. Flip-flop circuit 11_FourIs Tess
The signal value 0 of the input signal T-IN is latched. This 24
In the pattern, the flip-flop circuit 11₁Output value is
Since it is 1, the test output signal T-OUT becomes 1.

In the 25th pattern, the T for the test clock is used.
The -CLK, the output value 1 of the flip-flop circuit 11 ₂ is latched in the flip-flop circuit 11 _1, the output value 0 of the flip-flop circuit 11 ₃ is latched by the flip-flop circuit 11 _2, flip-flop circuit 11
The output value 0 of ₄ is latched by the flip-flop circuit 11 _3. Flip-flop circuit 11 ₄ latches the signal value 0 the test input signal T-IN. This 25 pattern eyes, the output value of the flip-flop circuit 11 ₁ is 1 test output signal T-OUT is 1.

In the 26th pattern, the test clock T
The -CLK, the output value 0 of the flip-flop circuit 11 ₂ is latched in the flip-flop circuit 11 _1, the output value 0 of the flip-flop circuit 11 ₃ is latched by the flip-flop circuit 11 _2, flip-flop circuit 11
The output value 0 of ₄ is latched by the flip-flop circuit 11 _3. Flip-flop circuit 11 ₄ latches the signal value 0 the test input signal T-IN. This 26 pattern th output value of the flip-flop circuit 11 ₁ is the test output signal T-OUT is 0 since it is zero.

Based on the above measurement results, that is, the observation result of the test output signal T-OUT, the data signal D1 has a skew value s1, the clock signal CLK2 has a skew value s2, and the skew values s1, s2, t, 2t,
It can be detected that there is a relationship of 0 <s1 = t <s2 = 2t <3t during 3t.

Next, the skew of the test program is adjusted based on the obtained result h, the test program c, and the circuit connection information d, thereby creating a test program (for the main test) i (step 104).

The generation of the test program (for the main test) i is realized by execution processing of software (program) by an arithmetic processing unit (not shown).

FIG. 7 shows a test program (for the main test).
It is a figure showing an example of i. In the test program i shown in FIG. 7, the test program c shown in FIG. 3 is based on the clock signal CLK2 having the largest skew value,
The data signal D1 is delayed by t time which is the minimum resolution,
The data signal D2 and the clock signal CLK1 are adjusted so as to be delayed by 2t time.

The skew value of the clock signal CLK2, which has been delayed most, is set to 0, the skew value t is added to the data signal D1, and the skew value 2t is added to the data signal D2 and the clock signal CLK1 which originally have no skew. Then, when given to the tester, it reaches the inside of the LSI to be measured at the same time.

Finally, the LSI to be measured is measured (tester) using the test pattern b and the test program (for this test) i (step 105). FIG. 8 is a diagram showing the measurement results of the test program (for the main test) i. Data signal D1 ', D2' and clock signal CLK
1 'and CLK2' indicate signals provided inside the LSI to be measured during the main test. As shown in FIG. 8, correct outputs O1 and O2 are obtained from the LSI to be measured.

The embodiment of the present invention has been described above in detail with reference to the drawings.
It is needless to say that the present invention is not limited to this embodiment, and is all examples including the LSI to be measured and the test circuit shown in FIG.

Each of the steps 101 to 105 in the above-described embodiment can be realized by executing processing of software (program) by an arithmetic processing unit (not shown).

[0060]

As described above, the present invention generates a test pattern and a test program for skew detection,
A skew value of a signal to be applied to an LSI to be measured is detected based on a result measured using a test pattern and a test program for skew detection, and the detected skew value is reflected in a test program for this test. Since the skew detection information is obtained before each measurement, the skew problem of the tester can be solved without depending on the test environment.

Further, since the present invention can be realized by executing software (program), it is possible to calculate and adjust a skew value in a short time.

Further, the present invention does not require any special equipment for realizing the method of the present invention, and can be realized with conventional equipment.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of a skew adjustment method for an LSI tester according to the present invention.

FIG. 2 is a diagram illustrating an example of a circuit in which a test circuit is inserted into a circuit to be measured.

FIG. 3 is a diagram illustrating an example of a test program c.

FIG. 4 is a diagram illustrating an example of a test pattern (for detection) f.

FIG. 5 is a diagram illustrating an example of a test program (for detection) g.

FIG. 6 is a diagram showing a measurement result h.

FIG. 7 is a diagram showing an example of a test program (for the main test) i.

FIG. 8 is a diagram showing a measurement result of a test program (for a main test) i.

FIG. 9 is a diagram illustrating a conventional skew adjustment method.

FIG. 10 is a diagram showing a conventional skew adjustment method.

FIG. 11 illustrates an example of an LSI to be measured, a timing chart when the LSI to be measured is tested, and an example of a test program.

FIG. 12 shows that the terminal of the data signal D1 has a skew value s1 and the terminal of the clock signal CLK2 has the skew value s.
FIG. 3 is a diagram showing a measured LSI and a timing chart when the number 2 is attached.

[Explanation of symbols]

a, d circuit connection information b test pattern c test program e tester information library f test pattern (for detection) g test program (for detection) h result i test program (for main test) 11 _{1 to} 11 ₄ flip-flop circuit 12 ₁ ~ 12 ₄ selector

Claims (10)

[Claims] 1. A skew adjustment method for an LSI tester for measuring an LSI using a test pattern and a test program, comprising: a test program, circuit connection information of the LSI, and a minimum resolution and a maximum skew value of the LSI tester. A skew detection test pattern and a skew detection test program generated in accordance with the LSI for each test environment from the information, and a result of measuring the LSI using the generated skew detection test pattern and the skew detection test program A skew value of a signal to be applied to an LSI, and reflecting the calculated skew value in the test program. 2. The LS according to claim 1, wherein the circuit connection information includes connection information of a test circuit used for calculating the skew value together with the connection information of the LSI.
Skew adjustment method for I tester. 3. The skew adjustment of the LSI tester according to claim 1, wherein the minimum resolution and the maximum skew value of the LSI tester are stored in advance in a tester information library for each type of the LSI tester. Method. 4. In the skew detection test pattern, a test clock signal for latching a signal applied to each terminal of the LSI includes a skew value in a minimum resolution unit from a minimum resolution of the LSI tester to a maximum skew value. 4. The skew adjusting method for an LSI tester according to claim 1, wherein 5. The LSI according to claim 4, wherein a skew value of the test clock signal increases in minimum resolution units at least for each clock number equal to the number of skew adjustment target terminals of the LSI. How to adjust the skew of the tester. 6. A computer, comprising: a test program; LSI circuit connection information;
A procedure for generating a skew detection test pattern and a skew detection test program tailored to the LSI for each test environment from information on a minimum resolution and a maximum skew value of the tester; and the generated skew detection test pattern and skew detection. A skew adjustment program for executing a procedure of calculating a skew value of a signal given to an LSI from a result of measuring the LSI using a test program, and a procedure of reflecting the calculated skew value in the test program. 7. The skew adjustment program according to claim 6, wherein the circuit connection information includes connection information of a test circuit used for calculating the skew value together with the connection information of the LSI. 8. The skew adjustment program according to claim 6, wherein the minimum resolution and the maximum skew value of the LSI tester are stored in advance in a tester information library for each type of the LSI tester. 9. In the skew detection test pattern, a test clock signal for latching a signal applied to each terminal of the LSI includes a skew value in a minimum resolution unit from a minimum resolution of the LSI tester to a maximum skew value. The skew adjustment program according to any one of claims 6 to 8, wherein? 10. The skew of the test clock signal according to claim 9, wherein the skew value of the test clock signal increases in minimum resolution units at least for each clock number equal to the number of skew adjustment terminals of the LSI. Adjustment program.