JP2002237735A - Automatic gain controller for radio receiver and radio receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress resonation in an automatic gain controller for a radio receiver. SOLUTION: A power detector 41 detects the power level of a digital signal ID, and an integrator 42 integrates the power level in a variable period, and calculates the integrated value. The various period is changed at random, and the updating time of the variable gain is changed at random. It is possible, therefore, to prevent a semi-synchronization detection signal I from varying in a period equal to that of the variable gain, and thus the variation of the variable gain is prevented from synchronizing with the variation of the semi- synchronization detection signal I. Consequently, it is possible to suppress resonance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an automatic gain control device for a radio receiver.

[0002]

2. Description of the Related Art A schematic configuration of a conventional W-CDMA radio receiver will be described below with reference to FIGS. FIG.
FIG. 5 is a block diagram showing a schematic configuration of a wireless receiver.
5 is a block diagram showing details of a control unit on the real part side of the quasi-synchronous detection signal in FIG. In FIG. 4, the radio receiver includes a quasi-synchronous detection circuit 10, power amplifiers 20a and 20b, analog-digital converters 30a and 30b, control units 40a and 4b.
0b, and a demodulator 50.

First, in the radio receiver shown in FIG. 4, a received signal Rx is input to a quasi-synchronous detection circuit 10. This quasi-synchronous detection circuit 10 multiplies the received signal Rx by COS (ωt + θ) in a multiplier 11 and
In step 2, the quadrature detection is performed by multiplying SIN (ωt + θ), and the low-pass filters (LPF) 13 and 14 remove the harmonic components, thereby outputting quasi-synchronous detection signals I and Q.

[0004] Next, the power amplifier 20a obtains the power amplification signal I _A by power-amplifying the quasi same detection signal I by the variable gain,
Power amplifier 20b calculates the power amplification signal Q _A by power-amplifying the detection signal Q at the variable gain. Analog - digital converter 30a converts the power-amplified signal I _A into a digital signal I _D, analog - digital converter 30b converts the power amplification signal Q _A into a digital signal Q _D.

[0005] Here, the control unit 40a controls the power amplifier 20
together with the automatic gain control circuit (AGC circuit)
The automatic gain control circuit uses analog-to-digital conversion.
Wide dynamic range while suppressing the increase in the number of quantization bits of the
The signal of the mic range is converted to the analog-digital converter 30a.
Has been adopted to be entered into. others
Therefore, the control unit 40a includes the analog-digital converter 30a
Digital signal I from _DVariable gain according to
The variable gain is output to the power amplifier 20a.

[0006] More specifically, as shown in FIG.
0a is composed of a power detector 41, an integrator 42, an integration time determination counter 43, and a digital-analog converter 44. The power detector 41 outputs the digital signal I _D
The integrator 42 integrates the power level over a certain period and outputs the integrated value for reasons such as improving noise resistance. In other words, the integrator 42 calculates the average value of the power level for a certain period. The fixed period is provided from the integration time determination counter 43 to the integrator 42.

Next, the digital-analog converter 44
The integrated value from the integrator 42 is converted into an analog signal, and the analog signal is given to the power amplifier 20a as the variable gain. Thereby, the control unit 40a forms a feedback loop to obtain the variable gain, and outputs an analog signal indicating an average value of the power level for a certain period to the power amplifier 20a. The control unit 40b, like the control unit 40a, an analog - determine the variable gain according to the digital signal Q _D from the digital converter 30b, and outputs the variable gain power amplifier 20b.

[0008]

As described above, the control unit 40a of the radio receiver integrates the power level of the digital signal _ID over a certain period in order to obtain the variable gain. The gain is updated at regular intervals. Therefore, a delay time occurs in updating the variable gain, and the variable gain and the quasi-synchronous detection signal I
When the (received signal Rx) fluctuates at a substantially equal cycle, there is a problem that the fluctuation of the variable gain is synchronized with the fluctuation of the quasi-synchronous detection signal I to cause resonance.

On the other hand, as shown in FIG. 6, it has been proposed to employ a control unit 40A having a variable coefficient multiplier 45 between a power detector 41 and an integrator 42 (2).
2000, IEICE General Conference B-5-58).

In FIG. 6, a variable coefficient multiplier 45 has a
Digital signal I from force detector 41 _DPower level
Multiplied by a variable coefficient and outputs the multiplied signal.
Is integrated by integrating the multiplied signal over the predetermined period.
Find the value (average value). Digital-analog converter 44
Converts the integrated value from the integrator 42 into a digital signal
The digital signal is used as the variable gain as the power amplifier 20.
a.

However, when the variable coefficient multiplier 45 multiplies the power level by a variable coefficient equal to or less than “1” to obtain a multiplied signal and reduces the amount of change in the variable gain, the controller 40 A Is suppressed, but the received signal Rx
It becomes impossible to follow a sudden input fluctuation such as shadow wing in the (quasi-synchronous detection signal I).

In view of the above, it is an object of the present invention to provide an automatic gain control device for a radio receiver, which suppresses resonance while keeping track of input fluctuations.

[0013]

In order to achieve the above object, according to the first aspect of the present invention, a power amplifier (20a) for amplifying a received signal by a variable gain and outputting a power amplified signal is provided. And calculating means (41, 42, 44) for averaging the power value of the power amplified signal over a predetermined period to obtain an average power value and outputting the obtained average power value as a variable gain to the power amplifier. And control means (46) for controlling the calculating means so as to obtain the average power value by randomly varying the predetermined period.

Thus, the calculating means averages the power values of the power amplification signals over a predetermined period that is randomly varied to obtain a variable gain, so that the variable gain calculation time is randomly varied. Therefore, the received signal has a variable gain,
It is possible to avoid fluctuations with the same period, and it is possible to suppress resonance caused by the variable gain and the received signal. Furthermore, since the calculating means outputs the variable gain to the power amplifier without reducing the amount of fluctuation of the variable gain, it is possible to keep track of the input fluctuation.

Here, a radio receiver that performs radio reception in the CDMA system employs a generator for generating a code that is randomly variable as a spreading code for despreading and demodulating a power amplified signal. The predetermined period may be randomly varied by using a spreading code from the means.

More specifically, a power amplifier (20a, 20b) for power-amplifying a received signal with a variable gain and outputting a power-amplified signal, and despreading the power-amplified signal, as in the second aspect of the present invention. A radio receiver for performing CDMA radio reception, comprising a generating means (610) for generating a spread code for demodulation, wherein the power value of the power amplified signal is averaged over a predetermined period to obtain an average power. Calculating means (41, 42, 44) for obtaining a value and outputting the obtained average power value as a variable gain to the power amplifier, and a variable period randomly varying according to the spreading code of the generating means as a predetermined period. And controlling means (462) for controlling the calculating means so as to obtain the average power value over the variable period.

In this case, the calculating means averages the power values of the power amplification signals over a variable period that varies randomly to obtain a variable gain, so that the variable gain calculation time varies randomly. Therefore, similarly to the first aspect of the present invention, the received signal can be prevented from fluctuating in the same cycle as the variable gain, the resonance can be suppressed, and the calculating means can calculate the amount of change in the variable gain. Since the variable gain is output to the power amplifier without reducing the power gain, it is possible to keep track of the input fluctuation. In addition to this, a variable period that is randomly varied using the spreading code of the generating means is obtained, so that the configuration can be simplified.

Further, according to the third aspect of the present invention, a power amplifier (20a) for power-amplifying a received signal by a variable gain and outputting a power-amplified signal, and averaging the power value of the power-amplified signal over a predetermined period. Calculating means (41, 42, 44) for obtaining the average power value as a variable gain and outputting the obtained average power value to the power amplifier as a variable gain, and a resonance detecting means for detecting resonance caused by the received signal and the variable gain ( 471) and control means (472) for controlling the calculation means so as to obtain an average power value by varying a predetermined period when resonance is detected by the resonance detection means.

Thus, when the occurrence of resonance is detected by the resonance detecting means, the calculating means averages the power values of the power amplified signals over a variable predetermined period to obtain an average power value. The power of the received signal is amplified by the average power value. Therefore, even if resonance occurs due to the variable gain and the received signal, the resonance can be interrupted, and the resonance caused by the variable gain and the received signal can be suppressed. Furthermore, the calculation means outputs the average power value as a variable gain to the power amplifier without reducing the variation amount of the average power value, so that the tracking means can keep up with the input fluctuation. obtain.

Incidentally, the reference numerals in parentheses of the above means are examples showing the correspondence with specific means described in the embodiments described later.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a first embodiment of a W-CDMA radio receiver according to the present invention. FIG. 1 is a block diagram showing a partial schematic configuration of the wireless receiver. In FIG. 1, the wireless receiver includes a power amplifier 20a, an analog-digital converter 30a, and
It has a control unit 40A. The control unit 40A includes the power detector 4
1, an integrator 42, an integration time controller 46, and a digital-analog converter 44. However, in FIG. 1, the same reference numerals shown in FIG. 5 indicate the same or substantially the same.

In the control unit 40A shown in FIG. 1, a power detector 41 detects the power level of the digital signal _ID ,
The integrator 42 integrates the power level over a variable period to obtain an integrated value (average value). The digital-analog converter 44 converts the integrated value from the integrator 42 into a digital signal, and applies the digital signal as a variable gain to the power amplifier 20a. The digital signal, and
The variable gain indicates an average value of the power level over a variable period.

Here, the variable period is a period in which the period changes at random, and the integration time controller 46 controls the integrator 42.
Is given to The random value generator 461 sequentially outputs a random value, and the counter 462 adds the random value from the integration time controller 461 every predetermined number, and uses the added value as the variable period as the integrator 42. Will be added to

As described above, since the integration period of the power level by the integrator 42 changes randomly, the update time (delay period) of the variable gain changes randomly.
Therefore, it is possible to avoid that the quasi-synchronous detection signal I (received signal Rx) and the variable gain fluctuate in the same cycle, and the fluctuation of the variable gain does not synchronize with the fluctuation of the quasi-synchronous detection signal I. The resonance between the variable gain and the quasi-synchronous detection signal I can be suppressed. In addition to this, as the variable gain (average power value), the level is not varied by a coefficient,
As in the configuration shown in FIG.
Since it is added to a, it is possible to maintain the following performance with respect to input fluctuation (fluctuation of the quasi-synchronous detection signal I).

In the first embodiment, an example is described in which the automatic gain control device is applied to a W-CDMA wireless receiver. However, the present invention is not limited to this, and is applied to various types of wireless receivers. Is also good.

Further, in the first embodiment, an example has been described in which the random value generator 461 for sequentially outputting random values to the counter 462 is employed. However, the present invention is not limited to this, and the received signal Rx is CDMA demodulated. A random value may be obtained by using a spreading code for this purpose. FIG. 2 shows the configuration in this case.

In FIG. 2, control units 400a and 400b are employed instead of the control unit 40A shown in FIG. 1 (in FIG. 1, the control unit on the imaginary part side is omitted). Further, FIG. 2 shows a detailed configuration of the demodulation unit 50. However, in FIG. 2, the same reference numerals shown in FIG. 1 indicate the same items.

Here, since the spreading code is generated in the demodulation unit 50, the configuration of the demodulation unit 50 will be described below. Demodulation unit 50, the digital signal I _D, and searcher 500 to detect the reception timing of the reception for each path of the received signal Rx in response to the Q _D, the digital signal I _D, receive path Q _D at the detected received timing Finger 600 that despreads each time, a combiner 700 that receives the despread signal for each reception path from finger 600, performs maximum ratio synthesis of the despread signals for a plurality of reception paths, and outputs the synthesized value as a demodulated signal. And

[0029] Note that the digital signal I _D is an analog - which has been outputted from the digital converter 30a, a digital signal Q _D is an analog - in which output from the digital converter 30b. Hereinafter, the configuration of one finger 600 in the demodulation unit 50 will be described with reference to FIG. First, in the finger 600, the digital signals I _D and Q _D are input to each of the despreading circuits 601 and 602.

Next, a complex correlator 601 obtains a complex correlation between the digital signals I _D and Q _D and spreading codes (demodulated CH Codes) Ci and Cq for demodulating an information channel. , And digital signals I _D , Q _D, and spreading codes (CPICH Code) Cpi, Cpq for demodulating a pilot channel (CPICH).

Next, the channel estimator 603 obtains a channel estimation value based on the complex correlation value by the complex correlator 602. For example, the channel estimation value indicates the amount of change in the phase of the signal in the communication path. Further, the channel compensator 60
4 is a complex correlator 601 based on the channel estimation value.
Is corrected, and a signal indicating the corrected value is output to the combiner 700 as a despread signal.

Each of the above-mentioned fingers 600 has a DLL (Dela) for synchronously following a spreading code.
y Locked Loop) circuit 610 is provided. In this DLL circuit 610, a complex correlator 611
Is that the phase is a predetermined value, for example, 1 /
A spreading code Ci ′ (= Ci (τ +
0.5)) and Cq ′ (= (τ + 0.5)), the complex correlation values between these spreading codes Ci ′ and Cq ′ and the digital signals I _D and Q _D are obtained. . Note that Ci ′ and Cq ′ indicate “CPICH Early Code” in FIG.

Next, the complex correlator 612 outputs the spread code C
i, Cq, a spreading code Ci ″ (= Ci (τ−0.5)) whose phase is delayed by チ ッ プ chip, Cq ″ (= Cq
(Τ−0.5)), these spread codes Ci ″, C
A complex correlation value between q ″ and the digital signals I _D and Q _D is obtained.
Note that τ indicates the phase difference between the spreading codes Ci and Cq, and the phase difference τ becomes 0 when synchronization is established. Also, Ci ″ and Cq ″ are “CPICH Lat” in FIG.
e Code ”.

Next, the real part and the imaginary part of the complex correlation value by the complex correlator 611 are squared by the squarers 613 and 614, respectively, and the result is added by the adder 615, and the complex correlation value of the complex correlator 611 is added. (Power) is output. Further, the real part and the imaginary part of the complex correlation value by the complex correlator 612 are squared by the squarers 616 and 617, and the results are added by the adder 618, and the magnitude of the complex correlation value by the complex correlator 612 ( Output).

Next, the outputs of the adders 615 and 618 are input to the adder 619. Adder 61
9 is the difference between the output of the adder 615 and the output of the adder 618;
That is, the difference D between the magnitude of the complex correlation value where the 1/2 chip phase is advanced and the magnitude of the complex correlation value where the 1/2 chip phase is delayed is obtained.

Here, the magnitude of the complex correlation value becomes the largest when the phase is 0 (τ = 0) with synchronization. At this time, the magnitude of the complex correlation value where the チ ッ プ chip phase is advanced is equal to the magnitude of the complex correlation value where the チ ッ プ chip phase is delayed, and the correlation value output from the adder 619 becomes equal. The output D indicating the magnitude difference becomes zero. But,
If the phase is shifted, there is a difference between the magnitude of the correlation value where the 1/2 chip phase is advanced and the magnitude of the correlation value where the 1/2 chip phase is delayed, and the output D of the adder 619 becomes It does not become 0 but has a predetermined size.

The output D of the adder 619 is input to the timing control section 621 via the LPF 620. The timing control unit 621 controls the code generator 622 so that the output D of the adder 619 becomes 0. For this reason, the code generator 622 is controlled by the timing control unit 621 to generate the spread codes Ci, Cq, Ci ′, Cq ′, Ci ″, C
Generate q ''. As a result, phase tracking control of the spread code is performed so that the output D of the adder 136 becomes zero.

Here, the spreading codes Ci, Cq, Ci ', C
The values of q ′, Ci ″, Cq ″ are sequentially and randomly varied, and the spreading codes Ci, Cq, Ci ′, Cq ′, C
i ”and Cq ″, any one of the spreading codes
0a (400b) is input to the counter 462. Then, the counter 462 adds the above-mentioned spreading codes for each predetermined number, and gives the added value to the integrator 42 as the above-mentioned variable period. As described above, in obtaining the variable period, without using the random value generator 461 shown in FIG.
Since two spreading codes are used, the circuit configuration can be simplified.

As described above, the present invention is not limited to obtaining the variable period using the spreading code subjected to the phase tracking control, but may obtain the variable period using the spreading code before the phase tracking control. Good.

(Second Embodiment) In the first embodiment,
The example in which the integration period of the power level by the integrator 42 is changed at random has been described. However, the present invention is not limited to this, and the resonance between the variable gain and the quasi-synchronous detection signal I is detected. The integration period of 42 may be varied. FIG. 3 shows the configuration in this case.

In the configuration shown in FIG. 3, the control unit 4 shown in FIG.
Instead of the 0A integration time controller 46, the integration time controller 4
7 is adopted. However, in FIG. 3, the same reference numerals shown in FIG. 1 indicate the same or substantially the same.

The comparator 471 of the control unit 40A shown in FIG.
Determines the occurrence of resonance between the change in the variable gain and the change in the quasi-synchronous detection signal I. Specifically, when the power level of the digital signal _ID by the power detector 41 exceeds the maximum inputtable level of the analog-digital converter 30a for a predetermined period or more, the comparator 471 determines that the resonance has occurred. Then, the variable counter 472 instructs the variable counter 472 to vary the integration period, and the variable counter 472 gives a different integration period to the integrator 42 each time the variable counter 472 receives the instruction from the comparator 471.

As described above, when the fluctuation of the variable gain and the resonance of the quasi-synchronous detection signal I occur, the integration period of the power level by the integrator 42 varies. Accordingly, an integrated value of the power level over the variable integration period is obtained, and the quasi-synchronous detection signal I is obtained by the integrated value (variable gain).
(Q) is power amplified. Therefore, each time a resonance occurs, the resonance is interrupted, and the resonance can be suppressed. In addition, similarly to the above-described first embodiment, the variable gain (average power value) is not changed by a coefficient, and the variable gain is applied to the power amplifier 20a. (A fluctuation of the signal I).

In the second embodiment, an example is described in which the automatic gain control device is applied to a W-CDMA wireless receiver. However, the present invention is not limited to this, and is applied to various types of wireless receivers. Is also good.

Further, although FIG. 2 shows a configuration in which the received signal RX is directly converted into a baseband signal, it is needless to say that the present invention can also be applied to a system in which the received signal RX is converted into a baseband signal via an intermediate frequency band. Further, in FIG. 2, the power amplifiers 20a and 20b (variable gain amplifiers) are shown after the low-pass filters (LPF) 13 and 14, but not limited to this position, , Before the multipliers 11 and 12,
Any number of stages may be used.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a partial configuration of a W-CDMA wireless receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a partial configuration of a modification of the first embodiment.

FIG. 3 is a block diagram illustrating a partial configuration of a W-CDMA wireless receiver according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a partial configuration of a conventional wireless receiver.

FIG. 5 is a block diagram showing a detailed configuration of a part of FIG. 4;

FIG. 6 is a block diagram showing a partial configuration of a conventional wireless receiver.

[Explanation of symbols]

 40A: control unit, 41: power detector, 42: integrator.

Claims (3)

[Claims] 1. A power amplifier (20a) for power-amplifying a received signal by a variable gain to output a power-amplified signal, and averaging a power value of the power-amplified signal over a predetermined period to obtain an average power value; Calculating means (41, 42, 44) for outputting the obtained average power value to the power amplifier as the variable gain; and calculating means for randomly varying the predetermined period to obtain the average power value. Control means (46) for controlling the automatic gain control of the radio receiver. 2. A power amplifier (20a, 20a) that power-amplifies a received signal by a variable gain and outputs a power-amplified signal.
b) and a generating means (610) for generating a spread code for despread demodulation of the power amplified signal, the radio receiver performing CDMA wireless reception, comprising: Calculating means (41, 42, 44) for averaging the power values over a predetermined period to obtain an average power value, and outputting the obtained average power value to the power amplifier as the variable gain; Control means (462) for determining a variable period that is randomly varied according to the spreading code as the predetermined period, and controlling the calculation unit so as to obtain the average power value over the variable period. Radio receiver. 3. A power amplifier (20a) for power-amplifying a received signal by a variable gain to output a power-amplified signal, and averaging a power value of the power-amplified signal over a predetermined period to obtain an average power value. Calculating means (41, 42, 44) for outputting the obtained average power value to the power amplifier as the variable gain; resonance detecting means (471) for detecting resonance caused by the received signal and the variable gain; When the resonance is detected by the resonance detecting means,
Control means (472) for controlling the calculation means so as to obtain the average power value by varying the predetermined time period.