KR100363907B1 - Auto frequency tracking control apparatus and method - Google Patents

Abstract

The present invention relates to a frequency automatic tracking control device and method for automatically tracking and compensating a carrier frequency error of a received signal, comprising: an accumulator for accumulating despread received signals by a spreading factor of a DPCCH; A moving average filter for removing noise from the output of the accumulator and increasing the number of outputs of the frequency error detector; A frequency error detection unit for inputting the output of the moving average filter, separating the real component and the imaginary component, and calculating them to output a signal proportional to the frequency error of the received signal; A received signal amplitude detector for calculating the separated real component and the imaginary component to detect an amplitude component of the received signal; As an output signal of the received signal amplitude detection unit, a signal proportional to a frequency error of the received signal is normalized, and a jump address for mapping a value obtained by adding a gain according to a multi-stage tracking mode to the normalized value is generated and output. A digital signal processor; And a frequency error compensation signal generator which reads the frequency error compensation signal indicated by the hopping address from the memory and multiplies the output signal of the accumulator.

Description

Frequency automatic tracking control device and its control method {AUTO FREQUENCY TRACKING CONTROL APPARATUS AND METHOD}

The present invention relates to a frequency automatic tracking control device and method, and more particularly, to an automatic frequency tracking control device and method for automatically tracking and compensating a carrier frequency error of a received signal.

Europe / Japan-oriented Generation Partnership Project (3GPP) is an asynchronous CDMA method called W-CDMA, and each base station operates independently without a separate receiver such as a GPS receiver. The third generation mobile communication W-CDMA base station modem is equipped with an AFC (Auto Frequency Control) circuit for automatic tracking control of the frequency.

The AFC circuit tracks the local error by tracking and compensating for the frequency error when the receiving local oscillator cannot accurately match the carrier frequency of the received signal or the Doppler frequency generated when the mobile station's moving speed is high and cannot be compensated by the channel estimator. The problem of the oscillator is compensated for and the desired reception performance can be obtained even when the mobile station has a high speed.

Therefore, fast tracking and compensation of frequency error using AFC is an essential requirement for efficient operation of the receiver. In general, AFC loops can be largely divided into long loops and short loops. In a base station accommodating multiple users, a short loop that adjusts frequency error for each user with an independent local oscillator is suitable, and a long loop is suitable for a terminal.

A configuration of a detector for detecting a frequency error (a difference between a carrier frequency and a receiver local oscillation frequency for demodulating the frequency error due to Doppler shift) in a conventional AFC loop employing such a short loop scheme is shown in FIG. 1. .

Referring to FIG. 1, a received signal is a signal multiplexed by a dedicated physical data channel (DPDCH) and a dedicated physical control channel (DPCCH), and when only a DPCCH channel passes through a 256 chip accumulation stage after despreading Will remain. Therefore, the received signal input to the frequency error detector is a complex DPCCH signal.

The splitter 10 separately outputs a complex DPCCH signal into a signal corresponding to a real part Re and a signal corresponding to an imaginary part Im. The real component Re of the separated output signal is multiplied by the imaginary component Im of the newly input signal from the first multiplier 16 after being delayed by one symbol in the time delay Ts 12. The imaginary component Im is also multiplied by the real component Re of the newly input signal which is inputted to the second multiplier 18 after being delayed by one symbol in the time delay Ts 14. In this way, a value proportional to the frequency error is output by multiplying the real component of the previous symbol by the imaginary component of the current symbol, and the value output from each of the multipliers 16 and 18 is added by the adder 20 and the polarity (+, -) And output as the final signal proportional to the frequency error.

However, the frequency error detector of the above-described configuration has a constant output due to path loss, multipath, and Rayleigh fading, and the change is very large. Converting these outputs to frequency introduces significant error. In more detail,

First, the pilot symbols accumulated by the spread factor (SF) of the DPCCH (256) are represented by Equation 1 below.

In Equation 1, N is the number of chips per symbol, Is the frequency error, Is the amplitude distortion component of the received signal, Is the sampling time and n (m) is the AWGN. The amplitude distortion of the received signal is caused by various causes. The first cause is path loss, and the amplitude of the transmitted signal is never maintained. The second is multipath. ), A signal that suffers from path loss is received at the receiving end with lower energy due to multiple paths. And the third is due to Rayleigh fading, which has the adverse effect of making the amplitude of the signal received evenly non-uniform.

Therefore, when the received signal of the DPCCH passes through the frequency error detector of the above-described configuration, a signal of the form Is output as

In Equation 2 Wow Product of, and Because of the fractional term (components of amplitude distortion due to frequency error), the output of the frequency error detector is not always constant. These components are components that change from time to time. When these components are present, the accuracy of the components of the frequency error detector when converted 1: 1 to the corresponding frequency error is reduced. This will cause the receiver to degrade the reception performance.

Accordingly, an object of the present invention is to remove the amplitude distortion component due to the noise component and the frequency error from the received signal, so that the frequency error detector output and frequency error by one-to-one conversion to accurately track the frequency error tracking compensation device and In providing a method.

Still another object of the present invention is to provide an automatic frequency tracking control apparatus and method for quickly tracking frequency errors by compensating for the delay of the frequency error tracking time that may occur when employing a frequency error detector for removing the components. In providing.

1 is a configuration example of a frequency difference detector (Frequency Difference Detector) employed in a general automatic frequency tracking control device.

2 is a block diagram of an automatic frequency tracking control device according to a preferred embodiment of the present invention.

3 is a diagram illustrating a slot structure of a dedicated physical control channel (DPCCH) for explaining the operation of a moving average filter according to an exemplary embodiment of the present invention.

4 illustrates a normalized output characteristic curve of a frequency error detector 40 according to an embodiment of the present invention.

5 is a diagram illustrating a multi-stage tracking mode switching of the automatic frequency tracking control apparatus according to the embodiment of the present invention.

6 is a configuration diagram of a plurality of frequency automatic tracking control apparatus in which the frequency error combiner 110 and the received signal amplitude combiner 120 are inserted as another embodiment of the present invention.

7 and 8 are graphs showing the frequency error compensation characteristics according to the use of AGC and normalization block

9 is a graph showing jitter performance according to the use of AGC and normalization block.

10 is a graph of frequency error compensation when the multi-stage tracking mode is applied to an automatic frequency tracking control apparatus according to an embodiment of the present invention.

Frequency automatic tracking control apparatus according to a preferred aspect of the present invention for achieving the above object;

An accumulator for accumulating the despread received signal by the spreading factor of the DPCCH;

A moving average filter for removing noise from the output of the accumulator and increasing the number of outputs of the frequency error detector;

A frequency error detection unit for inputting the output of the moving average filter, separating the real component and the imaginary component, and calculating them to output a signal proportional to the frequency error of the received signal;

A received signal amplitude detection unit for functionally processing the separated real and imaginary components to detect an amplitude distortion component of the received signal;

As an output signal of the received signal amplitude detection unit, a signal proportional to a frequency error of the received signal is normalized, and a jump address for mapping a value obtained by adding a gain according to a multi-stage tracking mode to the normalized value is generated and output. A digital signal processor;

And a frequency error compensation signal generator which reads the frequency error compensation signal indicated by the hopping address from the memory and multiplies the output signal of the accumulator.

Digital signal processing unit of the automatic frequency tracking control apparatus according to an additional aspect of the present invention;

A divider for normalizing the output of the frequency error detector to the amplitude of the received signal;

An accumulator for accumulating the normalized values to minimize the influence of noise;

A loop filter for adding a gain according to a multi-stage tracking mode to an output of the accumulator to prevent a sudden change of frequency;

A frequency mapper for mapping the output of the loop filter one to one with a frequency error;

And a gain adjusting unit for accumulating the output of the accumulator by one frame period or more, and comparing the accumulated value with preset reference values to vary the gain of the loop filter.

On the other hand the automatic frequency tracking control method according to another aspect of the present invention;

Accumulating the despread received signal by a spreading factor of the DPCCH and converting the received signal into a pilot symbol;

Detecting a frequency error and a received signal amplitude of the received signal in the converted pilot symbol, respectively;

Normalizing the detected frequency error of the received signal to the received signal amplitude;

Adding a gain according to the multistep tracking mode to the normalized value and generating a hopping address for mapping this value to frequency;

And compensating for the frequency error by reading a frequency error compensation signal indicated by the generated hopping address and multiplying the pilot symbol.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that a detailed description of a known function or configuration, such as a conventional frequency error detector (FDD) 40, may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. .

2 is a block diagram of an automatic frequency tracking control apparatus according to a preferred embodiment of the present invention. The automatic frequency tracking control apparatus includes a received signal amplitude detection unit 60 and a digital signal in a general FDD 40 configuration. The signal processor 80, the frequency error compensation signal generator 100, the accumulator 32, and the moving average filter 36 are added.

Referring to FIG. 1, a received signal is a signal in which a Dedicated Physical Data Channel (DPDCH) and a Dedicated Physical Control Channel (DPCCH) are channel multiplexed, and is despread by a scrambling code applied to the multiplier 30. 32). The despread received signal is accumulated for 256 chips in the accumulator 32. The reason why the despread received signal is accumulated for 256 chips is because the spreading factor of the DPCCH is 256 chips. In the 256-chip accumulation process, the signal of the DPDCH channel is lost. The reason is that the OVSF code of the DPDCH is not removed. The period of the OVSF code is a divisor of 256 and the sum of one period of OVSF is "0". Therefore, the sum of DPDCHs without OVSF removed is "0". Logically, it can be thought that the OVSF of the DPCCH has not been removed either. However, the OVSF codes of the DPCCH have a period of 256 and all are "1". Therefore, no extra work is needed to remove the OVSF code.

The moving average filter 36 is a 1-tap FIR filter in which 256 chip cumulative energy of the DPCCH and past cumulative energy values are combined and output. Positioning the moving average filter 36 at the input of the frequency error detector (FDD) 40 is to reduce the AWGN (noise), because the more the noise accumulates, the closer the average is to " 0 ".

3 illustrates a slot structure of a dedicated physical control channel (DPCCH) for explaining an operation of a moving average filter according to a preferred embodiment of the present invention. As shown in FIG. 3, only a portion of one slot corresponds to a pilot symbol. The number of pilot symbols varies from three to eight. 3 is a diagram based on the number of pilot symbols 5. In FIG. 3, the upper slot is a real part of the DPCCH channel, and the lower slot is an imaginary part. In FIG. 3, link symbols are indicated between two neighboring pilot symbols. The display conceptually connects the symbols summed with each other in the moving average filter 36. That is, if there are five pilot symbols, this means that four moving average operations will occur. The moving average operation is not performed in the remaining sections except for the pilot symbol.

On the other hand, the output value from the moving average filter 36 is four per slot, and this value is input to the frequency error detector (FDD) 40. In FIG. 3, the moving average filter output of the slot shown above is a real part, and the moving average filter output of the slot shown below is input to an imaginary part. These values are multiplied by a conventional frequency error detector (FDD) 40, which represents the values by which the arrows are multiplied by one another. In the example of FIG. 3, a total of three outputs causes a total of three outputs per slot in the frequency error detector FDD: 40.

Therefore, assuming the use of five pilot symbols per slot, the use of the moving average filter 36 has the advantage that the number of FDD outputs (three per slot) can be further increased than when not using, Since the jitter of the FDD 40 output is reduced and good jitter performance can be obtained even through the small accumulation of the FDD output, the convergence time of the loop filter output, which will be described later, can be reduced, and as a result, the tracking time for the frequency error can be reduced.

On the other hand, the received signal amplitude detection unit 60 performs a functional calculation on each of the real component Re and the imaginary component Re of the previous pilot symbol separated by the splitter 42 located at the input terminal of the frequency error detector (FDD) 40. To output the amplitude distortion component of the received signal. If you specify this as a formula,

First, the output of the moving average filter 36 may be simply expressed by Equation 3 below.

In Equation 3 Represents the amplitude distortion component of the received signal, Denotes a frequency error component at time k. The product of the conjugate complex number of S (k) and one symbol delay output S (k-1) of S (k) can be expressed by Equation 4 below.

In Equation 4, an imaginary part is a frequency error component output from the frequency error detector 40. Meanwhile, the real part of Equation 4 may be defined by Equation 5 below.

Therefore, when the equations 4 and 5 are squared and added, the amplitude distortion component of the received signal Can be obtained.

The digital signal processor (DSP) 80 normalizes the output of the frequency error detector (FDD) 40 and generates a hopping address for mapping the value obtained by adding gain according to the multi-step tracking mode to the normalized value to frequency. Output

The digital signal processor 80 includes a divider 82 for normalizing the output of the frequency error detector (FDD) 40. That is, the divider 82 as a normalization block normalizes the FDD 40 output by dividing the output of the frequency error detector FDD: 40 by the square root of the output of the received signal amplitude detector 60. The use of the normalization block is to normalize the output of the frequency error detector (FDD) 40 whose gain is sensitive to the amplitude of the received signal.

On the other hand, the output of the frequency error detector (FDD) 40 normalized to the amplitude component of the received signal is accumulated in the accumulator 84 to minimize the influence of noise. The accumulated value is then input to the first order IIR filter after the gain g is multiplied to obtain the desired tracking performance again in the loop filter 86. The gain (g) is a value less than 1, and the signal accumulated in the accumulator 84 is also used to increase the stability instead of lowering the tracking speed of the frequency error because the change due to noise is also a large value. In addition, the reason for using the IIR filter is to prevent a sudden frequency change and to gradually increase or decrease the frequency. The output of this IIR filter corresponds to any value proportional to the frequency error. Therefore, a process for mapping a value proportional to the frequency error that is the output of the loop filter 86 into a frequency 1: 1 is required. For this purpose, a frequency mapper 90 is provided at an output of the digital signal processor 80. Located.

The frequency mapper 90 maps the output of the loop filter 86 and the hopping address of the ROM table to be described later. The ROM table is included in the frequency error compensation signal generator 100. The ROM table includes frequency error compensation signals for compensating the output of the normalized frequency error detector 40 corresponding to one period of one sinusoidal curve. Saving. The normalized output characteristic curve of this frequency error detector 40 is shown in FIG. 4. If the output of the normalized frequency error detector 40 in FIG. 4 is 0.6, the frequency error is about 1500 Hz. Therefore, if the frequency error compensation signal for compensating for the 1500 Hz frequency error is stored in the ROM table, the corresponding frequency error compensation signal is output for each symbol by the hopping address output by the frequency mapper 90. The frequency error compensation signal is applied to the multiplier 34 as a complex signal and used to compensate the frequency error component of the received signal. For reference, if the frequency error is large, the leap interval in the ROM table should be large. If the frequency error is small, the leap interval should be small. And the frequency detected by the frequency mapper 90 In the ROM table Wow Is output. The size of the frequency mapper 90 and the ROM table described above is preferably determined according to the resolution of the compensable frequency error. The output characteristic of the normalized frequency error detector 40 is shown in FIG.

On the other hand, the gain adjusting unit 88 accumulates the output of the accumulator 84 by one frame period or more in order to minimize the influence of noise, and varies the gain of the loop filter 86 according to the accumulation value. That is, since the accumulated value corresponds to the frequency, the gain adjusting unit 88 switches to the capture mode when the accumulated frequency is greater than or equal to the preset first reference value (500 Hz), and the gain of the loop filter 86 as a coefficient of the capture mode. When the accumulated frequency is a value between the preset first reference value and the second reference value (50 Hz), the mode is switched to the tracking mode to vary the gain of the loop filter 86 by the coefficient of the tracking mode. If the accumulated frequency is less than or equal to the second reference value, the operation mode is switched to the stop mode and the gain of the loop filter 86 is varied by the stop mode coefficient.

FIG. 5 is a diagram briefly illustrating a multi-stage tracking mode of an apparatus for automatically tracking frequency according to an embodiment of the present invention. According to the control of the gain adjusting unit 88, the automatic frequency tracking control apparatus according to the embodiment of the present invention, as shown in Figure 5, the initial mode, acquisition mode (acquisition mode), tracking mode (tracking mode) and stop mode ( It is divided into stop mode. The initial mode is set at the beginning of the operation of the automatic frequency tracking control device to measure the frequency error of the received signal. The operation mode is sequentially changed by comparing the frequency error measured in the initial mode with preset reference values. If the frequency error is 50 Hz or less, the operation mode is changed to the stationary mode and the loop filter 86 gain is close to " 0 ". The frequency compensator stops the frequency error compensation, and the channel compensator (not shown) compensates for the remaining frequency error.

Through setting and switching of the above-described operation mode, it is possible to compensate for the degradation in tracking performance due to the use of the normalization block.

Referring to the operation of the frequency automatic tracking control device having the above-described configuration, first, when a signal transmitted from the mobile station is received by the receiver, the received signal is despread by the scrambling code and input to the accumulator 32. The accumulator 32 accumulates 256 chips corresponding to the spreading factor (SF = 256) of the DPCCH and converts the symbols into symbols. The transformed pilot symbol is passed through the moving average filter 36 to remove noise, and is then input to the frequency error detector (FDD) 40 and the received signal amplitude detector 60 by the splitter 42 to receive the received signal amplitude component. And a frequency error component. The received signal amplitude component and the frequency error component are respectively input to the divider 82 of the DSP 80, so that the frequency error component is normalized by the received signal amplitude component.

Meanwhile, the output of the normalized frequency error detector (FDD) 40 is input to the loop filter 86 after the noise is removed through the accumulator 84. In the loop filter 86, the gain g of the initial mode under the control of the gain adjusting unit 88 is added to perform infinite accumulation, and the frequency mapper 90 receiving the output of the loop filter 86 is looped. By mapping the output of the filter 86 and the hopping address of the ROM table, the frequency error compensation signal generator 100 having the ROM table outputs the frequency error compensation signal stored at the hopping address and applies it to the multiplier 34. do.

Accordingly, the frequency error of the received signal is gradually compensated for by the multi-step tracking mode performed under the control of the gain adjusting unit 88.

FIG. 6 is a diagram illustrating a configuration of a plurality of frequency automatic tracking control apparatuses in which a frequency error combiner 110 and a received signal amplitude combiner 120 are inserted as another embodiment of the present invention. And a frequency error combiner 110 between the frequency error detector (FDD) 40 and the DSP 80 to synthesize the amplitude of the received signal, and the received signal between the received signal amplitude detector 60 and the DSP 80. Connect the amplitude combiner 120. The transmission signal of the terminal arrives at the base station receiver with multiple paths. The base station receiver detects a frequency error for each multipath, but the frequency error component detected in a signal divided for each multipath has a very small value. This results in a relatively slow compensation of the frequency error. As shown in FIG. 6, when the frequency error signal detected for each multipath is combined, the frequency error detector output closest to the actual frequency error can be obtained, so that frequency error tracking can be performed quickly. The reason for combining the output of the received signal amplitude detector is also from the same reason.

Hereinafter, the simulation results of the automatic frequency tracking control device according to an embodiment of the present invention will be described with reference.

First, for the computer simulation, the number of pilot symbols per slot of the DPCCH was set to 5, the DPDCH was randomly generated, and the orthogonality between the DPDCH and the DPCCH was maintained using the OVSF code. In addition, the uplink scrambling code is a complex scrambling code obtained by performing a modular 2 operation with two 25 shift register strings each. As the gold code of the period, 38400 chip length short codes are used for the uplink DPDCH and DPCCH. The cumulative section of the accumulator 32 is set to 256 chips, the cumulative section of the accumulator 84 is set to 6 (= 2 slots), and the resolution of the compensated frequency is set to 10 Hz. In addition, simulation was performed assuming only AWGN channel.

In the simulation described above, a diagram showing the output of the frequency error detector 40 with respect to the frequency error is shown first in FIG. The output of this frequency error detector 40 becomes a major parameter for determining the values of the frequency mapper 90.

On the other hand, when looking at the tracking time performance for the frequency error, we first simulated by varying the loop filter 86 gain in the channel environment with Ec / No of -27dB to obtain the tracking time performance for the frequency error. The use of blocks was compared. In addition, the frequency error was set to 1500 Hz to represent the compensated frequency, showing the tracking time performance against the frequency error.

7 and 8 are graphs showing frequency error compensation characteristics depending on whether AGC and a normalization block are used. Referring to FIGS. 7 and 8, it can be seen that if the loop filter gain g1 is reduced, tracking time for frequency error is large, but it is excellent in terms of tracking accuracy. As shown in FIGS. 7 and 8, when the AGC and the normalization block are used, the tracking time delay for the frequency error is amplified in the step of calculating the power of the received signal in the normalization block. This is the result of outputting fewer values. However, with the use of AGC and normalization block, the FDD 40 output can be obtained without affecting the amplitude of the received signal.

Meanwhile, the jitter performance in the steady state will be described with reference to FIG. 9. First, FIG. 9 is a graph showing jitter performance according to the use of AGC and normalization block. In Fig. 8, the jitter performance is shown to be better when using AGC and normalization block, but when the actual normalized jitter is considered, the jitter performance is lowered because the AGC and normalization block have FDD gain. Can be. However, this is a result of compensating for the disadvantage of being sensitive to the input amplitude of the FDD 40.

Finally, the characteristics of the case where the multi-stage tracking mode is applied will be described. First, FIG. 10 illustrates a frequency error compensation graph when the multistage tracking mode according to the embodiment of the present invention is applied to the automatic frequency tracking control apparatus. The gain of the loop filter 86 used in FIG. 10 was 1/500 in the initial mode, 1/50 in the capture mode, and 1/500 in the tracking mode. Comparing with FIG. 8, it can be seen that the tracking time characteristic of the frequency error is improved.

Accordingly, the present invention uses a normalization block to compensate for the shortcomings of the general frequency error detector 40 shown in FIG. 1, and uses a moving average filter 36 at the input of the FDD 40 to output more FDD during the unit time. This allows fast frequency error tracking at good jitter performance. In addition, frequency offset is compensated for by using the NCO of the address hopping method using the frequency mapper 90 and the ROM table. Although the use of the normalization block reduces the tracking time and jitter performance, Sensitive shortcomings are compensated for, and reduced frequency error tracking performance and steady-state jitter performance can be compensated for by using multi-stage tracking mode to enable fast frequency error tracking.

As described above, the present invention removes the noise component and the amplitude distortion component of the received signal to one-to-one conversion of the frequency error detector output and the frequency error, thereby accurately correcting the tracking of the frequency error, thereby improving the reception performance of the receiver. There is an advantage.

In addition, the present invention compensates that the tracking time of the frequency error is delayed due to the use of the normalization block by employing the multi-stage tracking mode, and as a result, the tracking and compensation of the frequency error can be performed quickly and accurately.

On the other hand, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be defined only by the appended claims.

Claims (11)

In the automatic frequency tracking control, An accumulator for accumulating the despread received signal by the spreading factor of the DPCCH; A moving average filter for removing noise from the output of the accumulator and increasing the number of outputs of the frequency error detector; A frequency error detector for inputting the output of the moving average filter, separating the real component and the imaginary component, and performing a functional calculation on the output of the moving average filter to output a signal proportional to the frequency error of the received signal; A received signal amplitude detection unit for functionally processing the separated real and imaginary components to detect an amplitude distortion component of the received signal; As an output signal of the received signal amplitude detection unit, a signal proportional to a frequency error of the received signal is normalized, and a jump address for mapping a value obtained by adding a gain according to a multi-stage tracking mode to the normalized value is generated and output. A digital signal processor; And a frequency error compensation signal generator which reads from the memory a frequency error compensation signal indicated by the hopping address and multiplies the output signal of the accumulator. The method of claim 1, further comprising a combiner for combining the outputs of the plurality of frequency error detectors and the output signal amplitude detectors, respectively, for detecting the frequency error and the received signal amplitude of the received signal according to the multipath. Features automatic frequency tracking control. The received signal amplitude distortion according to claim 1 or 2, wherein the received signal amplitude portion is obtained by adding a square value of a real component obtained by multiplying an input pilot symbol by a conjugate complex number of one symbol delay output and a square value of the output of the frequency error detector. A frequency automatic tracking control device for detecting the amplitude of the received signal from the square of the component. The method of claim 1 or 2, wherein the digital signal processing unit; A divider for normalizing the output of the frequency error detector to the amplitude of the received signal; An accumulator for accumulating the normalized values to minimize the influence of noise; A loop filter for minimizing the amount of change in frequency by adding gain according to the multi-stage tracking mode to the output of the accumulator; A frequency mapper for mapping the output of the loop filter one to one with a frequency error; A gain adjustment unit for accumulating the output of the accumulator one or more frame periods and comparing the accumulated value with preset reference values to vary the gain of the loop filter; Control unit. The method of claim 4, wherein the gain control unit; If the cumulative value is equal to or greater than the first reference value, the switching mode is changed to the capture mode. The gain of the loop filter is varied by the coefficient of the capture mode. If the cumulative value is a value between the first reference value and the second reference value, the tracking mode is changed. The gain of the loop filter is varied by the coefficient of the tracking mode, and if the accumulated value is less than or equal to the second reference value, the gain of the loop filter is changed by the stop mode coefficient. Control unit. 6. The apparatus of claim 5, wherein the first reference value and the second reference value are 500 Hz and 50 Hz, respectively. The method of claim 4, wherein the frequency error compensation signal generator; And a ROM table storing frequency error compensation signals for compensating each output of the normalized frequency error detector corresponding to one period of one sinusoidal curve. 5. The apparatus of claim 4, wherein the moving average filter is a 1-tap FIR filter and outputs a combined energy value accumulated just as a diffusion factor of the DPCCH and an energy value accumulated immediately before. In the frequency automatic tracking control method, Accumulating the despread received signal by a spreading factor of the DPCCH and converting the received signal into a pilot symbol; Detecting a frequency error and a received signal amplitude of the received signal in the converted pilot symbol, respectively; Normalizing the detected frequency error of the received signal to the received signal amplitude; Adding a gain according to the multistep tracking mode to the normalized value and generating a hopping address for mapping this value to frequency; And compensating for the frequency error by reading a frequency error compensation signal indicated by the generated jump address and multiplying the pilot symbol. 10. The method of claim 9, further comprising removing noise by accumulating the normalized value. The method according to claim 10, wherein if the accumulated normalized value is equal to or greater than a first predetermined reference value, switching to a capture mode adds the gain as a coefficient of a capture mode, and wherein the accumulated normalized value is between the first reference value and the second reference value. If the value is changed to the tracking mode, the gain is added as a coefficient of the tracking mode, and if the accumulated normalized value is less than the second reference value, the gain is switched to the stop mode and the gain is added as the stop mode coefficient. Tracking control method.