JP2002237544A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which restrictions are not generated in the dimension of a semiconductor element to be mounted and in which a plurality of all types of semiconductor elements can be mounted. SOLUTION: A semiconductor device 219 or 222 is provided with a wiring board 216, in which a cavity 216a or an opening 216c is formed into a step shape and a plurality of internal semiconductor devices 211 mounted by using the difference of the step shape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a plurality of semiconductor elements.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of electronic equipment, a multi-chip semiconductor device having a plurality of semiconductor elements has been realized. The multi-chip semiconductor device includes a type in which a plurality of semiconductor elements are arranged in one plane and a type in which a plurality of semiconductor elements are stacked in a thickness direction. The former has a disadvantage that the mounting area of the multi-chip semiconductor device increases because the semiconductor elements are arranged in a plane. On the other hand, in the latter, such inconvenience does not occur because the semiconductor elements are arranged in the thickness direction. Hereinafter, the latter multi-chip semiconductor device will be described.

FIG. 11 is a cross-sectional view of a conventional multi-chip semiconductor device. In FIG. 11, reference numeral 101 denotes a wiring board. On the wiring substrate 101, a lower semiconductor element 102 and an upper semiconductor element 103 are sequentially stacked, and their respective electrode terminals 102a and 103a are connected to the wiring substrate 101 by bonding wires 107, 107,.
Is electrically connected to These lower semiconductor elements 10
Each of the second and upper semiconductor elements 103 is bonded to the wiring substrate 101 and the lower semiconductor element 102 with an adhesive 111.

In FIG. 1, reference numeral 105 denotes a wiring pattern of a wiring board 101, to which solder bumps 104, 104,... Functioning as external connection terminals are joined.
Reference numeral 106 denotes a resin film such as a polyimide film, and 110 denotes a solder resist applied on the wiring pattern 105. Reference numeral 108 denotes a sealing resin for sealing the lower semiconductor element 102, the upper semiconductor element 103, and the bonding wires 107.

[0005]

In order to perform wire bonding to the lower semiconductor element 102, the size of the upper semiconductor element 103 must be smaller than that of the lower semiconductor element 102. This is the upper semiconductor element 103
Is larger than or equal to that of the lower semiconductor element 102, the electrode terminal 102a of the lower semiconductor element 102 is covered by the upper semiconductor element 103, and the electrode terminal 10
This is because it becomes impossible to perform wire bonding on 2a. Thus, in the multi-chip semiconductor device 101, there are restrictions on the size of the lower semiconductor element 102 and the upper semiconductor element 103.

However, if the size of the semiconductor element is limited, there is a disadvantage that the types of semiconductor elements that can be mounted are limited. The present invention has been made in view of the problems of the conventional example, and provides a semiconductor device capable of mounting a plurality of semiconductor elements of any type without limiting the size of the mounted semiconductor element. It is intended to do so.

[0007]

The first object of the present invention is to provide a wiring board in which cavities or openings are provided in a step-like manner, and a plurality of internal parts mounted using steps of the steps. The problem is solved by a semiconductor device having a semiconductor device. Alternatively, according to the second invention, the internal semiconductor device includes a TAB tape or a lead frame in which a semiconductor element is housed, and a terminal portion is provided on a step surface of a stair, and an outer lead portion of the TAB tape or the lead frame. And the terminal portion are electrically connected to each other, the problem being solved by the semiconductor device according to the first invention.

In a third aspect of the present invention, a radiator plate for closing a bottom opening of the opening is joined to the opening of the wiring board, and a lowermost internal portion is provided on the radiator plate exposed in the opening. The problem is solved by the semiconductor device according to the first invention or the second invention, in which the semiconductor device is fixed. Alternatively, in the fourth invention, a radiator plate is joined to a bottom main surface of the cavity among the two main surfaces of the wiring board, according to the first invention or the second invention. To solve the problem.

Alternatively, a plurality of semiconductor devices according to any one of the first to fourth inventions according to the fifth invention are stacked, and the external connection terminals provided in each of the semiconductor devices are connected to each other. Are electrically connected to each other. Next, the operation of the present invention will be described. According to the semiconductor device of the present invention, the semiconductor device includes a wiring substrate having a cavity or an opening provided in a step shape, and a plurality of internal semiconductor devices mounted using the steps of the step.

When the steps of the stairs are used, when the internal semiconductor devices are mounted from the lower stage of the stairs to the upper stage, the mounting space for the internal semiconductor devices can be increased as the position of the upper stage increases. There is no restriction on the size of the semiconductor device. TAB as internal semiconductor device
A semiconductor device mounted on a tape or a semiconductor device mounted on a lead frame is used. A terminal portion is provided on a step surface of the stairs, and the terminal portion is electrically connected to the TAB tape or an outer lead portion of a lead frame.

In this case, the following advantages are obtained as compared with the case where the semiconductor element and the terminal portion are directly joined by the bonding wire. First, in the case of a bonding wire, the distance between the semiconductor element and the terminal portion becomes long, so that adjacent bonding wires are likely to be electrically short-circuited. Since the length of the outer lead portion can be shortened, there is no danger of short circuit. Second, when wiring layers are formed on both sides of the TAB tape, the wiring routing route can be changed even in the TAB tape, and wiring routing in the wiring board can be reduced. Third, it is also possible to mount the chip-shaped electric component on the TAB tape and form the electric component by a printing method.

A heat sink for closing a bottom opening of the opening is joined to the opening of the wiring board, and the lowermost internal semiconductor device is fixed on the heat sink exposed in the opening. good. With this configuration, the heat generated in the lowermost internal semiconductor device is radiated to the outside of the wiring board via the radiator plate. Similarly, of the two main surfaces of the wiring board, the heat radiation may be bonded to the main surface on the bottom surface side of the cavity. This also causes the heat generated in the internal semiconductor device to
Heat is radiated to the outside of the wiring board via the heat sink.

Further, two or more of the above semiconductor devices are stacked,
The external connection terminals of each semiconductor device may be electrically connected to each other.

[0014]

Next, an embodiment of the present invention will be described. Description of Internal Semiconductor Device First, an example of an internal semiconductor device used in the present embodiment will be described with reference to FIGS. Each of FIGS. 1A to 1C is a cross-sectional view illustrating an example of an internal semiconductor device.

The internal semiconductor device 21 shown in FIG.
1 is TAB (Tape-Automated-Bon)
(Ding) The semiconductor device 201 is mounted on a tape 214. The TAB tape 214 generally includes the insulating film 205, the wiring 206, and the resin film 203. The wiring 206 and the resin film 203 are bonded with the adhesive 2
04 are attached to each other. Resin film 203
For example, a flexible film such as a polyimide film may be used, or a relatively hard film made of epoxy glass may be used. On the other hand, the wiring 206 is formed by patterning a copper foil or a copper plating film, and the inner lead portion 20 is formed.
6a and an outer lead portion 206b. In FIG. 1A, the wiring 206 is formed only on one surface of the resin film 203, but the wiring 206 may be formed on both surfaces of the resin film 203.

The resin film 203 has a frame-like shape when viewed from the thickness direction. An outer lead portion 206b projects outside the frame, and an inner lead portion 206a projects inside the frame. The semiconductor element 201 is stored. Although not explicitly shown, the electrode terminals of the semiconductor element 201 are joined to the tip of the inner lead portion 206a by ultrasonic bonding, and are electrically connected to the wiring 206.

The internal semiconductor device 211 thus constructed
Can be manufactured by a known manufacturing technique.
Although not shown in the drawings, the semiconductor element 201 and the inner lead portion 2 are formed like a normal semiconductor device using TAB.
06a may be resin-sealed. Further, the internal semiconductor device 212 shown in FIG. 1B also includes the TAB tape 214 as in the above. In this internal semiconductor device 212,
The bumps 208, 208,... Are joined to the semiconductor element 201, and the semiconductor element 201 and the inner lead portion 206a are electrically joined via the bumps 208, 208,. In this case, the semiconductor element 20
1 and the TAB tape 214 are filled with the adhesive 207, whereby the semiconductor element 201 and the TAB tape 214 are filled.
And are glued. As the adhesive 207, an anisotropic conductive film may be used, or a paste-like adhesive having no conductivity may be used. The bumps 206 and 20
As 6, etc., for example, gold bumps are used.

This internal semiconductor device 212 can also be manufactured by a known technique. On the other hand, the internal semiconductor device 213 shown in FIG.
9 in which a semiconductor element 201 is mounted. In the figure, reference numeral 209c denotes a die pad portion of the lead frame 209, on which the semiconductor element 2 is placed via an adhesive 202.
01 is adhered. Reference numeral 209a denotes an inner lead portion of the lead frame 209, and its tip is electrically connected to an electrode terminal (not shown) of the semiconductor element 201 by wire bonding with a bonding wire 210. The semiconductor element 201 and the bonding wires 210 are sealed with a sealing resin 215, and an outer lead portion 209 b of the lead frame 209 projects outside the sealing resin 215.

The internal semiconductor device 213 thus constructed
Can also be manufactured by a known technique. 3A to 3C illustrate a method for manufacturing a semiconductor device. Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. FIG.
6A to 6C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the embodiment.

First, as shown in FIG. 2A, a wiring board 216 is prepared. As shown in FIG.
16 is provided with a cavity 216a having a stepped cross section. Reference numeral 217 denotes a wiring pattern, which extends to the step surface 216b of the cavity 216a, where it serves as an inner pattern 217a (terminal portion). Such a wiring board 216 is formed by laminating a plurality of wiring boards provided with openings, and each opening of the stacked wiring boards defines the cavity 216a. Then, the wiring pattern of each of the stacked wiring boards becomes the wiring pattern 217. Examples of the individual wiring boards to be laminated include, for example, those made of resin and those made of ceramic. When the wiring board 216 is made of ceramics, the green sheets may be laminated and fired to form the wiring board 216.

Next, as shown in FIG. 2B, the internal semiconductor device 211 is mounted on the first (lowest) step surface 216b. This is performed by electrically connecting the outer lead portion 206b of the internal semiconductor device 211 and the inner pattern 217a exposed on the step surface 216b by ultrasonic bonding or solder connection. Here, the semiconductor element 201 and the inner pattern 217a are interposed without interposing the TAB tape 214 (see FIG. 1A).
It is also conceivable to wire bond directly with
Note that this method has the following disadvantages.

First, in the wire bonding, the bonding wire connecting the semiconductor element 201 and the inner pattern 217a must be substantially straight when viewed from the thickness direction, but the distance between the semiconductor element 201 and the inner pattern 217a is large. , The bonding wire is easily bent, and there is a risk that adjacent bonding wires may be electrically short-circuited.

Second, the wiring is radially formed from the semiconductor element 201 by bonding wires to the inner pattern 217a.
The wiring board 216 must be designed to be large because the wiring is drawn only inside the wiring board 216. However, this causes a disadvantage that the wiring length is increased and the electrical characteristics are deteriorated. On the other hand, when the TAB tape 214 is interposed, the resin film 203 (FIG.
Since the wiring 206 is supported by (a), the outer lead portion 206b can be shortened, and there is no possibility that adjacent outer lead portions 206b are electrically short-circuited.

Furthermore, when a TAB tape 214 having a wiring layer formed on both sides is used, the wiring route can be changed even within the TAB tape 214, so that the wiring length can be shortened and the electrical characteristics can be improved. Thus, the wiring board 216 can be designed to be small. Also, TAB tape 2
By mounting a chip-shaped electric component on 14 or forming an electric component by a printing method, it is also possible to improve electric characteristics.

As described above, the first stage internal semiconductor device 211
Then, as shown in FIG. 3C, the internal semiconductor device 211 is mounted on the second and third step surfaces 216b in the same manner as above using the steps of the stairs. . The number of internal semiconductor devices 211 mounted on one stage may be arbitrary. For example, in the illustrated example, two semiconductor devices 211 are mounted on the third step surface 216b. When a plurality of internal semiconductor devices 211 are mounted in one step, the long TAB tape 214 including the plurality of semiconductor devices 211 may be mounted on the step surface 216b without separating the long TAB tape 214.

Further, it is not necessary to mount the internal semiconductor device 211 on all stages, and in some cases, the internal semiconductor device 2
There may be a stage where 11 is not mounted. Furthermore, the internal semiconductor devices mounted on each stage are the internal semiconductor devices 211.
The internal semiconductor devices 212 and 21 are not limited to
3 may be used. After mounting a desired number of internal semiconductor devices 211, the cavity 216a is filled with a sealing agent 218 such as a resin, and the semiconductor device 21 according to the present embodiment is filled.
9 is completed.

Note that an opening having a stepped cross section may be provided in the wiring board 216 instead of the cavity 216a. A cross section of such a wiring board 216 is shown in FIG.
(A). In FIG. 3A, reference numeral 216c denotes this opening. In the case where the opening 216c is provided, FIG.
As shown in (b), of the two main surfaces of the wiring board 216, a heat dissipation plate 220 for closing the bottom opening is bonded to the main surface on the bottom opening side of the opening 216c via an adhesive 221. The heat sink 220 is made of, for example, SUS (stainless steel), copper, graphite, or the like.

After the heat sink 220 has been joined,
The internal semiconductor device 21 is formed by the same steps as in (b) to (c).
The semiconductor device 2 shown in FIG.
22 is completed. As shown in FIG. 3C, the first-stage (lower-stage) internal semiconductor device 211 is fixed to the heat-radiating plate 220 via the adhesive 221, so that the first-stage (lower-stage) internal semiconductor device 211 is fixed. The heat generated in the internal semiconductor device 211 is radiated to the outside through the heat radiating plate 220.
Since the thermal conductivity of copper is very good, when the heat radiating plate 220 is made of copper, the heat radiating effect of the heat radiating plate 220 is enhanced.

Incidentally, as shown in FIG.
The fins 220 a may be provided on the outer surface 20, and may be exposed to the outer periphery of the wiring board 216. By doing so, the heat radiation effect of the heat radiation plate 220 is enhanced. Similarly, as shown in FIG. 4B, a heat sink 220 is also provided on a wiring board 219 (see FIG. 2A) provided with a cavity 216a.
May be joined. In this case, the heat radiating plate 220 is joined to the main surface on the bottom surface side of the cavity 216a among the two main surfaces of the wiring board 216.

The semiconductor device 219 and the semiconductor device 22
2 to EMI (Electromagnetic Int.)
Reference measures may be taken. To do this, of the wiring patterns 217 (see FIG. 2A) provided on the wiring board 216, the pattern serving as the ground is made solid. Alternatively, the semiconductor device 219 or the semiconductor device 22
A sheet containing ferrite may be stuck around the periphery of 2.

Further, the cavity 216a and the opening 2
The number of 16c is not limited to one. For example,
A wiring board 216 provided with a plurality of cavities 216a and openings 216c may be used, or a wiring board 216 in which cavities 216a and openings 216c are mixed may be used. According to the semiconductor devices 219 and 222 described above, the cross section of the cavity 216a and the opening 216c has a stepped shape, and the internal semiconductor device 211 is mounted using the step of the step. When the step is used, when the internal semiconductor device 211 is mounted from the lower stage of the stairs to the upper stage, the mounting space of the internal semiconductor device 211 can be more marginally increased toward the upper stage, so that the size of the internal semiconductor device 211 is limited. Does not occur. As a result, all types of semiconductor elements 201 included in the internal semiconductor device 211 can be used.
1 can be constructed.

Next, examples of external connection terminals provided on the semiconductor devices 219 and 222 will be described. FIG. 5 is a sectional view in the case where pins 223, 223,... For a single-in-line package are provided as external connection terminals. Each of the pins 223, 223,... Is electrically connected to the wiring pattern 217 of the wiring board 216. FIG. 6 is a perspective view of the semiconductor device 219 in this case. The semiconductor device 219 includes a pin 2
, Or the pins 223, 223,... Are inserted into the wiring holes of the mounting board (not shown) and soldered, thereby electrically and mechanically connecting these sockets and the mounting board. Connected to.

FIG. 7 shows pins 224, 224,... For a dual in-line package as external connection terminals.
It is sectional drawing at the time of providing. These pins 224, 22
Each of the wiring patterns 4,...
17 are electrically connected. The semiconductor device 219 includes:
.. Are inserted into a socket (not shown), and the pins 224 are inserted into wiring holes of a mounting board (not shown).
Are electrically and mechanically connected to these sockets and mounting boards by inserting and soldering 224.

.. May be provided on four sides of the semiconductor device 219 to form a package as shown in FIG. FIG. 9A is a cross-sectional view when solder bumps 226, 226,... Are provided as external connection terminals. In this case, the semiconductor device 222 has a so-called B
It becomes a GA (ball grid array) type semiconductor device.

The solder bumps 226, 226,...
Electrode pad 217 formed on mounting surface of wiring board 216
b, 217b,... The electrode pads 217b, 217b,... Are electrically connected to the wiring pattern 217 inside the wiring board 216. The solder bumps 226, 226,... Are in contact with a mounting board (not shown).
6, 226,... Are electrically and mechanically connected to the mounting substrate.

FIG. 9B shows the above-mentioned solder bump 22.
6, 226,... Are provided with pins 227, 227,... For PGA (pin grid array), and are cross-sectional views when the semiconductor device 222 is a so-called PGA type semiconductor device. . Pins 227, 227, ...
Are the electrode pads 217b, 217
b,... Then, the semiconductor device 22
2 is a pin 2 in a wiring hole provided in a mounting board (not shown).
Are electrically and mechanically connected to the mounting board by inserting and soldering.

FIG. 10 shows the semiconductor device 22 shown in FIG.
2 is a cross-sectional view in a case where two layers are stacked via a socket 228. FIG. In this case, the pins 227, 227,... Are joined to both of the two main surfaces of the lower semiconductor device 222. The socket 228 has through holes 228 a, 22
, And two upper and lower semiconductor devices 222 are provided.
, 227,...
8a, 228a,... Upper and lower pins 22
, A copper plating film 229 is formed on the inner wall of the through hole 228a. The two semiconductor devices 222 are the lower semiconductor device 2
22, pins 227, 227,.
Is electrically and mechanically connected to the mounting substrate by inserting and soldering into a wiring hole provided in the mounting substrate (not shown).

The number of semiconductor devices 222 to be stacked is arbitrary, and is not limited to two stages as shown. Further, a semiconductor device 219 is used instead of the semiconductor device 222.
Or the semiconductor device 219 and the semiconductor device 222 may be stacked.

[0039]

As described above, according to the semiconductor device of the present invention, a wiring board having a cavity or an opening formed in a step shape and a plurality of internal parts mounted using the step of the step are provided. A semiconductor device. With this structure, there is no restriction on the size of the internal semiconductor device unlike the related art. Therefore, any kind of semiconductor element included in the internal semiconductor device can be used.

As the internal semiconductor device, a semiconductor device having a semiconductor element mounted on a TAB tape or a semiconductor device having a semiconductor element mounted on a lead frame is used. A terminal is provided on the step surface of the cavity or the opening, and the terminal is electrically connected to the TAB tape or the outer lead of the lead frame. In this case, the length of the outer lead portion is shorter than when the terminal portion and the semiconductor element are directly joined by a bonding wire, so that there is a possibility that an adjacent outer lead portion may be electrically short-circuited. In addition, the use of a TAB tape with double-sided wiring can shorten the wiring length, and the electrical characteristics can be improved by forming electrical components on the TAB tape.

Further, a heat sink for closing the bottom opening of the opening may be joined to the opening of the wiring board, and the lowermost internal semiconductor device may be fixed on the heat sink exposed in the opening. . With this configuration, the heat generated in the lowermost internal semiconductor device can be radiated to the outside of the wiring board via the radiator plate. Furthermore, this heat radiation may be joined to the main surface on the bottom surface side of the cavity among the two main surfaces of the wiring board. Also in this case, the heat generated in the internal semiconductor device can be radiated to the outside of the wiring board via the radiator plate.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of an internal semiconductor device used in an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3A is a cross-sectional view of a wiring board provided with an opening having a stepped cross section in the embodiment of the present invention, and FIG. FIG. 3C is a cross-sectional view when the boards are joined, and FIG. 3C is a cross-sectional view when the internal semiconductor device is mounted in the opening of the wiring board.

FIG. 4A is a cross-sectional view of a case where a heat sink is provided on a wiring board having an opening and a fin is provided on the heat sink in the embodiment of the present invention. b)
FIG. 3 is a cross-sectional view when a heat sink is provided on a wiring board having a cavity.

FIG. 5 is a cross-sectional view when a single-in-line pin is provided as an external connection terminal in the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a perspective view when a single-in-line pin is provided as an external connection terminal in the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a cross-sectional view of a case where a dual-in-line pin is provided as an external connection terminal in the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a cross-sectional view of a case where dual-in-line pins are provided as external connection terminals on four sides of the semiconductor device according to the embodiment of the present invention;

FIG. 9A shows a semiconductor device according to an embodiment of the present invention, in which solder bumps are provided as external connection terminals;
FIG. 9B is a cross-sectional view of a GA-type semiconductor device. FIG. 9B shows a PGA-type semiconductor device provided with PGA pins as external connection terminals in the semiconductor device according to the embodiment of the present invention. It is sectional drawing in the case.

FIG. 10 shows a semiconductor device according to an embodiment of the present invention;
It is sectional drawing at the time of carrying out step lamination.

FIG. 11 is a sectional view of a multi-chip semiconductor device according to a conventional example.

[Explanation of symbols]

Reference numeral 101: conventional wiring board 102: lower semiconductor element 102a: electrode terminal of lower semiconductor element 103: upper semiconductor element 103a: electrode terminal of upper semiconductor element 104: 226: solder bump, 105, 217: wiring pattern, 106, 203: resin film, 107, 210: bonding wire, 108, 215: sealing resin, 110: solder resist , 111, 204, 207, 202, 221 ... adhesive, 201 ... semiconductor element, 205 ... insulating film, 206 ... wiring, 206a ... inner lead part of wiring, 206b ... Outer lead portion of wiring, 208: bump, 209: lead frame, 209a: inner lead portion of the lead frame, 09b: outer lead portion of the lead frame; 209c: die pad portion of the lead frame; 211, 212, 213: internal semiconductor device; 214: TAB tape; 216: wiring board;・ Cavity, 216b ・ ・ ・ Step surface, 216c ・ ・ ・ Opening, 217a ・ ・ ・ Inner pattern, 217b ・ ・ ・ Electrode pad, 218 ・ ・ ・ Sealant, 219, 222 ・ ・ ・ Semiconductor device, 220 ・..Heat sink, 220a fin, 223 pin for single in-line package, 224 pin for dual in-line package, 227 pin grid array 228: socket, 228a: through hole, 229: copper plating film, 230: solder.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 25/18 (72) Inventor Takashi Kurihara 711 Rita Kurita, Shano, Nagano City, Nagano Prefecture Shinko Electric Industries, Ltd. F-term (reference) 5F067 AA02

Claims (5)

[Claims] 1. A semiconductor device, comprising: a wiring board having a cavity or an opening provided in a step-like manner; and a plurality of internal semiconductor devices mounted using steps of the step. 2. An internal semiconductor device, wherein a semiconductor element is accommodated in a TAB tape or a lead frame, a terminal portion is provided on a step surface of a stair, and an outer lead portion of the TAB tape or the lead frame and the terminal portion are provided. The semiconductor device according to claim 1, wherein and are electrically connected to each other. 3. A heat sink for closing a bottom opening of the opening is joined to the opening of the wiring board, and a lowermost internal semiconductor device is fixed on the heat sink exposed in the opening. 3. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein a heat radiating plate is joined to a main surface on the bottom surface side of the cavity among the two main surfaces of the wiring board. 5. The semiconductor device according to claim 1, wherein a plurality of the semiconductor devices are stacked, and external connection terminals of each of the semiconductor devices are electrically connected to each other. Semiconductor device.