JP2002236066A - Capacitance type sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitance type sensor capable of obtaining digital output, without such a correction as linearity correction by detecting physical quantity change as capacitance change. SOLUTION: The capacitance type sensor 1 includes a first capacitor 2a detecting the change of physical quantity as a capacitance change, a second capacitor 2b which is to be a differential capacitor together with the first capacitor, a discharge means for accumulating electric charge to be the sum of electric charges, accumulated in the second capacitor and the first capacitor in a third capacitor 31 and repeatedly discharging the electric charge of the difference between the first capacitor charge and the second capacitor charge out of the charge accumulated in the third capacitor, a detection signal outputting means 4 for outputting a detection signal, when the charge in the third capacitor lowered a specific value as the results of the discharge with the discharge means, and a calculation means 7, counting the detection signals for a certain period and calculating physical quantity, based on the signal counts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance type sensor for detecting a change in a physical quantity as a change in capacitance, and in particular, to obtain a high-precision output by digitally converting a change in capacitance. The present invention relates to a capacitance type sensor that can perform the above-described operations.

[0002]

2. Description of the Related Art As a conventional capacitance type sensor, there is, for example, a capacitance sensor device disclosed in Japanese Patent Application Laid-Open No. 10-185970. As shown in FIG. 12, a conventional capacitive sensor device 101 includes a charge balance converter including an operational amplifier 103 in which an integrating capacitor 102 is connected between an output terminal and an inverting input terminal and a non-inverting input terminal is grounded; A first capacitor C1 having a first electrode 104 connected to the voltage U or ground and a second electrode 105 connected to ground or the inverting input terminal of the operational amplifier 103;
Is connected to the voltage U or the ground, and the second electrode 107
Has a second capacitor C2 connected to ground or the inverting input terminal of the operational amplifier 103, a comparator 108 connected to the output terminal of the operational amplifier 103, and a clock generator 109 for controlling a switching process.

In the capacitance sensor device 101, the first switch 110 controls the first electrode 10 of the first capacitor C1.
When 4 is connected to voltage U and the next clock is generated by clock generator 109, first switch 110 switches first electrode 104 of first capacitor C1 to ground. Then, the second electrode 1 is operated by the second switch 111.
When 05 is switched to the inverting input terminal of the operational amplifier 103, the integrating capacitor 102 receives the charge of the capacitor C1. This process is repeated until the output value of the operational amplifier 103 rises to the threshold value of the comparator 108.

Further, when the next clock pulse is output, a switching pulse is given to the third switch 113 and the fourth switch 114 via the first AND circuit 112, and the charge amount stored in the second capacitor C2 is output. Is discharged from the integrating capacitor 102. Therefore, the output value of the operational amplifier 103 decreases, and the output of the comparator returns to the original value. During this time, the timing drive of the first switch 110 and the second switch 111 is performed by the second AND circuit 115.
Has been blocked by

In the capacitance sensor device 101, the comparator 1
08 is proportional to the number n of clock pulses, and is determined by the ratio of C1 and C1 + C2.

(Equation 1) It is expressed as Then, the pulse number z is output as a digital value.

[0006]

However, in the capacitance sensor device 101 described above, the output z is not affected by the change in the capacitance of the first capacitor C1 and the second capacitor C2.
Has a quadratic function and does not have a linear characteristic. Therefore, there is a problem that the output z must be corrected so as to have a linear characteristic.

The present invention has been made in view of the above circumstances, and has as its object to detect a change in physical quantity as a change in capacitance and obtain a digital output that does not require linear correction or the like. It is to provide a capacitance type sensor.

[0008]

In order to achieve the above object, a capacitance type sensor according to the first aspect of the present invention comprises:
A first capacitor for detecting a change in a physical quantity as a change in capacitance, a second capacitor serving as a differential capacitor between the first capacitor and the first capacitor, and a charge stored in the second capacitor and a charge stored in the first capacitor. A discharge in which a charge amount that is a sum of the charge and the charge stored in the third capacitor is repeatedly discharged from the charge stored in the third capacitor as a difference between the charge of the first capacitor and the charge of the second capacitor. Means, a detection signal output means for outputting a detection signal when the amount of charge of the third capacitor is less than a predetermined value after being discharged by the discharge means, and a constant detection signal output by the detection signal output means. Time counting,
Calculating means for calculating the physical quantity based on the number of signals.

According to the first aspect of the present invention, a change in physical quantity is detected as a change in capacitance, and a digital output can be obtained without performing linear correction or the like.

According to a second aspect of the present invention, the discharging means of the capacitance type sensor discharges an electric charge which is a sum of the electric charge stored in the second capacitor and the electric charge stored in the first capacitor. Amplified at an amplification factor of 1 and stored in a third capacitor, and the first charge is stored in the third capacitor.
A charge amount that is a difference between the charge of the capacitor and the charge of the second capacitor is amplified at a second amplification factor and repeatedly discharged;
The first amplification factor is different from the second amplification factor.

According to the second aspect of the present invention, it is possible to increase the amount of charge of the sum of the first capacitor and the second capacitor and to reduce the amount of charge of the difference between the first capacitor and the second capacitor. Therefore, the number of pulses for a change in capacitance can be increased.

According to a third aspect of the present invention, in the capacitance type sensor, the first capacitor and the second capacitor are connected in parallel based on the detection signal output by the detection signal output means. A first timing for charging the first capacitor, a second timing for charging the third capacitor with the amount of charge charged at the first timing,
A third timing at which a capacitor and the second capacitor are connected in series to charge the electric charge, and a charge amount charged at the third timing is calculated from the charge amount of the third capacitor charged at the second timing. It is characterized by further including timing generation means for generating the fourth timing for discharging.

According to the third aspect of the present invention, it is possible to generate the timing for charging / discharging the sum of the first capacitor and the second capacitor and the difference between the first capacitor and the second capacitor. it can. Therefore, since the physical quantity can be calculated using the ratio of the sum charge amount and the difference charge amount, an accurate measurement result can be output without performing linear correction or temperature correction.

According to a fourth aspect of the present invention, in the capacitance type sensor, a sampling and holding circuit is connected between the discharging means and the detection signal outputting means.

According to the fourth aspect of the invention, noise can be cut from the output waveform of the discharging means, and malfunction of the detection signal output means can be prevented.

In the capacitance type sensor according to the present invention, the voltage charged at the first timing and the voltage charged at the third timing are generated by dividing a power supply voltage by a resistor. It is characterized by being performed.

According to the fifth aspect of the present invention, the power supply voltage is canceled out and disappears, so that even if the power supply voltage is changed, it is possible not to affect the pulse characteristics of the output.

According to a sixth aspect of the present invention, in the capacitance type sensor, a voltage charged at the third timing and a voltage charged at the fourth timing can be respectively adjusted.

According to the sixth aspect of the invention, since the offset can be adjusted, the output value can be adjusted to 0 in the initial state.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the configuration of a capacitance type sensor according to a first embodiment will be described with reference to FIG. here,
Pressure will be described as an example of a physical quantity measured by the capacitance type sensor 1.

As shown in FIG. 1, the capacitance type sensor 1
Are two capacitors 2a and 2b serving as differential capacitors in order to detect a change in pressure as a change in capacitance.
, A integrating circuit 3 for integrating the charges stored in the capacitors 2a and 2b of the detecting unit 2 and storing the integrated charge in an output holding capacitor 31, and a predetermined output voltage of the integrating circuit 3. A comparator circuit 4 for comparing with a threshold value, a timing generation circuit 5 for generating a control timing of the integration circuit 3, a clock CK and its inverted signal C
It comprises a clock generator 6 for generating KN and a calculating means 7 for calculating the pressure by counting the timing signal output by the timing generating circuit 5.

Further, the configuration of the detecting section 2 will be described with reference to FIG. The detection unit 2 includes a diaphragm 21 that changes according to the pressure to be measured, an electrode 22 mounted on the glass substrate GU, and an electrode 23 mounted on the opposite glass substrate GU. A capacitor 2a is formed between the electrode 22 and the capacitor 2b, and a capacitor 2b is formed between the diaphragm 21 and the electrode 23.
When the measured pressure is applied to the diaphragm 21, the diaphragm 21 is deformed, and the capacitance Ca of the capacitor 2a changes, and the capacitance Cb of the capacitor 2b changes. However, since the capacitors 2a and 2b are differential capacitors, the capacitance C
a and Cb change in opposite directions, and the total capacitance is kept constant.

Next, the integrating circuit 3 connects the non-inverting input terminal of the operational amplifier 32 to the ground, connects a capacitor 33 having a capacitance Cf between the inverting input terminal and the output terminal, and outputs the output to the output hold. Capacitor C of capacitance C
Is connected. The integrating circuit 3 turns on and off the switches S1, S2,..., S9 at the timings of φ1, φ2, φ3, φ4 generated by the timing generation circuit 5 to charge and discharge the output hold capacitor 31. Do. The voltage V input to the integration circuit 3
r and Vc are generated by dividing the power supply voltage Vcc by a resistor.

Further, in FIG. 1, the voltage Vc is inputted to the switches S2 and S6, but if the same voltage Vc is inputted to the switches S2 and S6, the offset is adjusted in the initial state where the measured pressure is 0. Therefore, there is a problem that the output of the sensor does not become 0 even though the pressure to be measured is 0.

Therefore, the voltage input to the switch S2 is Vca, the voltage input to the switch S6 is Vcb, and these voltages Vca and Vcb are adjusted so as to satisfy the relationship of Vca.Ca-Vcb.Cb = 0. Make the configuration possible.

Thus, the offset can be adjusted in the initial state where the measured pressure is 0, and the output value in the initial state can be adjusted to 0.

Next, the comparator circuit 4 has a non-inverting input terminal connected to the reference potential and an inverting input terminal connected to the integrating circuit 3.
, An inverter 42 that inverts the output of the operational amplifier 41, and a D-type flip-flop 43 whose output is connected to the D terminal.

Next, the timing generation circuit 5 outputs the outputs Q and Q 'of the D-type flip-flop 43 of the comparator circuit 4.
, Φ2, φ3, φ4 by AND of the clock CK generated by the clock generator 6 and the inverted signal CKN.
Are generated. The timings φ1, φ2, φ3, output by the timing generation circuit 5,
FIG. 3 shows a timing chart of φ4.

Next, the calculating means 7 comprises a binary counter 71 for counting the clock CK from the clock generator 6 by a predetermined number of pulses, and φ2 generated by the timing generating circuit 5.
And an up-counter 72 for counting the timing of. Then, while the binary counter 71 counts a fixed number of clocks, the φ2 timing signal output from the timing generation circuit 5 is counted by the up counter to calculate and output a digital value representing the pressure. .

Next, the operation of the capacitance type sensor according to the first embodiment will be described with reference to the drawings.

However, as an example of the physical quantity measured by the capacitance type sensor, a pressure will be described here as an example.

First, when pressure is applied to the diaphragm 21 shown in FIG. 2, the capacitors 2a, 2b
Change the capacitances Ca, Cb.

Here, the initial gaps of the capacitors 2a and 2b are da and db, the areas of the electrodes 22 and 23 are S, the pressure P
Let X be the amount of change in the gap due to
The capacitances Ca and Cb of a and 2b are

(Equation 2) Becomes

When the capacitances Ca and Cb change in this manner, the charge and discharge of the output hold capacitor 31 are performed by the integration circuit 3 at timings φ1 to φ4.

First, at the timing of φ1, the switch S
1, S5, S8 are turned on and other switches are turned off
Therefore, the integration circuit 3 becomes the circuit shown in FIG. 4A, and the charge of Qr = (Ca + Cb) · Vr (2) is stored in the capacitors 2a and 2b by the voltage Vr at the timing φ1.

Then, at the next φ2 timing, the switches S3, S4, S7, S9 are turned on and the other switches are turned off, so that the integrating circuit 3 becomes the circuit shown in FIG. 4 (b), and the capacitors 2a, 2b Charge Q stored in
r is amplified by the operational amplifier 32 and is output to the output hold capacitor 31.

(Equation 3) Of charge _{Q 0} is stored. The output voltage V ₀ of the integrating circuit 3 is

(Equation 4) Becomes

Next, at the timing of φ3, the switch S
2, S7 and S8 are turned on and other switches are turned off
4C, the integration circuit 3 becomes a circuit shown in FIG. 4C. The charge Va1 stores the charge Qa1 = Ca · Vc in the capacitor 2a, and the capacitor 2b stores the charge Qb1 = Cb · 0 = 0. It is stored.

At the timing of φ4, the switch S
When S3, S4, S6, and S9 are turned on and the other switches are turned off, the integrating circuit 3 becomes a circuit shown in FIG. 4D, and charges Qa2 = Ca · 0 = 0 on the capacitor 2a by the voltage Vc. the accumulated charge of the charge Qb 2 = Cb · Vc to the capacitor 2b is stored, whereby the output voltage _{V 1} of the integration circuit 3 has

(Equation 5) From the output hold capacitor 31,

(Equation 6) Charge Q ₁ is being discharged as a.

FIG. 5 shows changes in the output voltage of the integrating circuit 3 at these four timings. As shown in FIG. 5, at the timing of φ1, since the charges are stored in the capacitors 2a and 2b, no voltage is output from the integration circuit 3. Then, at the timing of φ2, the electric charges stored in the capacitors 2a and 2b during φ1 are
2, the electric charge Q ₀ shown in the equation (3) is stored in the output hold capacitor 31, and the output voltage V ₀ shown in the equation (4) is output.

Since the charges are stored in the capacitors 2a and 2b at the timing of φ3, the output voltage of the integrating circuit 3 does not change. At the timing of φ4, the output hold capacitor 31 calculates the equation (6). Charge Q ₁ shown
There is discharged, whereby the output voltage will be lowered by V _1.

The timings of φ3 and φ4 are repeated until the output voltage falls to a predetermined threshold. The comparison as to whether or not the voltage has dropped to the predetermined threshold value is performed by the comparator circuit 4. The output voltage of the integration circuit 3 described above is input to the comparator circuit 4, and is input to the inverting input terminal of the operational amplifier 41 of the comparator circuit 4 and is compared with the reference potential Vth.
When the value falls below h, the process returns to the timing of φ1 again and the next cycle is started.

However, since the output hold capacitor 31 is not reset at the time of moving to the next cycle, some of the stored charges remain without being discharged. Then, the residual voltage Vh as shown in FIG. 5 is outputted by the remaining charge, the residual voltage Vh is to be added to the output voltage V ₀ which the next cycle.

As described above, the residual voltage Vh is successively added to the next cycle without discharging the output hold capacitor 31 in one cycle, so that after several cycles, the residual voltage Vh is increased. Will reach V ₁ , thereby increasing the measurement accuracy of the sensor as compared to the case of resetting each cycle.

For example, when the electric charge of V ₀ = 2 pF is stored and when the electric charge of V ₀ = 2.001 pF is stored, it is difficult to measure the difference between them when resetting is performed every cycle. However, if the residual voltage Vh is added, the output waveform will be different after several cycles, so that the difference between 2 pF and 2.001 pF can be measured.

Next, the output voltage of the integrating circuit 3 becomes equal to the reference potential V
When the value is below th, the comparator circuit 4 causes the operational amplifier 4
1 outputs a detection signal, which is inverted by the inverter 42 and input to the D terminal of the D-type flip-flop 43. The D-type flip-flop 43 outputs outputs Q and Q ′ according to the clock CK from the clock generator 6 and the input of the D terminal. The outputs Q and Q ′ are input to the timing generation circuit 5.

Then, in the timing generation circuit 5, the outputs Q and Q ′ and the clock CK from the clock generator 6 are output.
And a clock CKN which is an inverted signal of the clock CK
, Four timings of φ1, φ2, φ3, and φ4 are generated by the AND circuit shown in FIG. 4 generated by the timing generation circuit 5
FIG. 3 shows a timing chart of the two timings.

The four timings generated by the timing generation circuit 5 correspond to the switches S 1 and S
2,..., S9 are input to the integration circuit 3 as signals for controlling, and the φ2 timing signal is input to the calculation means 7.

The calculating means 7 calculates a physical quantity to be measured, here a pressure, based on the timing signal φ2 and the clock CK from the clock generator 6.

Here, a method of calculating the physical quantity by the calculating means 7 will be described.

First, when the measured pressure P is applied to the diaphragm 21 and the change amount of the gap when the diaphragm 21 changes is X, the capacitances Ca and Cb of the capacitors 2a and 2b are

(Equation 7) It can be expressed as.

Here, the capacitances Ca and Cb are

(Equation 8) Substituting into

(Equation 9) (However, da = db). Here, da + db is a constant, and the change amount X of the gap changes in proportion to the pressure P applied to the diaphragm 21.
Is

(Equation 10) Can be rewritten.

Since the integration circuit 3 is a charge-balanced circuit, the capacitance becomes Ca- at the timing of φ3 and φ4.
The charge amount Qc when the charge is stored at the voltage Vc in the capacitors 2a and 2b that become Cb is the charge when the charge is stored at the voltage Vr in the capacitors 2a and 2b whose capacitance becomes Ca + Cb at the timing of φ1 and φ2. It is an integral multiple of the quantity Qr.

Therefore, the following relationship holds: Qr · m = Qc · n (m and n are integers) (10) For example, in the staircase waveform shown in FIG.
Since the waveform has five descending stairs, V ₀ = 5 · V
₁ holds, and the charge also holds the relationship Qr = 5 · Qc.

Here, the charge amounts Qr and Qc are as follows: Qr = Vr · (Ca + Cb) (11) Qc = Vc · (Ca−Cb) (12) ) And from

[Equation 11] Becomes Therefore, from equations (9) and (13),

(Equation 12) Can be summarized. Here, Vr and Vc are constant voltages, respectively, and n is Qc = (Ca−Cb) · Vc
Is the same as the number of pulses of the clock CK, and m is the number of times the charge amount of Qr = (Ca + Cb) · Vr is stored. Therefore, it is the same as the number of timing signals of φ2. That is, if the number of clocks CK counted in advance by the binary counter 71 is set, the number of clocks becomes n, and the timing of φ2 output from the timing generation circuit 5 within the time set by the number of clocks n The signal is counted by the up counter 72, and this number becomes m.

Therefore, the constants Vr, V
By inputting c and setting and inputting the clock number n, the pressure P can be output as a digital value from the number m of the φ2 timing signals counted by the up counter 72.

For example, when a pressure of 5 mmH ₂ O is applied to the diaphragm 21, the capacitance C of the capacitor 2a is reduced.
a is 11 pF and the capacitance Cb of the capacitor 2b is 9 pF
When Vr = 1.5V, Vc = 3V, Cf =
Assuming 10 pF, V ₀ and V ₁ shown in FIG.

(Equation 13) Can be calculated. Thereby, 3V / 0.6V
= 5, it can be seen that the waveform of the output voltage of the integrating circuit 3 is a five-step staircase waveform as shown in FIG. In the case of a five-step staircase waveform, six clocks constitute one cycle.
When the clock is set to be counted, the relationship between the clock CK and the staircase waveform as shown in FIG. 6 is obtained.

When this relationship is input to equation (14), α is a value obtained in advance through experiments or the like.

[Equation 14] Can be requested. That is, the number of timing signals of φ2 (the number of staircase waveforms) corresponds to a pressure value of 5 mmH ₂ O.

Therefore, while the binary counter 71 counts 30 clocks, the number of φ2 timing signals output is counted and output by the up counter 72, so that the pressure value to be measured is output as a digital value. can do.

As described above, according to the capacitance type sensor of the first embodiment, the capacitors 2a,
The change in the capacitance 2b can be output as a digital value.

Further, according to the capacitance type sensor of the first embodiment, since the physical quantity is calculated by using the ratio of (Ca-Cb) / (Ca + Cb), linear correction, temperature correction, and the like can be performed. And accurate measurement results can be output.

Since the capacitors 2a and 2b have a differential structure, the change in capacitance of the capacitors 2a and 2b can be increased by using Ca-Cb as the numerator of the calculation formula. That is, when the capacitance of the capacitor 2a changes to Ca ′ = Ca + α due to the differential structure, the capacitance of the capacitor 2b changes to Cb ′ = Cb−α. Therefore, (Ca-Cb) / (Ca + Cb)
Substituting Ca ′ and Cb ′ into the equation (Ca−Cb) / (Ca + Cb) = 2α / (Ca + C
b) and the change α in the capacitance can be doubled. Therefore, in the capacitance type sensor according to the first embodiment, the measurement accuracy can be further increased.

Further, in the capacitance type sensor according to the first embodiment, Vr,
Although Vc is used, by increasing Vr and decreasing Vc, the number of pulses output for a change in capacitance can be increased, so that the measurement accuracy can be further increased.

Vr and Vc are generated by dividing the power supply voltage Vcc by a resistor. Therefore, Vc = Vcc · (R1 / R2) Vr = Vcc · (R3 / R4), and when these are substituted for Vr and Vc in equation (14), α · P · (Vc / Vr) = m / n α · P · {Vcc · (R1 / R2)} / ｛Vcc · (R
3 / R4)｝ = m / n α · P · (R1 · R4) / (R2 · R3) = m / n

As described above, in the equation (14), the power supply voltage Vcc is canceled out and disappears. Therefore, in the capacitance type sensor of the first embodiment, even if the power supply voltage Vcc is changed, the output pulse characteristics are not changed. Can be unaffected.

Next, the configuration of the capacitance type sensor according to the second embodiment will be described with reference to FIG.

As shown in FIG. 7, the capacitance type sensor 81 of the second embodiment has a static capacitance between the inverting input terminal and the output terminal of the operational amplifier 32 of the integrating circuit 3 of the first embodiment. The difference from the first embodiment is that the capacitor 82 having the capacitance Cf 'and the switch S10 are connected.

As described above, by connecting the capacitor 82 and turning on the switch S10 at the timing of φ4, the electric charges Q ₀ and Q ₁ shown in the equations (3) and (6) become respectively

(Equation 15) Becomes Therefore, according to the electrostatic capacity-type sensor 81 of the second embodiment, it is possible to it is possible to increase the charge amount Q _0, decreasing the amount of charge Q _1.

Therefore, the number of pulses for a change in capacitance can be increased, so that the measurement accuracy can be further improved.

Next, the configuration of the capacitance type sensor according to the third embodiment will be described with reference to FIG.

As shown in FIG. 8, the capacitance type sensor 91 of the third embodiment is different from the first embodiment in that a sampling and holding circuit 92 is connected between the integrating circuit 3 and the comparator circuit 4 in the first embodiment. This is different from the first embodiment.

In the capacitance type sensor according to the first embodiment,
In some cases, a whisker-like noise as shown in FIG. 9 occurs in the waveform of the output voltage of the integrating circuit 3, and this noise causes a malfunction in the comparator circuit 4.

Therefore, in the capacitance-type sensor 91 of the third embodiment, a sampling and holding circuit 92 is connected between the integrating circuit 3 and the comparator circuit 4 to cut off whisker-like noise. As shown in FIG. 10, the whisker-like noise N occurs at the rise and fall of the output waveform of the integration circuit 3, so that the sampling and holding circuit 92
In this example, a timing pulse P is generated at a timing delayed by a predetermined time t from the rise and fall of the output waveform, and sampling and holding are performed.

As a result, the output waveform of the integrating circuit 3 becomes a waveform from which the whisker-like noise has been cut as shown in FIG. 11, and the malfunction of the comparator circuit 4 can be prevented.

[0074]

As described above, according to the capacitance type sensor of the present invention, a change in physical quantity can be detected as a change in capacitance, and a digital output can be obtained without performing linear correction or the like. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a capacitance type sensor according to the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a detection unit 2 shown in FIG.

FIG. 3 is a timing chart for explaining a timing signal generated by a timing generation circuit 5 shown in FIG. 1;

4 is a circuit diagram for describing a configuration at each timing of an integrating circuit 3 shown in FIG.

FIG. 5 is a diagram showing an example of a staircase waveform output by the integration circuit 3 shown in FIG.

FIG. 6 is a timing chart for explaining an example of an output signal from a calculating means 7 shown in FIG. 1;

FIG. 7 is a block diagram showing a configuration of a second embodiment of the capacitance type sensor according to the present invention.

FIG. 8 is a block diagram showing a configuration of a third embodiment of the capacitance type sensor according to the present invention.

9 is a drawing showing an output waveform of the integration circuit 3 shown in FIG.

FIG. 10 is a drawing for explaining sampling and holding by the sampling and holding circuit 92 shown in FIG. 8;

FIG. 11 is a drawing showing an output waveform of the integration circuit 3 after the sampling and holding circuit 92 is connected.

FIG. 12 is a circuit diagram for explaining a configuration of a conventional capacitance sensor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 81, 91 Capacitance sensor 2 Detection part 2a, 2b, 33, 82 Capacitor 3 Integrator circuit 4 Comparator circuit 5 Timing generation circuit 6 Clock generator 7 Calculation means 21 Diaphragm 22, 23 Electrode 31 Output hold capacitor 32 , 41 Operational amplifiers S1, S2,..., S10 Switch 42 Inverter 43 D-type flip-flop 71 Binary counter 72 Up counter 92 Sampling and holding circuit

Claims (6)

[Claims] A first capacitor for detecting a change in a physical quantity as a change in capacitance; a second capacitor serving as a differential capacitor between the first capacitor and the first capacitor; a charge stored in the second capacitor; A third capacitor stores a charge amount that is a sum of the charge stored in the capacitor and a charge amount that is a difference between the charge of the first capacitor and the charge of the second capacitor from the charge stored in the third capacitor. Discharging means for repeatedly discharging, a detection signal outputting means for outputting a detection signal when the amount of charge of the third capacitor falls below a predetermined value by being discharged by the discharging means, and a detection signal output means for outputting the detection signal. Calculating means for counting the detection signal for a certain period of time and calculating the physical quantity based on the number of signals. 2. The method according to claim 1, wherein the discharging means amplifies a charge amount, which is the sum of the charge stored in the second capacitor and the charge stored in the first capacitor, at a first amplification factor, and amplifies the charge amount to a third capacitor. Storing, amplifying, by a second amplification factor, a charge amount that is a difference between the charge of the first capacitor and the charge of the second capacitor from the charge stored in the third capacitor, and repeatedly discharging the first capacitor; The capacitance type sensor according to claim 1, wherein an amplification factor is different from the second amplification factor. 3. A first timing in which the first capacitor and the second capacitor are connected in parallel to charge an electric charge based on the detection signal output by the detection signal output means; A second timing for charging the third capacitor with the amount of charge charged in the third step, a third timing for connecting the first capacitor and the second capacitor in series to charge the electric charge, and charging at the third timing. 3. The apparatus according to claim 1, further comprising a timing generation unit configured to generate a fourth timing for discharging the charged amount from the charge amount of the third capacitor charged at the second timing. 4. Capacitive sensor. 4. The capacitance type sensor according to claim 1, wherein a sampling and holding circuit is connected between said discharging means and said detection signal output means. 5. A voltage to be charged at the first timing,
The capacitance sensor according to claim 3, wherein the voltage charged at the third timing is generated by dividing a power supply voltage by a resistor. 6. A voltage charged at the third timing,
6. The capacitance-type sensor according to claim 3, wherein a voltage charged at the fourth timing is adjustable.