JP2002232744A - Image processing method and image processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow suppressing an overshoot with a simple circuit configuration having a small number of gates and acquiring a desired outline compensation characteristic without generating ringing or a deformation of the waveform. SOLUTION: An absolute value A of a first order difference, which is the difference of data value between a certain pixel and a pixel one clock previous to it, and polarity are detected for digital input brightness data Yin by a first order difference detecting circuit 10. The absolute value A of the first order difference is encoded to an encoded signal of a predetermined number of bits by a first order difference coding circuit 20. The coded signal of the first order difference is added to or subtracted, from the original brightness data Yin depending on the polarity as the outline compensation component F with a smaller gain for a larger coding signal when the first order differential component is negative, by means of an outline compensation control circuit 40, a gain level adjusting circuit 50, an outline compensation component generation and selection circuit 60, and an outline compensation component superinterposing circuit 70.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a DVD (Dig).
ital Video Disc, Digital V
ersatile Disc) player and digital T
The present invention relates to a method and apparatus for video processing in a V (Television) receiver or the like.

[0002]

2. Description of the Related Art As a method of compensating (emphasizing) the outline of an image in a TV receiver or the like, conventionally, a high-frequency component of an original signal is extracted as an outline compensation component by analog processing, and this is converted into an original signal. The method of superimposing is widely used.

Further, as contour compensation by digital processing, an FIR (Finite Impulse Resp) is used.
A method has been considered in which a high-frequency component of the original signal is extracted as a contour compensation component using an onse) filter and is superimposed on the original signal.

[0004]

However, in contour compensation by analog processing, it is difficult to compensate for the high-frequency component lost due to the group delay characteristic of the signal, and ringing occurs due to temperature characteristics and the like, and the waveform is reduced. In some cases, a defect such as distortion occurs and the image quality is deteriorated.

Further, in the case of analog processing, there is a disadvantage that overshoot and preshoot increase as the contour emphasis increases.

In contour compensation by digital processing using an FIR filter, ringing occurs when the FIR filter has a steep cutoff characteristic, and conversely, when the FIR filter has a gentle cutoff characteristic, the amount of attenuation in a cutoff region. However, there is a drawback that it is not sufficient and cannot be used as an image filter.

Further, when an FIR filter is used, the configuration of the filter must be changed depending on the sampling frequency of the signal and the cutoff frequency of the filter, and the number of taps and coefficients must be changed in order to obtain a desired contour compensation characteristic. However, there is a disadvantage that the configuration becomes complicated and the cost increases.

Therefore, according to the present invention, overshoot can be suppressed by a simple circuit configuration with a small number of gates.
A desired contour compensation characteristic can be obtained without causing ringing or waveform distortion.

[0009]

According to the contour compensation method of the present invention, an absolute value and a polarity of a primary difference, which is a difference of a data value between a certain pixel and a pixel one clock before, are detected from digital luminance data. In addition, the absolute value of the primary difference is encoded into a coded signal of a predetermined bit, and the coded signal is converted into a smaller gain as the coded signal is larger, and as a contour compensation component, the polarity of the first difference is Accordingly, when the primary difference is positive, it is added to the original luminance data, and when the primary difference is negative, it is subtracted from the original luminance data.

In the above method, 1
In addition to detecting the secondary difference and its polarity, the primary difference is encoded into an encoded signal having a predetermined number of bits to generate a contour compensation component that is more suitable for the luminance signal, so that ringing and waveform distortion do not occur. A desired contour compensation characteristic can be obtained, and a simple circuit configuration with a small number of gates can be achieved. Furthermore, since the encoded signal of the primary difference is superimposed as a contour compensation component with a smaller gain as the encoded signal of the primary difference is larger, overshoot can be suppressed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment of Contour Compensation Device and Contour Compensation Method ... FIGS. 1 to 12] FIG. 1 shows an embodiment of a contour compensation device according to the present invention, and FIGS. An example of a circuit of each unit is shown.

Luminance data Yi input to the contour compensator
n is an ITU (International Tele Telephone)
communication Union) Recommendation ITU
-RBT. The sampling frequency fs specified in 601 is 13.5 MHz, "16: black level, 235:
It is 8-bit data of "white peak level".

The contour compensating apparatus according to this embodiment has a primary difference detecting circuit 10, a primary difference encoding circuit 2 as a whole.
0, contour compensation control circuit 40, gain level adjustment circuit 5
0, a contour compensation component generation / selection circuit 60, a contour compensation component superposition circuit 70, and a limiter 80.

(Primary difference detection--FIGS. 2 and 8) In the primary difference detection circuit 10, 1
The absolute value and polarity of the next difference are detected.

Assuming that a certain pixel is a target pixel and a pixel one clock before it is an adjacent pixel, the primary difference is a target pixel value Yq and an adjacent pixel value Yp as shown in FIG. 8A or 8B. (Yq−Yp). Therefore, the absolute value of the primary difference is represented by A = | Yq−Yp |, and the polarity of the primary difference is positive if Yq> Yp as shown in FIG. If Yq <Yp as in B), it is negative.

In the primary difference detection circuit 10, the luminance data Y
in, that is, the luminance data Yi
The absolute value A and the polarity of the primary difference are detected with each pixel value of n as a target pixel value.

Specifically, as shown in FIG. 2, the input luminance data Yin is delayed by one clock by a DFF (D flip-flop) 11, and the output data Y1D of the DFF 11 is further delayed by one clock by a DFF 12.
The output data Y1D of the DFF 11 is used as one input of the selectors (switches) 13, 14 and the comparator 15, and the output data Y2D of the DFF 12 is used as the selector 13,
The selector 13 is switched by the output signal DA of the comparator 15 as the other input of the comparator 14 and 14, and the selector 14 is switched by a signal obtained by inverting the output signal DA by the inverting circuit 16.

When P> Q, the comparator 15 determines that P>
When QN = Low (low level output) and P ≦ Q, P>
This is a logic circuit where QN = High (high-level output).

Accordingly, at time tc as shown in FIG. 8A, Y1D> Y2D, that is, when Q> P, the signal DA becomes high level, and at time tc as shown in FIG. , Y2D> Y1D, that is, P>
By being Q, the signal DA becomes low level,
The signal DA detects whether the luminance data Yin is increasing and the primary difference is positive or the luminance data Yin is decreasing and the primary difference is negative for the pixel having the pixel value Yq. You.

When the signal DA goes high,
That is, when the first-order difference is positive, the selectors 13 and 14 are switched to the states shown in FIG.
When the data Y1D is taken out from the selector 13 and the data Y2D is taken out from the selector 14, and when the output signal DA is at a low level, that is, when the first-order difference is negative, the selectors 13 and 14 are brought into the states shown in FIG. Is switched to the opposite state, and selector 1
3 and the data Y2D from the selector 14
Are respectively taken out. That is, regardless of the polarity of the primary difference, the larger one of the data Y1D and Y2D is extracted from the selector 13, and the smaller one is extracted from the selector 14.

Further, the larger data from the selector 13, the data obtained by inverting each bit of the smaller data from the selector 14 by the inverting circuit 17, and 1 of the carry input Cin are added by the adding circuit 18. And adder circuit 1
From 8, the absolute value A of the primary difference as a result of subtracting the smaller data from the larger data is obtained.

(Encoding of the absolute value of the primary difference: FIGS. 3 and 9) In the primary difference encoding circuit 20, the absolute value A of the primary difference obtained by the primary difference detecting circuit 10 is converted into a 4-bit value. The signal is converted into a primary differential encoded signal (primary differential encoded signal) ED composed of a binary code.

More specifically, as shown in FIG. 3, the absolute value A of the primary difference is input to 16 comparators 21 to 36, and the comparators 34h, 32h, 30h, 2Eh, and 2C respectively.
h, 2Ah, 27h, 24h, 21h, 1Eh, 1B
h, 18h, 14h, 10h, 0Ch, and 08h. Here, the lowercase letter h in the alphabet is a hexadecimal number (Hexadecimal N).
members) expression.

That is, as shown in FIG. 3, the comparators 21 to 36 receive the absolute value A of the primary difference at the P terminal and the respective thresholds (Threshold) at the Q terminal.
d) is input. Then, when P> Q (the absolute value of the primary difference A> threshold), a signal at a high level (“1”) is output. When P> Q, a signal at a low level (“0”) is output. And outputs the respective signals to the priority encoder 37.

The priority encoder 37 has a 16
The most significant of the data inputs is detected, and a 4-bit binary code, that is, a primary differential encoded signal E is detected.
D. Therefore, the primary differential encoded signal E output from the priority encoder 37
As shown in FIG. 9, D increases as the absolute value A of the primary difference increases.

Although the thresholds supplied to the comparators 21 to 36 are different for each comparator as shown in FIG. 3, the threshold differences between the comparators 21 to 26 are different. Is set to “2”, and the difference between the thresholds of the comparators from the small pattern 26 to the comparator 32 is set to “3”. Further, the comparator 32
The difference between the threshold values of the comparators from the comparator to the comparator 36 is set to “4”.

(Contour Compensation Control: FIGS. 4 and 10) The contour compensation control circuit 40 is capable of controlling contour compensation depending on which of the image sense of detail and noise is important. When the coring level is set from the outside and the coring on / off is set, and the coring on is set, the absolute value A of the primary difference obtained by the primary difference detection circuit 10 is: When the coring level is equal to or higher than the set coring level, contour compensation is performed. When the absolute value A of the primary difference is smaller than the set coring level, the absolute value A of the primary difference is regarded as a minute noise component. When contour compensation is not performed and coring off is set, contour compensation is performed regardless of the relationship between the set coring level and the absolute value A of the primary difference. Than it is.

More specifically, as shown in FIG. 4, the set coring level value AC is used as one input of a comparator 41, and the absolute value A of the primary difference from the primary difference detection circuit 10 is compared with the comparator 41. 41 is the other input. The comparator 41 is the same logic circuit as the comparator 15 in FIG. 2. The comparator 41 inputs the output signal FC and the coring on / off signal determined by the coring on / off setting to the OR gate 42, and superimposes the output signal FCT of the OR gate 42 on the contour compensation component superposition. Take it out as a limit signal.

Therefore, when the coring on is set and the coring on / off signal is set to the low level, the absolute value A of the primary difference becomes the coring level value AC as shown in FIG. If it is smaller, the output signal FC of the comparator 41 becomes low level, and the contour compensation component superimposition limiting signal FCT becomes low level, and contour compensation is not performed as described later.

On the other hand, even when the coring on is set and the coring on / off signal is set to a low level, the absolute value A of the first-order difference is equal to the coring level value as shown in FIG. When AC or more, the output signal FC of the comparator 41 becomes high level, the contour compensation component superimposition limit signal FCT becomes high level, and contour compensation is performed. When coring off is set and the coring on / off signal is set to a high level, regardless of whether the absolute value A of the primary difference is smaller than the coring level value AC, the contour compensation component superimposition is performed. The limit signal FCT becomes high level, and contour compensation is performed.

(Gain Level Adjustment--FIG. 5) The gain level adjustment circuit 50 is provided with a gain level set for the gain level adjustment circuit 50 from outside the contour compensator and a primary difference from the primary difference encoding circuit 20. Coded signal ED
Is extracted as the superimposed gain level of the contour compensation component, and when the contour compensation component superimposition limit signal FCT from the contour compensation control circuit 40 is at a low level indicating coring on, the contour compensation component Is set to zero.

More specifically, as shown in FIG. 5, a 4-bit gain level setting signal G indicating the set gain level is provided.
L and the 4-bit 1 from the primary differential encoding circuit 20.
A signal obtained by inverting each bit of the next difference coded signal ED by the inversion circuit 51 and 1 of the carry input Cin are added by the addition circuit 52, and the first difference is obtained from the addition circuit 52 from the gain level setting signal GL. As a result of subtraction of the encoded signal ED, a 4-bit signal GC is obtained.

Therefore, the output signal GC of the addition circuit 52
Is smaller as the absolute value A of the first-order difference is larger and the first-order difference encoded signal ED is larger, so that unnatural emphasis can be suppressed.

Further, the output signal GC of the adder circuit 52 and
The contour compensation component superimposition limiting signal FCT from the contour compensation control circuit 40 is input to the AND gate 53, and the AND gate 5
3 is taken out as a gain level adjustment signal.

Therefore, coring on is set (coring on / off signal is set to low level) and 1
When the absolute value A of the next difference is smaller than the coring level value AC, the contour compensation component superimposition limiting signal FCT becomes low level, and the gain level adjustment signal GCT becomes independent of the output signal GC of the addition circuit 52. "0000", but if coring on is set (coring on / off signal is set to low level) and the absolute value A of the primary difference is equal to or greater than coring level value AC, or coring off is set. (The coring on / off signal is set to a high level), the contour compensation component superimposition limit signal F
When CT becomes high level, the output signal GC of the adding circuit 52 becomes the gain level adjustment signal GCT as it is.

(Contour Compensation Component Generation Selection--FIG. 6) In the contour compensation component generation selection circuit 60, 16 gain levels including zero are obtained from the absolute value A of the primary difference obtained by the primary difference detection circuit 10. Are generated, and the gain level adjustment signal G from the gain level adjustment circuit 50 is generated.
One corresponding to the value of CT is selected as the contour compensation component F to be superimposed on the input luminance data Yin.

More specifically, as shown in FIG. 6, the absolute value A of the primary difference from the primary difference detection circuit 10 is sequentially bit-shifted one bit at a time by the bit shifters 61, 62, 63 and 64. Shift to 0.5A, 0.25 respectively
A, data of values of 0.125A and 0.0625A are generated, and two, three, or four of the four data are added by an adding circuit 65, as shown in FIG. 0.9375A, 0.875A, 0.81 respectively
25A, 0.75A, 0.6875A, 0.625A,
0.5625A, 0.4375A, 0.375A, 0.
Data of values 3125A and 0.1875A are generated, and 16 data including data of a fixed value of 0 are obtained.

In the selector 66, when the gain level adjustment signal GCT is "1111",
When data having a value of 0.9375A is selected and the gain level adjustment signal GCT is “1110”, 0.87
5A is selected and the gain level adjustment signal GC is selected.
When T is "0000", data having a value of 0 is selected, and so on.
A, 0.8125A, 0.75A, 0.6875A,
0.625A, 0.5625A, 0.5A, 0.437
5A, 0.375A, 0.3125A, 0.25A,
0.1875A, 0.0125A, 0.0625A, 0
Gain level adjustment signal GC in 16 data of
One corresponding to the value of T is selected as the contour compensation component F.

Therefore, coring on is set,
When the absolute value A of the first-order difference is smaller than the coring level value AC, the gain level adjustment signal GCT becomes “00”.
By setting to 00 ”, the contour compensation component F becomes 0, but the coring on is set and the absolute value A of the primary difference is equal to or greater than the coring level value AC, or coring off is set. In this case, for example, if the gain level setting signal GL is “1111”, the gain level adjustment signal GCT becomes “1111”.
The contour compensation component F is 0.9375A.

Also, the contour compensation component F is 0.9375A, 0.875A,
0.8125A, 0.75A, 0.6875A, 0.6
25A, 0.5625A, 0.5A, 0.4375A,
0.375A, 0.3125A, 0.25A, 0.18
75A, 0.0125A, 0.0625A, 0.

(Superimposition of contour compensation component: FIG. 7) In the contour compensation component superimposition circuit 70, the contour compensation component F obtained from the contour compensation component generation selection circuit 60 is converted into a primary difference according to the polarity of the primary difference. Is positive to the input luminance data Yin, and if the primary difference is negative, it is subtracted from the input luminance data Yin.

Specifically, as shown in FIG. 7, the contour compensating component F from the contour compensating component generation selecting circuit 60 and the data obtained by inverting each bit of the contour compensating component F by the inverting circuit 71 are sent to the selector (switch) 72. The selector 72 is switched by the primary difference polarity detection signal DA from the primary difference detection circuit 10 and when the primary difference is positive and the signal DA becomes high level, the selector 72 outputs the contour compensation component F When the primary difference is negative and the signal DA is low, inverted data is extracted from the selector 72.

Further, input luminance data Yi as an original signal
n and the data from the selector 72 are input to the addition circuit 73, and the primary difference polarity detection signal DA is input to the addition circuit 73 as a carry input.

Therefore, when the primary difference is positive, the contour compensating component F is added to the input luminance data Yin, and when the primary difference is negative, the contour compensating component F is subtracted from the input luminance data Yin. From 73, that is, from the contour compensation component superimposing circuit 70, the luminance data Yout after contour compensation is obtained.

(Standardization of Luminance Data--FIG. 7) Limiter 8
At 0, the value of the luminance data from the contour compensation component superimposing circuit 70, which can be smaller than 16 defined as the black level as a result of contour compensation, is limited. That is, assuming that the input data of the limiter 80 is X and the output data is Y, when X <16, Y = 16.

As described above, the sampling frequency fs after contour compensation is set to 13.5 MHz from the limiter 80.
To obtain output luminance data Yout composed of 8-bit data.

(Effects of Embodiment: FIGS. 11 and 1)
2) FIG. 11 shows that the primary difference is positive and that FIG.
This is a case where the absolute value A of the primary difference is equal to or greater than the coring level value AC as shown in FIG.

As shown in FIG. 11, each pixel P1, P2,
.., P3, P4, P5, P6,.
When the absolute value A of the primary difference is obtained, | P2−P1 | = Δa
1, | P3−P2 | = Δa2, and | P
3-P2 | = Δa3. In this case, each difference is Δa
1 is small (small amplitude), Δa2 is medium (medium amplitude), and Δa3 is large (large amplitude).

Then, the absolute value A of the primary difference is converted into a 4-bit primary difference encoded signal ED in the primary difference encoding circuit 20. This primary difference encoded signal ED
In the gain level adjustment circuit 50
The contour compensation component F is formed by subtracting from the bit gain level setting signal GL and also taking into account the contour compensation component superimposition limiting signal FCT. Yin
Is performed.

In this case, as the absolute value A of the primary difference becomes smaller (the amplitude becomes smaller), the contour compensation component F of a higher level is formed and supplied to the contour compensation component superimposing circuit 70. The larger the absolute value A of the difference (the larger the amplitude is), the smaller the level of the contour compensation component F is formed.
It is supplied to the contour compensation component superimposing circuit 70.

In other words, the smaller the absolute value A of the primary difference (the smaller the amplitude is, the greater the amplitude), the greater the amount of compensation of the luminance signal, and the greater the rise of the luminance signal. Is larger (as the amplitude is at a higher level), the amount of compensation of the luminance signal is reduced so that the luminance signal does not rise.

By doing so, the luminance signal Y is greatly reduced without necessitating the contour compensation more than necessary for the sharp contour part where the luminance difference between adjacent pixels is large.
An appropriate contour compensation is performed only on the pixel part that requires in, and the contour part of the image is emphasized.

FIG. 12 shows the magnitude of the absolute value of the primary difference,
FIG. 9 is a diagram for explaining a relationship with a compensation gain. FIG.
As shown in the figure, the area a1 where the magnitude of the absolute value A of the primary difference is small, the area a2 where the magnitude of the absolute value A of the primary difference is medium, and the magnitude of the absolute value of the primary difference are large An area a3 is provided.

The absolute value A of the primary difference is calculated in the area a1
If the signal has a very small amplitude belonging to
1, and when the absolute value A of the first-order difference is a signal having a medium amplitude belonging to the area a2, a medium gain k2
When the absolute value A of the first-order difference is a large-amplitude signal belonging to the area a3, a low gain k3 is used.

Therefore, as shown in FIG. 11, the pixel P2 having a small absolute value A of the difference from the adjacent pixel uses the high gain k1 and sets P2 ′ = k1 × Δa1 to greatly increase the input luminance data Yin. Compensate to raise. Also, the pixel P3 whose absolute value A of the difference from the adjacent pixel is medium
Is P3 ′ = k2 × Δa using a medium gain k2.
As 2, the input luminance data Yin is compensated so as to rise to a medium level. A pixel P4 having a large absolute value A of a difference from an adjacent pixel uses a low gain k3 to obtain P4 ′ =
As k3 × Δa3, compensation is made so that the input luminance data Yin does not rise too much.

In this embodiment, as described above, the absolute value A of the first-order difference is coded into a 4-bit signal so that the absolute value A belongs to one of 16 levels. Depending on the level to which the signal belongs
The contour compensation is performed on the luminance signal Yin.

That is, as described above, the degree to which the luminance signal is compensated is quickly and easily determined by the contour compensation component F selected by the gain level adjustment signal GCT determined according to the absolute value A of the primary difference. In addition, it is possible to more appropriately determine the input luminance data Yin.

Also, the primary difference becomes negative, and
When the absolute value A of the primary difference is equal to or greater than the coring level value AC as shown in (B), the primary difference described above with reference to FIG. 11 is positive, and FIG. As shown, the case where the absolute value A of the primary difference is equal to or larger than the coring level value AC means that the direction of compensation of the luminance signal is opposite (dark direction (minus direction)), but the absolute value of the primary difference is In accordance with only the value A, the amount of compensation can be adjusted to perform contour compensation.

As described above, the absolute value A of the primary difference is encoded and encoded into a signal of a predetermined stage (a predetermined number of bits). It is possible to quickly and appropriately judge how much (level) the contour compensation is to be performed based only on the size of the image signal, and to appropriately perform the contour compensation on the luminance signal.

[Embodiment of System ... FIGS. 13 to 19]
The contour compensation method described above can be applied to digital video playback devices such as DVD players and digital video devices such as digital TV receivers.

(Overview of System: FIG. 13) FIG.
When applied to a VD player, the disc 91 contains
The video signal and the audio signal are, for example, MPEG (Movi)
ng Picture Experts Group)
The data is compression-encoded according to the two standards, multiplexed and recorded, and a disc ID (identification information) for identifying the disc is recorded.

The disk 91 is driven to rotate by a drive mechanism 101 including a disk motor and its drive circuit. The optical head 92 includes a driving mechanism 1 including a feed motor and an actuator for tracking and focusing.
02. Drive mechanisms 101 and 102
Is controlled by a servo controller 103, and the servo controller 103 is controlled by a system controller 104 that controls the entire player system.

For the system controller 104,
An operation unit 105 such as a remote controller is provided,
The operation unit 105 allows the user to perform the above-described coring on / off setting, coring level setting, and gain level setting for contour compensation, and also performs contrast adjustment, color gain adjustment, and hue adjustment of a reproduced image described later. Configure to be able to do it. A display unit 106 including a display element such as a liquid crystal display element is provided to the system controller 104.
Is provided.

Further, an EAROM (Electrica)
lly Alterable Read Only M
memory) or a non-volatile memory 107 such as a flash memory, so that the parameter data for the above adjustment can be written to and read from the memory. However, the non-volatile memory 107 includes a memory that can hold the stored content with a backup power supply, in addition to a memory that can hold the stored content with no power supply.

The information read from the disk 91 and output from the optical head 92 is supplied to the RF processor 93, and the tracking error signal, the focus error signal, the disk ID, and the M
A video and audio data stream of the PEG2 standard is obtained.

The tracking error signal and the focus error signal are supplied to the servo controller 103 and used for tracking servo control and focusing servo control of the optical head 92.

The disk ID is stored in the system controller 1
04 and used for the above adjustments as described below.

The video / audio data stream from the RF processor 93 is separated into a video data stream and an audio data stream by the MPEG decoder 94, and is decompressed and decoded.

The video data output from the MPEG decoder 94 is separated into luminance data and chrominance data in a video reproduction processing unit 95 as described later, and the luminance data undergoes contour compensation and contrast adjustment processing. After performing the processes of color gain adjustment and hue adjustment, the luminance data and the color difference data are combined to obtain video data in the same format as the video data input to the video reproduction processing unit 95.

On the other hand, the video data output from the video reproduction processing unit 95
NTSC system, PAL system, or progressive (P
image display device, such as a CRT display device, a liquid crystal display device, or a video projector, or an analog TV signal.
Output to analog video / audio equipment such as a receiver or other analog video equipment.

On the other hand, the video data output from the video reproduction processing unit 95 is converted into video data of another format by the digital output encoder 97 or is not converted, and is converted to an IEEE (Institute of Select).
Rical and Electronics Eng
The output is to a digital video / audio device such as a digital TV receiver or other digital video devices via a digital interface 98 such as a 1394 standard interface.

The audio data output from the MPEG decoder 94 is subjected to audio reproduction processing in an audio reproduction processing unit 99. Although not shown in the figure, the audio data is output in accordance with the video data output from the video reproduction processing unit 95. It converts it to an analog audio signal and outputs it to an audio output device such as a speaker device or a headphone device, an analog video / audio device such as an analog TV receiver, or other analog audio devices. On the other hand, other types of audio data Multiplexed with or without conversion to video data, via a digital interface 98 or through another digital interface without multiplexing with video data, such as a digital TV receiver. Output to video / audio equipment or other digital audio equipment.

(Example of Video Reproduction Processing Unit: FIGS. 14 to 19)
FIG. 14 shows an example of the video reproduction processing unit 95, and FIG.
FIGS. 16, 17 and 18 show a picture correction circuit 114, a color gain adjustment circuit 115,
Cb hue adjustment circuit 116b, Cr hue adjustment circuit 11
6r shows an example.

As shown in FIG. 19A, the video data Vin input from the MPEG decoder 94 to the video reproduction processing unit 95 is of 4: 2: 2 format (the sampling frequency of the luminance data Y is 13.5 MHz, The sampling frequency of the data Cb and Cr is 6.75 MHz, respectively.
The luminance data Y (Y0, Y1, Y2, Y3...), The color difference data Cb (Cb0, Cb2.
..) Are multiplexed 8-bit data.

Further, according to ITU recommendation ITU-R BT. 60
1, the relationship between the video signal level and the quantization level is such that the quantization signal level is 1 to 254.
The luminance data Y is 22 of “16: black, 235: white peak”.
The color difference data Cb and Cr are set to the 225 level of "128: achromatic color".

<YCbCr Separation> In the video reproduction processing unit 95, the YCbCr separation circuit 111 converts the input video data Vin into luminance data Y, color difference data Cb, and Cr.
Is separated.

In this case, the positions of the data Y, Cb, and Cr in the video data Vin are determined by the phase of the horizontal synchronization signal HSYNC based on the 27 MHz clock CLK1, which is input to the video reproduction processing unit 95 together with the video data Vin. It is determined.

Therefore, in the YCbCr separation circuit 111,
The falling edge of the horizontal synchronizing signal HSYNC is detected, the 2-bit counter is turned using the point latched by the clock CLK1 as a "0" start point, and the value of the counter when the video data Vin is latched by the clock CLK1. , The positions of the data Y, Cb, and Cr are determined, and the data Y, Cb, and Cr are separated.

Further, as shown in FIG. 19A, in the video data Vin, the data Y0
Is delayed by one clock and the data Cr0 is delayed by two clocks, so that the separated data Cb is delayed by two clocks and the separated data Y is delayed by one clock so as to match the phase with the data Cr.

On the other hand, the clock CLK1 of 27 MHz is supplied to the frequency dividing circuit 112, and the clock C1 of 13.5 MHz is supplied.
Generate LK2. In this case, if the frequency of the clock CLK1 is simply divided, the phase of the clock CLK2 becomes unstable. Therefore, like the YCbCr separation circuit 111, the frequency dividing circuit 112 generates the horizontal synchronizing signal HSYNC.
The 1-bit counter is turned with the point at which the falling edge of is latched by the clock CLK1 as the "0" start point,
The phase of the clock CLK2 is controlled and determined by the value of the counter when the clock CLK2 is latched by the clock CLK1.

The 13.5 MHz clock CLK2 having the phase determined as described above is supplied to the YCbCr separation circuit 111, and the YCbCr separation circuit 111 outputs the clock having the phase matched as shown in FIG. 13.5M
Hz data Y, Cb, and Cr are obtained.

<Contour Compensation> For the luminance data Y separated by the YCbCr separation circuit 111, the contour compensation circuit 11
In step 3, a contour compensation process is performed. That is, the contour compensating circuit 113 is a contour compensating apparatus whose example is shown in FIGS. 1 and 2 to 7, and performs contour compensation as described above.

In this case, the luminance data Y output from the contour compensating circuit 113 is 16 (1) by the limiter 80 as described above.
0h) to 235 (EBh).

<Contrast Adjustment> Further, the picture data correction circuit 114 performs contrast adjustment processing on the luminance data Y output from the contour compensation circuit 113.

The contrast adjustment is to change the inclination of the luminance data Y around the value of 16 (10h) of the pedestal level in the direction of increasing or decreasing the contrast. Assuming that the luminance data Y after the adjustment is Yout, Yout = (1 + α) Yin (−1 ≦ α ≦ 1).

In the picture correction circuit 114 shown in FIG. 15, the arithmetic circuit 121 outputs 8-bit input luminance data Yi.
Subtract 16 (10h) from n. Thereby, the value of 16 (10h) of the pedestal level of the input luminance data Yin can be set to a value of 0 in the data Yc output from the arithmetic circuit 121, and can be the center of changing the slope.

The data Yc output from the arithmetic circuit 121
Bit shifters 122, 123, 124 and 125 sequentially shift the bits one bit at a time to the lower side to generate 1/2, 1/4, 1/8 and 1/16 of the data Yc, respectively.

1/2, 1/4, 1 /
The data of 8, 1/16 is supplied to the selector 126 as a component for changing the slope, and according to the value of the 2-bit adjustment signal Scont sent to the selector 126 as described later,
One of the data is selected as a component for determining the magnitude of the inclination.

Then, in the arithmetic circuit 127, according to the value of the one-bit adjustment signal Shl sent to it, S
When hl = 0, the data Y of the output of the arithmetic circuit 121
The data Ysum of the output of the selector 126 is added to c,
When Shl = 1, the data Yc to the data Ysum
Is subtracted, and 16 of the amount reduced by the arithmetic circuit 121 is obtained.
(10h) is added.

The 8-bit data output from the arithmetic circuit 127 is converted by the limiter 128 from 16 (10h) to 235
It is limited to the value of (EBh), and is output from the picture correction circuit 114 as luminance data Yout after contrast adjustment.

However, in the United States, there is a case where the luminance data of less than 16 (10 h) is written in the disk with the setup of 7.5 IRE. Therefore, the video data Vin input to the video reproduction processing unit 95 has 16
When luminance data less than (10h) is included,
The data is output from the contour compensation circuit 113 and the picture correction circuit 114 while retaining the value.

<Color Gain Adjustment> For the color difference data Cb and Cr separated by the YCbCr separation circuit 111,
The color gain adjustment circuit 115 performs color gain adjustment processing.

The color gain adjustment is performed for achromatic 128 (8
The inclination of the color difference data Cb, Cr is changed in the direction of increasing or decreasing the color density around the value of 0h). The color difference data Cb, Cr before adjustment is Cin, and the color difference data Cb, Cr after adjustment is adjusted. When Cr is Cout, Cout = (1 + β) Cin (−1 ≦ β ≦ 1).

Regarding the color gain adjustment, the processing of the color difference data Cb and Cr is exactly the same, but since the hue adjustment circuit 116 at the subsequent stage needs to process the color difference data Cb and Cr separately, the color gain adjustment is also performed. , Color difference data Cb and Cr are processed separately. That is, FIG.
The color gain adjustment circuit 115 of FIG.
r is provided for both.

In the color gain adjustment circuit 115 of FIG. 16, the MSB inversion circuit 131 inverts the MSB of the 8-bit input color difference data Cin. By this, MSB
Is a sign bit, and input color difference data Cin of 0 to 255 (FFh) is -127 (-7Fh) to +127 (+
7Fh), the achromatic 128 (80h) value of the input color difference data Cin can be set to a value of 0 in the converted data Cinv, and can be the center for changing the slope. .

The converted data Cinv is sequentially bit-shifted to the lower side by one bit by bit shifters 132, 133, 134 and 135, and the data Cinv is
Data of 1/2, 1/4, 1/8, and 1/16 of inv are generated. However, the MSB is a sign bit, and when each data is bit-shifted, a copy of the sign bit is shifted in.

1/2, 1/4, of these data Cinv
The data of 1/8 and 1/16 are supplied to the selector 136 as a component for changing the inclination, and the data of the selector 136 is described later.
, One of the data is selected as a component for determining the magnitude of the gradient in accordance with the value of the 2-bit adjustment signal Sgain sent to.

In the arithmetic circuit 137, when Sdplt = 0 according to the value of the 1-bit adjustment signal Sdplt sent thereto, the MSB inverting circuit 131
, The data SUM output from the selector 136 is added to the output data Cinv, and when Sdplt = 1, the data SUM is subtracted from the data Cinv.

In this case, the number of bits of the data Cinv and SUM is expanded to 9 bits by copying each MSB of the data Cinv and SUM to the ninth bit.

The value of the 9-bit data Cnt output from the arithmetic circuit 137 is limited by a limiter 138. "2
According to the definition of "25 levels, 128: achromatic color", the dynamic range of the color difference data Cb, Cr is 16 (1
0h) to 240 (F0h).

Therefore, in limiting the value of the 9-bit data Cnt, 113 (71h) ≦ Cnt ≦ 255 in consideration of inverting the eighth bit later.
In the case of (FFh), Cnt = 112 (70h), and 256 (100h) ≦ Cnt ≦ 399 (18Fh)
, Cnt = 400 (190h).

The 9-bit data Cnt whose value has been limited by the limiter 138 as described above is supplied to the MSB inverting circuit 139.
, The ninth bit is rounded down to 8-bit data, and the 8th bit is inverted and output from the color gain adjustment circuit 115 as color difference data Cout after color gain adjustment.

<Hue Adjustment> As described above, the hue adjustment circuit 116 performs a hue adjustment process on the color difference data Cb and Cr after the color gain adjustment output from the color gain adjustment circuit 115 of FIG.

The hue adjustment is performed for achromatic 128 (80h)
The inclinations of the color difference data Cb and Cr are changed in opposite directions around the value of the color difference data. In this example, the color difference data Cb and Cr before the adjustment are Cbin and Crin, and the color difference data Cb and Cr after the adjustment are the Cbout. , Cout, Cbout = Cbin + γCrin Cout = Crin−γCbin (−1 ≦ γ ≦ 1).

The Cb hue adjustment circuit 116b in FIG. 17 and the Cr hue adjustment circuit 116r in FIG.
The MSBs of the 8-bit input color difference data Cbin and Crin are inverted by the MSB inversion circuits 141 and 151, and the achromatic 128 (80h) value of the input color difference data Cbin and Crin is converted to the data Cbinv and Crinv after the MSB inversion. In this case, the value is set to 0, the center for changing the inclination is set, and the bit shifters 142 to 14 are set.
5 and 152 to 155 are the same as the color gain adjustment circuit 115 of FIG.

In the Cb hue adjustment circuit 116b, the data of the component for changing the inclination is supplied to the selector 146, and any one of the two bits of the adjustment signal Shue sent to the selector 146 will be described later. The data is selected as a component for determining the magnitude of the gradient, and the Cr hue adjustment circuit 116r supplies the data of the component for changing the gradient to the selector 156, and in accordance with the value of the 2-bit adjustment signal Shue, One of the data is selected as a component for determining the magnitude of the inclination.

Further, in the arithmetic circuit 147 of the Cb hue adjusting circuit 116b, according to the value of the 1-bit adjusting signal Sbr sent thereto, when Sbr = 0, the MSB
The data Cbinv output from the inversion circuit 141 is added to the data C output from the selector 156 of the Cr hue adjustment circuit 116r.
rSUM is added, and when Sbr = 1, the data Cb
The data CrSUM is subtracted from inv.

Conversely, the arithmetic circuit 157 of the Cr hue adjusting circuit 116r, when Sbr = 0, sets the MSB inverting circuit 15 according to the value of the 1-bit adjustment signal Sbr.
The data CbSUM output from the selector 146 of the Cb hue adjustment circuit 116b is subtracted from the data Crinv output 1 and, when Sbr = 1, the data CbSUM is added to the data Crinv.

Also in this case, the data Cbinv, CrSU
The number of bits of the data Cbinv, CrSUM, Crinv, and CbSUM is expanded to 9 bits by copying each MSB of M, Clinv, and CbSUM to the ninth bit.

Then, the 9-bit data Cbh and Cr of the output of the arithmetic circuit 147 of the Cb hue adjusting circuit 116b and the arithmetic circuit 157 of the Cr hue adjusting circuit 116r are output.
h limits its value at limiters 148 and 158, respectively. As described above, “225 levels, 12
8: achromatic color ”, the color difference data Cb, C
The dynamic range of r is 16 (10 h) to 240
(F0h).

Therefore, in limiting the values of 9-bit data Cbh and Crh, 113 (71h) ≦ Cb in consideration of inverting the eighth bit later.
When h, Chr ≦ 255 (FFh), Cbh, C
rh = 112 (70h), 256 (100h) ≦ C
When bh, Crh ≦ 399 (18Fh), Cb
h, Crh = 400 (190h).

Thus, 9-bit data Cbh and Crh after the values are limited by limiters 148 and 158.
In the MSB inverting circuits 149 and 159, respectively, the ninth bit is rounded down to 8-bit data, and the 8th bit is inverted so that the hue-adjusted color difference data Cbout and Cout are converted into C data.
b hue adjustment circuit 116b and Cr hue adjustment circuit 1
16r, that is, from the hue adjustment circuit 116 in FIG.

<YCbCr Synthesis> In the video reproduction processing unit 95 of FIG. 14, the luminance data Y and the color difference data Cb, Cr output from the YCbCr separation circuit 111 are in phase as shown in FIG. 19B. . However, the luminance data Y in the contour compensation circuit 113 and the picture correction circuit 114
Is different from the number of latches of the color difference data Cb and Cr in the color gain adjustment circuit 115 and the hue adjustment circuit 116. More specifically, the former is larger. Hugh adjustment circuit 116
Color difference data Cb and Cr output from the
14 so as to be in phase with the luminance data Y of the output,
A predetermined clock of 13.5 MHz clock CLK2,
Latch.

Then, in the YCbCr synthesis circuit 118,
The luminance data Y output from the picture correction circuit 114 and the delay adjustment circuit 117 that are in phase as shown in FIG.
Are combined and multiplexed.

In this case, in the synthesized video data Vout, the phase relationship between the data Y, Cb, and Cr is as shown in FIG.
As shown in (C), the data Cr is converted to a 27 MHz clock CLK so as to be the same as that of the video data Vin input to the video reproduction processing unit 95 shown in FIG.
1 and the data Y is delayed by the clock CLK1.
1 clock.

Further, similarly to the YCbCr separation circuit 111, a falling edge of the horizontal synchronizing signal HSYNC is detected, and a 2-bit counter is turned using the point latched by the 27 MHz clock CLK1 as a "0" start point. , The data Y and C according to the value of the counter when the video data Vout is latched by the clock CLK1.
After determining the positions of b and Cr, the video data Vout is changed to Y
Output from the CbCr synthesis circuit 118, that is, from the video reproduction processing unit 95.

(Adjustment in System: FIG. 20) In the player system shown in FIG. 13 configured as described above, for example, the user operates the operating unit while a reproduced image is displayed on an image display device connected to the player system. By operating 105, for contour compensation, coring on / off setting, setting of the coring level value AC shown in FIGS. 4 and 10, and setting of the gain level by the gain level setting signal GL shown in FIG. 5 are performed. Configure the system to be able to.

By operating the operation unit 105 in the same manner, the contrast can be adjusted in four steps in the direction of increasing the contrast or in the direction of decreasing the contrast, and in the color gain adjustment, the color density can be increased. The system is configured such that the adjustment can be made in four steps, respectively, in the direction of increasing or decreasing, and the hue adjustment can be adjusted in four steps, in the direction of increasing blue or in the direction of increasing red, respectively.

The system controller 104 detects the adjustment operation on the operation unit 105, sends an adjustment signal corresponding to the adjustment operation to each circuit of the video reproduction processing unit 95, and makes each circuit adjust the adjustment operation according to the adjustment operation. Is performed.

That is, when coring on is set for contour compensation, the coring on / off signal sent from the contour compensation circuit 113 to the contour compensation control circuit 40 shown in FIG. Is set, the coring on / off signal is set to a high level, and the coring level value AC and the gain level setting signal GL are determined according to the degree of adjustment.

When the contrast is adjusted in the direction of increasing the contrast, Shl is set to 0, and when the contrast is adjusted in the direction of decreasing the contrast, Shl is set to 1 and the adjustment signal Shl is set as shown in FIG. The arithmetic circuit 127 shown in FIG. 15 of the fourteen picture correction circuits 114
, And the 2-bit adjustment signal Scont is set to a value of 0, 1, 2, or 3 according to the degree of adjustment, and is sent to the selector 126 shown in FIG.

As a result, in the picture correction circuit 114, the contrast adjustment process is performed on the luminance data Y as described above.

When the color gain is adjusted in the direction of increasing the color density, Sdplt = 0, and when the color gain is adjusted in the direction of decreasing the color density, Sdlt is set to Sdplt = 0.
plt = 1, and the adjustment signal Sdplt is applied to the arithmetic circuit 1 shown in FIG. 16 of the color gain adjustment circuit 115 in FIG.
At the same time, the 2-bit adjustment signal Sgain is set to a value of 0, 1, 2, or 3 according to the degree of adjustment, and is sent to the selector 136 shown in FIG.

Thus, the color gain adjustment circuit 11
At 5, the color gain adjustment process is performed on the color difference data Cb and Cr as described above.

Further, when the hue adjustment is performed in the direction of increasing blue, Sbr = 0 is set, and when the hue adjustment is performed in the direction of increasing red, Sbr = 1 is set, and the adjustment signal Sb is set.
is sent to the arithmetic circuit 147 shown in FIG. 17 and the arithmetic circuit 157 shown in FIG. 18 of the hue adjustment circuit 116 in FIG. 14, and the 2-bit adjustment signal Shue is set to 0, The values are sent to the selector 146 shown in FIG. 17 and the selector 156 shown in FIG.

Thus, the hue adjustment circuit 116 executes the hue adjustment process on the color difference data Cb and Cr as described above.

Further, in the player system shown in FIG. 13, when an adjustment is made in response to a user's adjustment operation as described above while a certain disc is being played, the system controller 104 transmits the adjustment signal at that time. The state is used as an adjustment parameter for the disk I of the disk.
D is written to the nonvolatile memory 107 in association with D, and when the same disc is reproduced next, the nonvolatile memory 10
7, the system is configured to read the adjustment parameter corresponding to the disc, set the adjustment signal to the same state as previously set according to the user's adjustment operation, and perform the adjustment.

As a result, the user can always obtain an optimum reproduced image for the same disk without performing an adjustment operation each time the disk is reproduced.

FIG. 20 shows an example of the above-described adjustment processing routine performed by the system controller 104.

In this adjustment processing routine, after the reproduction of a certain disk is started, first, in step 161, the disk ID of the disk is fetched. Then, in step 162, it is determined whether or not the disk ID is stored in the nonvolatile memory 107. Judge.

When the disk ID is the non-volatile memory 107
If it is not stored, the process proceeds to step 163, where the contour compensation, the contrast adjustment, the color gain adjustment, and the hue adjustment are set in a predetermined state.
For example, for the contour compensation, coring on is set, the coring level value AC is set to a predetermined value, and the gain level setting signal GL is set to “111” at which the gain level is maximized.

Next, proceeding to step 164, it is determined whether or not the user has performed an adjustment operation. Then, the process proceeds to step 166 to display on the display unit 106 a message asking the user whether or not to store the adjustment state at that time as the adjustment state of the disc.

When the user wants to store the adjustment state at that time as the adjustment state of the disk, he or she performs an operation to that effect, and stores the adjustment state at that time as the adjustment state of the disk. If the user does not wish to do so, the user performs an operation to that effect.

Then, the system controller 104
Proceeding from step 166 to step 167, it is determined whether or not the user's response is desired to be stored. If the response is desired to be stored, the process proceeds from step 167 to step 168, where the adjustment signal at that time is output. The state,
The adjustment parameter is written in the non-volatile memory 107 in association with the disk ID of the disk, and if the user's response is not desired to be stored, the adjustment process is terminated.

On the other hand, in step 162, the disk I
If it is determined that D is stored in the non-volatile memory 107, the process proceeds to step 169, where the non-volatile memory 1
From 07, the adjustment parameter corresponding to the disk ID is read out, and the process proceeds to step 171. After the adjustment is performed using the adjustment parameter, the process proceeds to step 164.

The user can change the adjustment even with the adjustment parameter stored in the nonvolatile memory 107 and corresponding to the disk. When the user performs an operation to change the adjustment, the system controller 104 performs the same processing as that of the first adjustment for the disc in step 165 and subsequent steps.
In step 168, the adjustment parameters are rewritten.

When recording video data on a disc, a scene ID (identification information) for specifying a video scene can be multiplexed with video data and recorded.

When playing back a disk on which a scene ID is recorded in this way, when the adjustment is performed as described above, the system controller 104
In addition to associating with the scene ID at that time, the adjustment parameter is written into the non-volatile memory 107, and when the same disc is reproduced next time, the non-volatile memory 107 It is also possible to read the adjustment parameters corresponding to the video scene and set the adjustment state.

As a result, the user can always obtain an optimum reproduced image for each video scene for the same disc without performing an adjustment operation each time the reproduction is performed and for each video scene.

In addition, not only video identification information, which is information for specifying video, such as a disk ID and a scene ID, but also characteristic description information, which is information describing image characteristics such as the entire disk and scenes, is recorded on the disk. In this case, the adjustment parameter is written in the nonvolatile memory 107 in association with the characteristic description information, and when the next disk or scene in which the same characteristic description information is recorded is reproduced, the adjustment parameter is written. It is also possible to read the adjustment parameter corresponding to the characteristic description information from the characteristic memory 107 and set the adjustment state.

Further, the above adjustment method is not limited to a digital video reproducing apparatus such as a DVD player,
It can also be applied to digital video equipment such as a V receiver.

In digital TV broadcasting, video identification information such as a program (program) ID and a genre (category) ID is transmitted, and characteristic description information describing image characteristics of a program or scene is inserted into the program or scene. Can be sent.

Therefore, in the digital TV receiver, a memory corresponding to the non-volatile memory 107 described above is provided, and the system controller stores the adjustment parameters at that time in the memory based on the user's instruction. Write in association with video identification information or characteristic description information,
Next, when a program or scene in which the same video identification information or characteristic description information is inserted is received, an adjustment parameter corresponding to the video identification information or characteristic description information is read out from the memory, and an adjustment state is set. The configuration is as follows.

[0144]

As described above, according to the present invention, overshoot can be suppressed by a simple circuit configuration with a small number of gates, and desired contour compensation characteristics can be obtained without causing ringing or waveform distortion. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a contour compensation device of the present invention.

FIG. 2 is a diagram illustrating an example of a primary difference detection circuit of FIG. 1;

FIG. 3 is a diagram illustrating an example of a primary differential encoding circuit in FIG. 1;

FIG. 4 is a diagram illustrating an example of the contour compensation control circuit of FIG. 1;

FIG. 5 is a diagram illustrating an example of a gain level adjustment circuit in FIG. 1;

FIG. 6 is a diagram illustrating an example of a contour compensation component generation selection circuit in FIG. 1;

FIG. 7 is a diagram illustrating an example of a contour compensation component superimposing circuit and a limiter of FIG. 1;

FIG. 8 is a diagram provided for describing an absolute value and a polarity of a primary difference.

FIG. 9 is a diagram for explaining an output signal ED from the primary differential encoding circuit of FIG. 1;

FIG. 10 is a diagram illustrating a relationship between an absolute value of a primary difference and a coring level value.

FIG. 11 is a diagram for describing an outline compensation component when a first-order difference is positive;

FIG. 12 is a diagram for describing an outline compensation component when a first-order difference is positive;

FIG. 13 is a diagram showing an embodiment when applied to a DVD player.

FIG. 14 is a diagram illustrating an example of a video reproduction processing unit.

FIG. 15 is a diagram illustrating an example of a picture correction circuit.

FIG. 16 is a diagram illustrating an example of a color gain adjustment circuit.

FIG. 17 is a diagram illustrating a part of an example of a hue adjustment circuit.

FIG. 18 is a diagram illustrating a part of an example of a hue adjustment circuit.

FIG. 19 is a diagram provided for description of data processing in a video reproduction processing unit.

FIG. 20 is a diagram illustrating an example of an adjustment processing routine performed by a system controller.

[Explanation of symbols]

Since the main parts are all described in the figure, they are omitted here.

Continued on the front page F term (reference) 5C021 PA17 PA53 PA66 PA71 RA11 RB03 SA25 XB03 YC08 ZA02 5C066 AA07 CA06 EA03 EC02 EF12 GA05 GA31 HA02 JA01 KA12 KD02 KD06 KE02 KE07 KE11 KM11 KP02

Claims (10)

[Claims] 1. A method according to claim 1, wherein a certain pixel and one pixel
While detecting the absolute value and the polarity of the primary difference, which is the difference of the data value between the pixel before the clock and the polarity, encodes the absolute value of the primary difference into an encoded signal of a predetermined bit. The larger the coded signal is, the smaller the gain is, and as a contour compensation component, according to the polarity of the primary difference, the primary difference is added to the original luminance data if the primary difference is positive, and the original luminance data is added if the primary difference is negative. Video processing method to subtract from the luminance data of 2. The image processing method according to claim 1, wherein when the absolute value of the primary difference is smaller than a set coring level, the contour compensation component is limited to a predetermined value. 3. A method according to claim 1, wherein luminance data and color difference data are separated from digital video data in which luminance data and color difference data are multiplexed, and the separated luminance data is contour-compensated by the method according to claim 1. And a gain adjustment or hue adjustment process for the separated color difference data. 4. A method according to claim 1, wherein a certain pixel and one
A primary difference detection unit that detects the absolute value and polarity of a primary difference that is a difference between the data value before the clock and the pixel value, and an absolute value of the primary difference obtained by the primary difference detection unit, A primary difference encoding unit that encodes the encoded signal of a predetermined bit; and the encoded signal obtained by the primary difference encoding unit, with a smaller gain as the encoded signal is larger, as a contour compensation component. A contour compensation component generating and superimposing unit that adds to the original luminance data when the primary difference is positive and subtracts from the original luminance data when the primary difference is negative according to the polarity of the primary difference. Video processing device. 5. The video processing device according to claim 4, wherein the contour compensation component generation and superimposition unit is configured to determine whether the absolute value of the primary difference obtained by the primary difference detection unit is smaller than a set coring level. A video processing device for limiting the contour compensation component to a predetermined value. 6. A data separation circuit for separating luminance data and chrominance data from digital video data in which luminance data and chrominance data are multiplexed, and contour compensation for the luminance data separated by the data separation circuit. A contour compensating circuit for performing a process, wherein the contour compensating circuit is configured to calculate, for the luminance data separated by the data separating circuit, a primary difference of a data value between a pixel and a pixel one clock before. A primary difference detector for detecting an absolute value and a polarity, a primary difference encoder for encoding the absolute value of the primary difference obtained by the primary difference detector into an encoded signal of a predetermined bit, When the primary difference is positive according to the polarity of the primary difference, the encoded signal obtained by the primary difference encoding unit has a smaller gain as the encoded signal is larger, and as a contour compensation component, Former Was added to the luminance data, the image processing apparatus and a contour compensation component generating superimposing unit for subtracting from the original luminance data when the primary difference is negative. 7. The video processing apparatus according to claim 6, further comprising: an adjustment processing circuit that performs gain adjustment or hue adjustment processing on the color difference data separated by the data separation circuit. 8. An image processing apparatus according to claim 6, further comprising a data synthesizing circuit for synthesizing luminance data output from said contour compensation circuit and color difference data output from said data separation circuit or said adjustment processing circuit. Processing equipment. 9. A digital video device comprising the video processing device according to claim 4 as a video processing unit. 10. A digital video device according to claim 9, wherein: a memory capable of holding storage contents by a no power source or a backup power source; an adjustment state for the video data; Or, in association with characteristic description information, which is information describing image characteristics, written in the memory, at the time of video output, video identification information or characteristic description information about video data to be output, and the corresponding adjustment parameter, A digital video device comprising: a control unit that, when stored in a memory, reads the adjustment parameter from the memory, and sets an adjustment state for output video data based on the read adjustment parameter.