JP2002232490A - Clock signal transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock signal transmission system that reduces spurious electromagnetic radiation noise generated attended with a clock signal and is hardly susceptible to the effect of signals existing in the surrounding. SOLUTION: The clock signal led to many points on a printed circuit board is transmitted by the LVDS(low voltage differential signaling) system. Since a common mode noise is eliminated from the output LVDS signal, the effect of noise in the surrounding is hardly susceptible. Since the LVDS signal is a signal with a small amplitude, a cause for unwanted electromagnetic radiation noises can be avoided and the effect on external devices can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal transmission system and, more particularly, to a clock signal transmission system which reduces unnecessary electromagnetic radiation noise generated with the transmission of a clock signal and is less affected by surrounding signals. It relates to a transmission system.

[0002]

2. Description of the Related Art Conventionally, printers, copiers, facsimile machines
The output signals of the clock generator and clock driver used for TTL level (high potential level 2.0-5V, low potential level 0-0.8V) and LVTTL level (high potential level MAX)
1.7 V, low potential level MAX 0.7 V), and in an actual printer or the like, an output signal (clock signal) from a clock oscillator or the like is routed on a printed circuit board and transmitted.

[0003]

However, when a clock signal of a TTL level or the like is routed on a printed circuit board as described above, it causes unnecessary electromagnetic radiation noise due to the clock signal. Further, when the clock signal is affected by the surrounding signals, there is a problem that a malfunction of the image forming apparatus system is easily caused.

An object of the present invention is to provide a clock signal transmission system which reduces unnecessary electromagnetic radiation noise generated with a clock signal and is hardly affected by surrounding signals.

[0005]

According to a first aspect of the present invention, a clock signal routed on a printed circuit board is transmitted by an LVDS signal system. Further, the invention according to claim 2 is characterized in that the clock signal routed on the printed circuit board generates a plurality of clock output signals from one clock input signal.

In this way, the output LVDS signal removes common-mode noise, so that it is less susceptible to noise from the surroundings. Also, since the LVDS signal is a small-amplitude signal, unnecessary sources of electromagnetic radiation noise are generated. And the effect on external devices can be reduced.

According to a third aspect of the present invention, the output of the clock signal routed on the printed circuit board is a single output.
Switching between end signal output and LVDS signal output is possible. In this way, the output of the clock signal routed on the printed circuit board can be single-ended and LV
Since it can be switched to a DS signal, versatility can be provided.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the illustrated embodiment. (1) First Embodiment FIG. 1 is a block diagram of the present embodiment. In FIG. 1, reference numeral 10 denotes a clock oscillator configured on a printed circuit board according to the present embodiment. The clock speed of the clock generator is, for example, about 100 MHz at the maximum. Reference numeral 11 denotes a clock transmission circuit, which is connected to the driver 12 by a single-ended signal such as TTL or LVTTL. The driver 12 has a transmission path on the plus side and the minus side of the LVDS signal. LVDS stands for Low Voltage Differential Signalin
g (low-voltage differential signal). Reference numeral 13 denotes a receiver, and reference numeral 14 denotes a terminating resistor.

Next, the transmission system of the LVDS signal will be described with reference to FIG. 2 which is an explanatory diagram of the LVDS transmission system and its signal level. As shown in FIG. 2, in the LVDS transmission system, a signal of "H" or "L" of the TTL (or LVTTL) driving system is converted into a low-amplitude differential signal, that is, a signal composed of a combination of two signals. And then transmit. One of these two signals is defined as "+ side" and the other "-side",
The "H" or "L" signal of the TTL (or LVTTL) drive method is converted into a voltage level between the "+ side" and the "-side".

The "+" and "-" signal lines are short-circuited by a 100Ω resistor at the input stage on the receiver side. This is because the impedance of the transmission line through which the low-amplitude differential signal (LVDS signal) is transmitted is defined as 100Ω (TIA / EIA-644 standard), and the terminating resistance of each signal line is reduced. It is for securing.

Here, referring to FIG. 3 and FIG.
The difference between the influence of noise (external factors) on the end signal and the influence of noise on the differential signal will be described. single·
In the case of the end signal, if no noise is applied, FIG.
As shown in (A), the same signal as the driver input is output from the receiver. However, when noise is applied, as shown in FIG. 3B, false data is output from the receiver to a location corresponding to the noise.

On the other hand, in the case of the LVDS signal, if no noise is applied, the same signal as the driver input is output from the receiver as shown in FIG. As shown in FIG. 4B, the same signal as the driver input is output from the receiver. That is, the LVDS signal is strong against noise because common-mode noise is removed.
In the case of the LVDS signal, since the transmission method is the current mode, a terminating resistor is required, and the output voltage of the driver is 350 mV when the terminating resistance value is 100Ω. This small amplitude suppresses the occurrence of EMI (Electro Magnetic Interference). That is, generation of unnecessary electromagnetic radiation noise can be suppressed.

In this embodiment, the terminating resistance is set to 10
Although the case of 0Ω has been described, the termination resistance value can be set to another value according to the impedance of the printed circuit board or the input threshold of the receiver.

(2) Second Embodiment FIG. 5 is a block diagram of the present embodiment. In FIG. 5, reference numeral 20 denotes a clock driver circuit formed on a printed circuit board according to the present embodiment.
For example, the output of the crystal oscillator is amplified by the amplifier 22. The output of the amplifier 22 is connected to the buffers 23a to 23n. In this example, the clock output shows an example of N channels. Buffer output is LVDS driver 2 each
4a to 24d, which are connected to the LVDS driver 24n and have a transmission path for N-channel clock output. Symbols 25a to 25n
Is a receiver, and reference numerals 26a to 26n are terminating resistors.

In the present embodiment, the LVDS signal is used for transmission for the same reason as in the first embodiment, so that it is resistant to external noise and generates unnecessary electromagnetic radiation noise. Can be suppressed.

(3) Third Embodiment FIG. 6 is a block diagram of the present embodiment. In FIG. 6, reference numeral 30 denotes a clock transmitter formed on a printed circuit board according to the present embodiment, and a clock transmitter 32
Is connected to the 3-State buffers 34 and 35, and the buffer 3
4 is connected to the LVDS driver 33. The buffer 35 has a single-ended output.

Reference numeral 31 denotes an inverter, which inverts the switching signal D / S and outputs a 3-state buffer 34 and an enable terminal 3
5 When switching signal D / S is "H", 3-S
The tate buffer 34 is enabled, the LVDS output is selected, and when the D / S signal is "L", the 3-State buffer 35 is enabled, and the single-ended output is selected.
Reference numerals 36 and 38 are receivers, and reference numeral 37 is a terminating resistor.

Although the present embodiment has shown the case where there is one clock input signal, as in the second embodiment, one clock input signal is used.
When generating multiple output signals from one input signal,
Needless to say, the present embodiment is applicable. Also in the case of the present embodiment, for the same reason as in the first embodiment, since the LVDS signal is used for transmission, it is resistant to external noise and suppresses generation of unnecessary electromagnetic radiation noise. Can be.

[0019]

As described above, according to the present invention, the following effects can be obtained. According to the first and second aspects of the present invention, since the output is an LVDS signal, the output is less susceptible to noise from the surroundings, and unnecessary sources of electromagnetic radiation noise are eliminated, thereby affecting external devices. Can be reduced. According to the third aspect of the present invention, the output can be switched between single-ended and LVDS signals, so that versatility can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an LVDS transmission system and its signal level.

FIG. 3A is a waveform diagram when noise is not applied to a single-ended signal, and FIG. 3B is a waveform diagram when noise is applied to a single-ended signal.

4A is a waveform diagram when noise is not applied to the LVDS signal, and FIG. 4B is a waveform diagram when noise is applied to the LVDS signal.

FIG. 5 is a block diagram of a second embodiment of the present invention.

FIG. 6 is a block diagram of a third embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 clock transmitter 11 clock transmission circuit 12, 24a to 24n, 33 driver 13, 25a to 25n, 36, 38 receiver 14, 26a to 26n, 37 termination resistor 20 clock driver 21 transmission means 22 Amplifiers 23a to 23n Buffer 30 Clock oscillator 31 Inverter 32 Clock transmission circuit 34, 35 3-state buffer

Claims (3)

[Claims] 1. A clock signal transmission system for transmitting a clock signal routed on a printed circuit board by an LVDS signal system. 2. The clock signal transmission system according to claim 1, wherein the clock signal routed on the printed circuit board generates a plurality of clock output signals from one clock input signal. 3. The clock signal transmission system according to claim 1, wherein the output of the clock signal routed on the printed circuit board is switchable between a single-ended signal output and an LVDS signal output. .