JP2009060489A - Signal transmitter, signal receiver, and multiplex differential transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve differential transmission of 3-bit bit information signals through three signal lines, to transmit the states of all 3 bits, to prevent wrong detections which may arise when the voltage value of a differential driver on the transmitter side is not proper, and to reduce power consumption by the differential driver. <P>SOLUTION: In a multiplex differential transmission system, a signal transmitter 10 has differential drivers 11 to 13 transmitting output signals S11a to S13a and inversion output signals S11b to S13b respectively. In the multiplex differential transmission system, the signal transmitter 10 synthesizes the output signals S11a and S13b, transmits the output signals to the signal conductor 31, synthesizes the output signals S12a and S11b and transmits them to the signal conductor 32, and synthesizes the output signals S13a and S12b and transmits the output signals to the signal conductor 33. In this system, when the detectable minimum voltage values of differential receivers 21 to 23 are X, the signal voltage Vd1 of the output signals S11a and S12a and the signal voltage Vd3 of the output signal S13a are set to satisfy Vd1≥2X and Vd1+2X≤Vd3≤3Vd1-2X. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal transmitter, a signal receiver, and a multiple differential transmission system, and in particular, a multiple differential transmission system that differentially transmits a 3-bit bit information signal via a signal transmission path composed of three signal lines. And a signal transmitter and a signal receiver used in the multiple differential transmission system.

  In recent years, in flat panel displays typified by liquid crystal televisions and plasma televisions, the signal speed for transferring image information has been increased as the image quality has increased from VGA (Video Graphics Array) to XGA (eXtended Graphics Array). Yes. Therefore, a low-amplitude differential transmission method has been used as a high-speed digital data transmission method.

  This transmission method is a transmission method in which signals having opposite phases are transmitted through one balanced cable or two signal line patterns formed on a printed circuit board. Features include low noise, strong resistance to external noise, low voltage amplitude, high-speed data transmission, and the like, and the introduction of the high-speed transmission technique is progressing particularly in the display field.

Japanese Patent No. 3507687. JP-A-4-230147.

  The differential transmission method has many merits in the high-speed transmission as described above compared with the normal single-ended transmission method. However, since two signal lines are required for one data bit transmission, in order to realize multi-bit transmission, there are problems such as an increase in the number of signal lines and an increase in the signal line area on the printed circuit board. Had. For this reason, it has become a big issue in realizing further high-speed transmission in the future.

  With respect to this problem, for example, in the differential data transmission method disclosed in Patent Document 1, two data bit transmissions are performed using three lines (conventional data lines) by using one line as a complementary data line. The differential transmission method requires four wires), and has achieved a reduction in data signal lines, but the signals flowing through the three wires are not balanced and the radiation noise is larger than in normal differential transmission. There were problems such as becoming.

  Further, in Patent Document 2, differential transmission of a 3-bit bit information signal is performed using three signal lines. However, there is a limitation that output signals of all three differential drivers must be different, and 3 Since all three bits cannot transmit the states of 0 and 1, and only 6 states can be transmitted from 3 bits (8 states) except for the states of all 0 and 1 bits, There was a big problem.

  Furthermore, if the value of the signal voltage of the differential driver on the transmitter side is not appropriate, the voltage applied to the differential receiver on the receiver side is less than the threshold voltage that can be detected by the differential receiver, which may cause false detection. There was sex.

  The object of the present invention is to realize the differential transmission of a 3-bit bit information signal with three signal lines in order to solve the above problems, suppress the generation of noise, and further reduce the number of data signal lines. Multiple errors that can be transmitted and all three bits can be transmitted, prevent false detections that can occur when the voltage value of the differential driver on the transmitter side is not appropriate, and reduce power consumption by the differential driver An object of the present invention is to provide a dynamic transmission system and a signal transmitter and a signal receiver used for the multiple differential transmission system.

A signal transmitter according to a first aspect of the present invention is a signal transmitter comprising a signal transmitter, a signal receiver, and first, second, and third signal lines connecting the signal transmitter and the signal receiver. In a signal transmitter for a multiple differential transmission system comprising a path, in response to a first bit information signal, a first output signal and an inverted first output that is a phase inverted signal of the first output signal A first differential driver for transmitting the signal, and a second output signal and an inverted second output signal that is a phase inverted signal of the second output signal in response to the second bit information signal. A second differential driver; a third output signal having a signal voltage different from the first output signal and the second output signal in response to the third bit information signal; and a phase inverted signal of the third output signal. And a third differential driver for transmitting an inverted third output signal that is The first output signal and the inverted third output signal are combined and transmitted to the first signal line, and the second output signal and the inverted first output signal are combined and transmitted to the second signal line. The third output signal and the inverted second output signal are combined and transmitted to a third signal line, and when the minimum detectable voltage value of the differential receiver of the signal receiver is X, the first A signal voltage Vd1 of the first output signal and the second output signal, and a signal voltage Vd3 of the third output signal,
[Equation 1]
Vd1 ≧ 2X
And [Equation 2]
Vd1 + 2X ≦ Vd3 ≦ 3Vd1-2X
It is characterized by setting to satisfy.

  A signal receiver according to a second aspect of the invention is a signal composed of the signal transmitter, the signal receiver, and first, second, and third signal lines that connect the signal transmitter and the signal receiver. In a signal receiver for a multiplex differential transmission system including a transmission line, a termination voltage generated in a first termination resistor connected between the first signal line and the second signal line. A first differential receiver for detecting the polarity and outputting the detection result as a first bit information signal; and a second differential connected between the second signal line and the third signal line A second differential receiver for detecting a polarity of a termination voltage generated in the termination resistor and outputting the detection result as a second bit information signal; and the third signal line and the first signal line. The polarity of the termination voltage generated in the third termination resistor connected between them is detected, and the detection result is A third differential receiver that outputs a third bit information signal, and a determination unit that determines whether or not a voltage across the third termination resistor is greater than or equal to a threshold value. When the voltage is equal to or higher than a threshold value, the first, second, and third bit information are detected by the first, second, and third differential receivers, respectively, and the voltage across the third termination resistor is the threshold value. If it is less than, only the detection result of the third differential receiver determines that all the bit information is 0 or all is 1, and the minimum voltage value that can be detected by the first, second, and third differential receivers Is X.

  A multiple differential transmission system according to a third aspect of the present invention includes the signal transmitter and the signal receiver.

  According to the signal transmitter, the signal receiver, and the multiple differential transmission system according to the present invention, the differential transmission of the 3-bit bit information signal is performed in order to suppress the generation of noise and further reduce the data signal line. Can be realized with three signal lines, and all three bits can be transmitted, and it is possible to prevent erroneous detection that may occur when the voltage value of the differential driver on the transmitter side is not appropriate, and the differential driver The power consumption due to can be reduced.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following embodiments, the same reference numerals are assigned to the same components.

Embodiment.
FIG. 1 is a block diagram showing a configuration of a multiple differential transmission system according to an embodiment of the present invention. In FIG. 1, the multiple differential transmission system according to the present embodiment is configured by connecting a signal transmitter 10 and a signal receiver 20 via a signal transmission path 30.

The signal transmitter 10
(A) a differential driver 11 that outputs a first output signal S11a and an inverted first output signal S11b that is a phase inverted signal in response to a bit information signal B1 having a high level or a low level;
(B) in response to a bit information signal B2 having a high level or a low level, a differential driver 12 that outputs a second output signal S12a and an inverted second output signal S12b that is a phase inverted signal thereof;
(C) A differential driver 13 that outputs a third output signal S13a and an inverted third output signal S13b that is a phase inverted signal thereof in response to a bit information signal B3 having a high level or a low level. The binary voltage levels of the output signals of the differential driver 11 and the differential driver 12 are equal to ± 200 [mV], but the binary voltage level of the output signal of the differential driver 13 is ± 400 [mV], The absolute value is set higher than that of the differential drivers 11 and 12, and the differential drivers 11, 12, and 13 operate so as to transmit each output signal at the rising timing of the clock CLK.

  The signal transmission path 30 includes signal lines 31, 32, and 33. Here, the first output signal S <b> 11 a from the differential driver 11 and the inverted third output signal S <b> 13 b from the differential driver 13 are combined and sent to the signal line 31. Also, the second output signal S12a from the differential driver 12 and the inverted first output signal S11b from the differential driver 11 are combined and then sent to the signal line 32. Further, the third output signal S13a from the differential driver 13 and the inverted second output signal S12b from the differential driver 12 are combined and sent to the signal line 33.

  The signal receiver 20 includes three differential receivers 21, 22, and 23 that are bit information determiners (comprising comparators that determine whether the termination voltages V 1, V 2, and V 3 are negative), respectively. The clock recovery circuit 24, three termination resistors 41, 42, and 43 having resistance values R1, R2, and R3, a comparator 25 having a threshold voltage source 44, and an output signal from the comparator 25, respectively. The switches 26 and 27 that are controlled to be switched in conjunction with each other and an absolute value calculator 28 are provided. A termination resistor 41 is connected between the signal line 31 and the signal line 32, and the direction of the current flowing through the termination resistor 41 or the polarity of the termination voltage V <b> 1 generated in the termination resistor 41 is detected by the differential receiver 21. A termination resistor 42 is connected between the signal line 32 and the signal line 33, and the direction of the current flowing through the termination resistor 42 or the polarity of the termination voltage V <b> 2 generated in the termination resistor 42 is detected by the differential receiver 22. Further, a termination resistor 43 is connected between the signal line 33 and the signal line 31, and the direction of the current flowing through the termination resistor 43 or the polarity of the termination voltage V 3 generated in the termination resistor 43 is detected by the differential receiver 23.

  The clock recovery circuit 24 includes a rise detection circuit and a PLL circuit, and detects a clock CLK having a predetermined cycle by detecting a rising edge of a transmission signal transmitted to the three signal lines 31, 32, and 33. It reproduces and outputs to each differential receiver 21, 22, 23. Each differential receiver 21, 22, 23 executes bit information determination at the rising edge of the input clock CLK, as will be described later, and outputs bit information signals B1, B2, B3, respectively.

  After detecting the termination voltage V3 of the termination resistor 43, the absolute value calculator 28 calculates the absolute value | V3 | and outputs a voltage signal indicating it to the non-inverting input terminal (+) of the comparator 25. The comparator 25 compares the absolute value | V3 | of the termination voltage V3 with the threshold voltage Vth from the threshold voltage source 44, and when | V3 |> | Vth | , 27, the changeover switches 26, 27 are switched to the contact a side. On the other hand, when | V3 | ≦ | Vth |, a low-level control signal is output to the changeover switches 26, 27. , 27 are switched to the contact b side. Each differential receiver 21, 22, 23 executes bit information determination at the rising edge of the input clock CLK, as will be described later, and outputs bit information signals B1, B2, B3, respectively. Here, when the changeover switches 26 and 27 are switched to the contact a side (when the result of step S11 in FIG. 5 is YES, the processing of steps S21 to S23 is executed), the bit information signal from the differential receiver 21 B1 is output through the contact a side of the changeover switch 26, the bit information signal B2 from the differential receiver 22 is output through the contact a side of the changeover switch 27, and the bit information signal B3 from the differential receiver 23 is Output as is. On the other hand, when the changeover switches 26 and 27 are switched to the contact b side (NO in step S11 in FIG. 5, the processing in steps S12 to S14 is executed). Bit information signal B3 from the differential receiver 23 The bit information signal having the determination result (000 or 111) is output as the bit information signals B1, B2, and B3.

If the absolute values of the output signals of the differential drivers 11 and 12 are Vd1 and Vd2, respectively, and the absolute value of the binary signal voltage of the output signal of the differential driver 13 is Vd3, the setting condition (Vd3> In Vd1 = Vd2 (for example, when Vd1 = Vd2 = 200 [mV]; Vd3 = 400 [mV]), the bit information signals 000 and 111 are distinguished from all other bit information signals as follows. Can be executed under conditions.
(1) | Vd1 | = | Vd2 |
(2) When | Vd3 | ≠ | Vd1 |: Vd3 = Vd1, if the bit information signals 000 and 111 are sent, the potential difference between the signal lines becomes 0 and determination is impossible.
(3) When | Vd3 | ≠ | 3Vd1 |: Vd3 = 3Vd1, sending the bit information signals 010, 1011, 100, 101 causes 0 in the potential difference between the signal lines and makes determination impossible.
(4) | Vd3 |> | Vd1 | / 2: Since the threshold value | Vth |
(5) | Vd1-Vd3 | <| Vth |: a threshold value condition. As a result, only the comparator 25 and the absolute value calculator 28 can make the determination.

  In the first setting example, the threshold value Vth is set to be 200 [mV] <Vth <400 [mV], for example, Vth = 300 [mV].

  In this embodiment, the minimum voltage value X = 100 [mV] that can be detected by the differential receivers 21, 22, and 23, and the signal voltage levels of the differential driver 21 and the differential driver 22 are Vd 1 = Vd 2 = 200 [mV]. ] (= 2X), and the signal voltage level of the differential driver 23 is Vd3 = 400 [mV] (= 2Vd1). The voltages Vd1, Vd2, and Vd3 are set so as to satisfy the following expressions (1) and (2) with respect to the minimum detectable voltage value X. In this specification, the number number of the black brackets in which the mathematical formula is imaged and the formula number of the square brackets in which the mathematical formula is input are used in combination. The formula number is assigned to the last part of the formula using the formula (1) as the formula number (there is also a formula that is not given).

[Equation 3]
Vd1 ≧ 2X (1)

[Equation 4]
Vd1 + 2X ≦ Vd3 ≦ 3Vd1-2X (2)

  FIG. 2 is a signal waveform diagram showing signal waveforms of the output signals S11a, S11b, S12a, S12b, S13a, and S13b of the differential drivers 11, 12, and 13 of FIG. FIG. 3 is a waveform diagram showing the relationship between the signal waveforms of the signal voltages Vs1, Vs2, and Vs3 of the transmission signal transmitted through the signal lines 31, 32, and 33 of the signal transmission path 30 of FIG. is there. Each differential receiver 21, 22, 23 outputs the output signal shown in FIG. 2 according to the input bit information signal. At this time, the signal transmission is performed according to the input 3-bit bit information signal. Signal voltages Vs1, Vs2, and Vs3 of transmission signals transmitted through the signal lines 31, 32, and 33 of the path 30 are as shown in FIG.

Here, the signal voltages Vs1, Vs2, and Vs3 of the signal lines 31, 32, and 33 will be described. Signal voltages V _i1 and V _i2 from two differential drivers (11, 12; 12, 13; 13, 11) are superimposed on each signal line 31, 32, 33. The internal resistance of each differential driver 11, 12, 13 is r, and the impedance of the termination resistors 41, 42, 43 of the signal receiver 20 is Z (the input impedance of the differential receivers 21, 22, 23 is infinite ( And the signal voltage Vs generated on each signal line 31, 32, 33 is expressed by the following equation.

  Here, since r << Z, it is approximately expressed by the following equation.

  4 shows bit information transmitted in the multiplex differential transmission system of FIG. 1, signal voltages Vs1, Vs2, and Vs3 of transmission signals transmitted through the signal lines 31, 32, and 33, and terminal resistors of the signal receiver 30. FIG. It is a figure which shows the relationship between the termination voltage V1, V2, V3 of 41,42,43 and its polarity.

  As described above, the signal voltage level of only one differential driver 13 is set to a value different from the signal voltage level of the other differential drivers 11 and 12, and the circuit elements 25 to 28 forming all bit compensation circuits are provided. Thus, it is possible to decode the bit information signals in all eight states including the case where all bits are 0 and all bits are 1. In addition, the signal voltage applied to each signal line 31, 32, 33 of the signal transmission path 30 is 0 in total when any bit information signal is transmitted, and is radiated from each signal line 31, 32, 33. Since the noises cancel each other, transmission with less noise is possible as in the normal differential transmission method.

  FIG. 5 is a flowchart showing a first embodiment of bit information determination processing executed by the differential receivers 21, 22, 23 and the comparator 25 of the signal receiver 20 in the multiplex differential transmission system of FIG.

  In FIG. 5, first, in step S11, the comparator 25 determines whether or not the absolute value | V3 | of the termination voltage V3 of the termination resistor 43 exceeds the threshold value Vth. In the present embodiment, | V1-V3 | <| Vth | is preset in accordance with the above threshold value condition (| Vd1-Vd3 | <| Vth |). If NO in step S11, the process proceeds to step S12. If YES, the process proceeds to step S21, and the termination voltages Vi (i = 1, 2) of the termination resistors 41, 42, and 43 are detected by the differential receivers 21, 22, and 23. , 3) whether or not the polarity is negative. If YES, the process proceeds to step S22 to set 0 to the bit information signal Bi. If NO, the process proceeds to step S23 and 1 is set to the bit information signal Bi. Set. Then, the bit information determination process ends. In step S12, it is determined whether or not the termination voltage V3 of the termination resistor 43 is negative. If YES, the process proceeds to step S13, and all bit information signals B1, B2, B3 are set to 0. Proceeding to S14, all bit information signals B1, B2 and B3 are set to 1. Then, the bit information determination process ends.

  FIG. 6 is a diagram showing the relationship between the signal voltage Vd3 of the differential driver 13 and the voltage V1 across the termination resistor 41 in the multiplex differential transmission system of FIG. FIG. 7 is a diagram showing the relationship between the signal voltage Vd3 of the differential driver 13 and the voltage V2 across the termination resistor 42 in the multiple differential transmission system of FIG. FIG. 8 is a diagram showing the relationship between the signal voltage Vd3 of the differential driver 13 and the voltage V3 across the termination resistor 43 in the multiple differential transmission system of FIG. 6 to 8, the signal voltages Vd1 and Vd2 of the differential drivers 11 and 12 are fixed to 200 [mV], and the signal voltage Vd3 of the differential driver 13 is changed from 200 [mV] to 1200 [mV]. At this time, both-end voltages V1, V2, and V3 of the termination resistors 41, 42, and 43 change according to the values of the bit information signals B1, B2, and B3, as shown in FIGS.

  In order to detect the current direction in the differential receivers 21, 22 and 23, the potential difference applied between the non-inverting input terminal (+) and the inverting input terminal (−) of the differential receivers 21, 22 and 23 is detected. It must be greater than or equal to the minimum possible voltage value X.

  FIG. 9 is a diagram illustrating the relationship between the signal voltage Vd3 of the differential driver 13 and the absolute value of the minimum voltage of the differential receivers 21, 22, and 23 in the multiplex differential transmission system of FIG. The minimum voltage of the differential receivers 21, 22, and 23 coincides with the minimum value among the voltages V 1, V 2, and V 3 across the termination resistors 41, 42, and 43 shown in FIGS. In FIG. 9, the case where the minimum voltage value X that can be detected by the differential receivers 21, 22, and 23 is 100 [mV] is indicated by a dotted line. In this case, multiple differential transmission is possible when the signal voltage Vd3 of the differential driver 13 is 400 [mV] and when it is in the range of 800 [mV] or more. Here, since the power consumption of the entire system can be reduced if the signal voltage Vd3 of the differential driver 13 is as small as possible, the minimum signal voltage among the values capable of the multiple differential transmission is 400 [mV]. Most preferred.

  In FIG. 9, as another example, a case where the minimum detectable voltage value X is 50 [mV] is indicated by a one-dot chain line. In this case, assuming that the voltages Vd1 and Vd2 are 200 [mV], it is possible to construct multiple differential transmission in the range of 300 to 500 [mV] and the range of 700 [mV] or more according to the above-described equation. In order to reduce power consumption, a range of 300 to 500 [mV] is more preferable, and 300 [mV] is most preferable.

  Next, a method for calculating the relationship between the minimum detectable voltage value X and the signal voltages Vd1 and Vd3 shown in the above formulas (1) and (2) will be described. For example, when considered based on the relationship diagram of FIG. 6, the signal voltage Vd3 is calculated from the intersection C1 of the straight line indicating [B1, B2, B3] = 000 and the straight line indicating the minimum detectable voltage value X to [B1 , B2, B3] = 101 and the range up to the intersection C2 of the straight line indicating the minimum detectable voltage value X. When [B1, B2, B3] = 000, the voltage across the termination resistor 41 is (−Vd1 + Vd3) / 2 − (− Vd1 + Vd1) / 2, ie, (Vd3−Vd1), which is the difference voltage between the voltage Vs1 and the voltage Vs2. ) / 2, and when [B1, B2, B3] = 101, the voltage across the termination resistor 41 is (Vd1-Vd3) / 2-(-Vd1-Vd1) / 2, that is, (3Vd1-Vd3) / 2. It becomes. The intersection C1 is represented by X = (Vd3−Vd1) / 2, that is, the voltage Vd3 is (Vd1 + 2X). The intersection C2 is represented by X = (3Vd1-Vd3) / 2, that is, the voltage Vd3 is (3Vd1-2X). Therefore, the voltage Vd3 is in the range from (Vd1 + 2X) to (3Vd1-2X), and the above equation (2) is derived. The voltage Vd1 is derived from the relational expression Vd1 + 2X ≦ 3Vd1-2X from the above formula (2).

  As described above, according to the multiple differential transmission system according to the present invention, when the minimum voltage value detectable by the differential receivers 21 to 23 of the signal receiver 20 is X, the differential drivers 11 and 12 Since the signal voltage Vd1 of each output signal and the signal voltage Vd3 of the output signal of the differential driver 13 are set so as to satisfy Vd1 ≧ 2X and Vd1 + 2X ≦ Vd3 ≦ 3Vd1-2X, generation of noise is suppressed, and further In order to reduce the number of data signal lines, the differential transmission of 3-bit bit information signals can be realized with three signal lines, and all three bits can be transmitted, and the output driver voltage It is possible to prevent erroneous detection that may occur when the value is not appropriate, and to reduce power consumption by the output driver on the transmission side.

  According to the signal transmitter, the signal receiver, and the multiple differential transmission system according to the present invention, the differential transmission of the 3-bit bit information signal is performed in order to suppress the generation of noise and further reduce the data signal line. Can be realized with three signal lines, and all three bits can be transmitted, preventing false detection that can occur when the voltage value of the output driver is not appropriate, and power consumption by the output driver on the transmission side Can be reduced.

  The multiplex differential transmission system of the present invention can be used as a multi-bit transmission for a display for realizing a higher image quality than before and a high-speed transmission method in a device that needs to be downsized.

It is a block diagram which shows the structure of the multiple differential transmission system which concerns on one Embodiment of this invention. FIG. 2 is a signal waveform diagram showing signal waveforms of output signals S11a, S11b, S12a, S12b, S13a, and S13b of the differential drivers 11, 12, and 13 in FIG. FIG. 3 is a waveform diagram showing a relationship between signal waveforms of signal voltages Vs1, Vs2, and Vs3 of transmission signals transmitted via signal lines 31, 32, and 33 of the signal transmission path 30 of FIG. 1 and assigned bit information. The bit information transmitted in the multiplex differential transmission system of FIG. 1, the signal voltages Vs1, Vs2, and Vs3 of the transmission signals transmitted through the signal lines 31, 32, and 33, and the terminating resistors 41 and 42 of the signal receiver 30. , 43 is a diagram showing the relationship between the terminal voltages V1, V2, V3 and their polarities. 2 is a flowchart showing a first embodiment of bit information determination processing executed by each differential receiver 21, 22, 23 and comparator 25 of the signal receiver 20 in the multiple differential transmission system of FIG. FIG. 2 is a diagram illustrating a relationship between a signal voltage Vd3 of a differential driver 13 and a voltage V1 across a termination resistor 41 in the multiplex differential transmission system of FIG. FIG. 2 is a diagram illustrating a relationship between a signal voltage Vd3 of a differential driver 13 and a voltage V2 across a termination resistor 42 in the multiplex differential transmission system of FIG. FIG. 2 is a diagram illustrating a relationship between a signal voltage Vd3 of a differential driver 13 and a voltage V3 across a termination resistor 43 in the multiplex differential transmission system of FIG. FIG. 2 is a diagram illustrating a relationship between a signal voltage Vd3 of a differential driver 13 and an absolute value of a minimum voltage of differential receivers 21, 22, and 23 in the multiplex differential transmission system of FIG.

Explanation of symbols

10: Signal transmitter,
11, 12, 13 ... differential driver,
20 ... Signal receiver,
21, 22, 23 ... differential receiver,
24. Clock recovery circuit,
25 ... comparator,
26, 27 ... changeover switch,
28: Absolute value calculator,
30: Signal transmission path,
31, 32, 33 ... signal lines,
41, 42, 43 ... termination resistors,
44: Threshold voltage source.

Claims (3)

A multiple differential transmission system comprising: a signal transmitter; a signal receiver; and a signal transmission path including first, second, and third signal lines connecting between the signal transmitter and the signal receiver. In the signal transmitter for
A first differential driver for transmitting a first output signal and an inverted first output signal that is a phase inverted signal of the first output signal in response to the first bit information signal;
A second differential driver for transmitting a second output signal and an inverted second output signal that is a phase inverted signal of the second output signal in response to the second bit information signal;
In response to the third bit information signal, a third output signal having a signal voltage different from the first output signal and the second output signal, and an inverted third output signal that is a phase inverted signal of the third output signal; A third differential driver for transmitting
The first output signal and the inverted third output signal are combined and transmitted to the first signal line, and the second output signal and the inverted first output signal are combined and transmitted to the second signal line. Then, the third output signal and the inverted second output signal are combined and transmitted to the third signal line,
When the minimum detectable voltage value of the differential receiver of the signal receiver is X, the signal voltage Vd1 of the first output signal and the second output signal, and the signal voltage Vd3 of the third output signal,
[Equation 1]
Vd1 ≧ 2X
And [Equation 2]
Vd1 + 2X ≦ Vd3 ≦ 3Vd1-2X
A signal transmitter characterized by being set to satisfy 2. A multiplexing system comprising: the signal transmitter according to claim 1; a signal receiver; and a signal transmission path comprising first, second, and third signal lines connecting the signal transmitter and the signal receiver. In a signal receiver for a differential transmission system,
The polarity of a termination voltage generated in a first termination resistor connected between the first signal line and the second signal line is detected, and the detection result is output as a first bit information signal. A first differential receiver;
The polarity of the termination voltage generated in the second termination resistor connected between the second signal line and the third signal line is detected, and the detection result is output as a second bit information signal. A second differential receiver;
The polarity of the termination voltage generated in the third termination resistor connected between the third signal line and the first signal line is detected, and the detection result is output as a third bit information signal. A third differential receiver;
A determination unit that determines whether or not a voltage across the third termination resistor is greater than or equal to a threshold value,
When the voltage across the third termination resistor is greater than or equal to a threshold value, the first, second, and third differential receivers detect first, second, and third bit information, respectively, and the third termination resistor When the both-end voltage is less than the threshold value, only the detection result of the third differential receiver determines that all the bit information are all 0 or all are 1,
A signal receiver characterized in that the minimum detectable voltage value of the first, second and third differential receivers is X. A signal transmitter according to claim 1;
A multiple differential transmission system comprising the signal receiver according to claim 2.

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