JP2002231935A - Method of solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the electric charge-to-voltage transducer efficiency of an electric charge detecting section without causing a harmful influence on the other characteristics by reducing the impurity region of the electric charge detecting section. SOLUTION: On a silicon substrate 110 formed with a channel section 112, an insulation film 120 is formed. By pattering a photo resist and etching, a contact hole 116 is formed. The contact hole 116 is formed by a process independently of those for the other contact holes. Thereafter, impurities for forming an N+ region are doped in continuous processes to form an N+ region 14 self-aligned in the insulation film 120. The impurities are doped in several operations from a plurality of directions with the angle kept constant with respect to a substrate 110. Then, a pickup electrode 118 is formed, and a contact section 118A is formed in the contact hole 116.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a solid-state imaging device having an FD (floating diffusion) type charge detecting section.

[0002]

2. Description of the Related Art Conventionally, as a means for obtaining an image signal from a signal charge detected by a photosensor, a signal charge transferred by a charge transfer section to an impurity region provided in a semiconductor layer is guided by a MOS transistor. A solid-state device having a so-called FD (floating diffusion) type charge detection unit which is configured to convert a signal into a voltage signal corresponding to the potential of a signal charge by inputting the signal to a gate electrode of a configured output circuit. An imaging device is provided.

FIGS. 3A and 3B are a cross-sectional view and a plan view showing a structure of a portion of an impurity region (N + region) and a pickup electrode in such a conventional charge detecting portion, and FIG. FIG. 4 is a cross-sectional view showing a method of forming the impurity region shown in FIG. In FIG. 3, the N-type silicon substrate 10 has a P-
A channel well layer 11 is formed, and a channel portion 1 comprising an N- region serving as a charge transfer portion is formed on the P-type well layer 11.
2 is provided, and the N + region (FD portion) 14 for extracting electric charges described above is provided in a cylindrical shape at the final end. Then, a contact hole 16 is formed at the center of the N + region 14, and the contact portion 1 of the pickup electrode 18 for extracting electric charges is formed in the contact hole 16.
8A is provided, and is electrically connected to N + region 14. The pickup electrode 18 is wired on the N-type silicon substrate 10 via an insulating film 20 and is connected to the above-described input portion of the output circuit (eg, a gate electrode of a drive transistor).

In order to manufacture such a charge detecting portion, first, a region for forming an N + region 14 on a channel portion 12 of an N-type silicon substrate 10 by using a photoresist (not shown) is patterned. An impurity implantation (ion implantation) 22 is performed to form an N + region 14 (FIG. 4A). Next, an insulating film 20 is provided between the silicon substrate 10 and the pick-up electrode 18, and a contact region between the pick-up electrode 18 and the N + region 14 is patterned thereon with a photoresist, and then the insulating film 20 is etched. Then, a contact hole 16 is formed (FIG. 4B). Further, a pickup electrode 18 is provided on the contact hole 16 and connected to an input portion of an output circuit (FIG. 3).

[0005]

Incidentally, in this type of solid-state image pickup device, the output voltage tends to decrease due to the reduction in the pixel area accompanying the recent miniaturization of the optical system and the increase in the number of pixels. There is a problem that the sensitivity is reduced due to the reduction of the sensitivity. As one of the measures to cope with such a problem, an improvement in the conversion efficiency (hereinafter, simply referred to as conversion efficiency) of the charge-voltage conversion in the FD-type charge detection unit is required. Therefore, as a method of improving the conversion efficiency, a method of reducing the size of a drive transistor constituting an output circuit of a charge detection unit is known.
This method has disadvantages such as deterioration of S / N and frequency characteristics. On the other hand, as a means for improving the conversion efficiency without causing such adverse effects, it is conceivable to reduce the size of the N + region in the above-described charge detection unit. That is,
By reducing the size of the N + region, the parasitic capacitance with the P-type region such as a channel stop existing around the N + region can be reduced, so that conversion efficiency can be improved without adversely affecting other characteristics.

However, in the above-described method of forming a charge detecting portion in the conventional example, impurity implantation for obtaining an N + region is performed first, an insulating film is provided thereon, a contact hole is opened, and then a pickup electrode is mounted. Therefore, in the N + region, it is necessary to secure a margin (for example, a margin 24 shown in FIG. 4B) with respect to the processing accuracy such as a pattern shift and a variation in line width at the time of opening the contact. Is an obstacle in reducing the size of the device.

The opening of the contact hole is made at the same time as the opening of the contact portion of another portion, for example, the contact hole of the peripheral wiring portion. However, the diameter of the contact hole of the charge detection unit, which has been required in recent years, has become extremely small, and the conversion difference of the photoresist has a pattern size dependency. It is becoming difficult to form them as designed. Therefore, the size of the contact hole in the FD portion is inevitably increased, which is an obstacle in reducing the size of the N + region.

Accordingly, an object of the present invention is to provide a method of manufacturing a solid-state imaging device in which the impurity region of the charge detection section can be reduced in size, and conversion efficiency can be improved without adversely affecting other characteristics. Is to do.

[0009]

According to the present invention, there is provided a method of manufacturing a solid-state imaging device having an FD-type charge detecting portion, the method comprising the steps of: And an etching step of forming a contact hole for making contact between the impurity region and the pickup electrode, wherein the impurity implantation step is performed after the etching step. In the method of manufacturing a solid-state imaging device according to the present invention, when forming a charge detection portion, a semiconductor substrate is patterned and etched to form a contact hole for making contact between an impurity region and a pickup electrode. Next, impurities are implanted into the semiconductor substrate through the contact hole to form an impurity region into which signal charges from the charge transfer section are led.

As a result, the impurity region is formed in a self-aligned manner by the previously formed contact hole, and the displacement of the region with respect to the contact hole does not occur. Therefore, it is not necessary to secure a shift margin when forming the impurity region, and the impurity region of the charge detection unit can be reduced in size. As a result, the charge-to-voltage conversion efficiency of the charge detection unit can be improved without causing adverse effects on other characteristics, and it is possible to effectively cope with miniaturization of imaging pixels.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a method for manufacturing a solid-state imaging device according to the present invention will be described in detail. The embodiments described below are preferred specific examples of the present invention, and various technically preferable limitations are added. However, the scope of the present invention is not limited to the embodiments described below. The embodiments are not limited to these embodiments unless otherwise specified.

The manufacturing method according to the present embodiment provides an effective method for improving the charge-to-voltage conversion efficiency of a solid-state imaging device having an FD-type charge detection unit. , N + region (high-concentration N-type impurity-added region) is implanted in a continuous step immediately after an etching step for forming a contact hole for a pickup electrode. This enables the area to be reduced in size.
In this impurity implantation step, the impurity implantation direction is maintained in a fixed angle range with respect to the substrate surface of the semiconductor substrate, and the impurity implantation is performed in a plurality of times from multiple directions, so that the N + region is uniformly formed. It is intended to obtain various characteristics. Furthermore, by performing the step of opening a contact hole by etching separately from the step of opening a contact hole in another portion, fine processing of the contact hole is realized, and the size of the N + region can be further reduced. .

Hereinafter, specific embodiments will be described in detail with reference to the drawings. 1A and 1B are a cross-sectional view and a plan view showing a structure of a contact portion between an impurity region (N + region) of a charge detection unit and a pickup electrode according to an embodiment of the present invention. First, the configuration of the charge detection unit of the solid-state imaging device according to the present embodiment will be described with reference to FIG. First, an N-type silicon substrate 110 is provided with a photosensor of a solid-state imaging device and a charge transfer unit (not shown). FIG. 1 shows a structure of a peripheral portion of a final output stage of the charge transfer unit. That is, the N-type silicon substrate 11
0, a P-type well layer 111 is formed, and a channel portion 112 composed of an N-region (low-concentration N-type impurity-doped region) serving as a charge transfer portion is provided above the P-type well layer 111. The signal charges read from the photo sensor are transferred by the channel section 112 and supplied to the charge detection section shown in FIG.

The charge detecting section includes a charge extracting N + region (FD section) 1 provided at the final end of the channel section 112.
14 and a pick-up electrode 118 for picking up signal charges from the N + region 114. The pick-up electrode 118 is connected to an input portion (such as a gate electrode of a drive transistor) of an output circuit (not shown) for performing charge-voltage conversion. Have been. The N + region 114 is a region formed in a cylindrical shape. A contact hole 116 is formed in the center of the N + region 114. A contact portion 118A of the pickup electrode 118 is provided in the contact hole 116, and the N + region 114 is electrically connected to the N + region 114. It is connected. Also,
The pickup electrode 118 is wired on the N-type silicon substrate 110 via the insulating film 120, and is led to the above-described output circuit.

Next, a description will be given of a method of forming the charge detecting portion in the solid-state imaging device as described above. FIG. 2 (A),
2B is a cross-sectional view illustrating a method of forming the charge detection unit illustrated in FIG. 1, and FIG. 2A mainly illustrates an etching step of forming a contact hole of a pickup electrode;
(B) mainly shows the ion implantation step of the N + region.
A frame a in FIG. 2B shows a conventional ion implantation operation that does not employ the ion implantation method shown in FIG. 2B.

In this embodiment, first, the channel portion 112 is formed in the silicon substrate 110 by the same process as the conventional one.
To form Thereafter, an insulating film 120 is formed first, and a contact hole region having a desired size is patterned with a photoresist (not shown).
0 is etched (FIG. 2A). Immediately thereafter, an impurity implantation (ion implantation) 130 for forming an N + region is performed in a continuous process without patterning with a photoresist (FIG. 2B). By doing so, the N + region 114 is formed in the insulating film 120 in a self-aligned manner.
No displacement of the area with respect to 16 occurs at all. Therefore, it is not necessary to secure a shift margin, which is conventionally required for the N + region 114, so that the size can be reduced.

On the other hand, the impurity implantation is implanted at a certain angle with respect to the silicon substrate 110 in order to prevent the channeling, but when the contact hole 116 is downsized, the implantation angle and the thickness of the insulating film 120 are reduced. In some cases, as shown in a frame a of FIG. 2B, a shadow is formed on one side, and a region 140 where impurities are not effectively implanted is formed. Therefore, the biased N + region 11
4 ′ may be formed. Accordingly, here, the impurity implantation is performed in a plurality of directions in a plurality of directions while maintaining a certain angle (within a certain range) with respect to the substrate 110 as shown by 132 and 134 in FIG. ,
Since the impurity concentration of the N + region 114 can be formed uniformly while preventing channeling, a charge-voltage converter having stable characteristics can be formed.

Further, as described above, if the formation of the contact opening of the FD portion is performed simultaneously with the formation of the contact openings of the other positions, the opening of the FD portion having an extremely small size tends to widen. Therefore, in order to improve this, in the present embodiment, the contact opening step of the FD portion is different from that of the other portions. This makes it possible to execute the work by setting the exposure conditions for the photoresist patterning of the contact openings in the FD section exclusively, so that the opening size can be reduced.

In the method of manufacturing a solid-state imaging device according to the present embodiment as described above, the following effects can be obtained. (1) By implanting impurities for forming the N + region in the contact portion of the charge detection portion in a continuous process after the opening of the contact hole, the size of the N + region can be reduced, and the conversion efficiency can be improved. (2) Impurity implantation for forming an N + region in the contact portion of the charge detection section is performed in a continuous process after the opening of the contact hole, so that a photoresist patterning step for determining the N + impurity implantation region can be reduced. (3) Impurity implantation for forming an N + region in a contact portion of a small charge detection unit is performed a plurality of times in multiple directions while maintaining a certain angle with respect to a substrate. Since the concentration can be made uniform, a charge-voltage converter having stable characteristics can be formed. (4) By performing the step of opening the contact hole in the contact section of the charge detection section separately from the step of opening the contact hole in the other positions, the exposure conditions for photoresist patterning can be set independently, so the opening size Can be reduced in size. By the above method, the charge-voltage conversion efficiency can be improved, and the sensitivity and size of the imaging device can be increased.

[0020]

As described above, in the method of manufacturing a solid-state imaging device according to the present invention, when forming the FD type charge detecting portion,
An impurity implantation step of forming an impurity region into which a signal charge from the charge transfer unit is introduced into the semiconductor substrate is performed after an etching step of forming a contact hole for making contact between the impurity region of the charge detection unit and the pickup electrode. . For this reason, the impurity region is formed in a self-aligned manner by the previously formed contact hole, and it is not necessary to secure a shift margin, so that the impurity region of the charge detection unit can be downsized. As a result, the charge-to-voltage conversion efficiency of the charge detection unit can be improved without causing any adverse effect on other characteristics, and an effect of effectively responding to miniaturization of imaging pixels can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view and a plan view showing a structure of a contact portion between a pickup electrode and an impurity region of a charge detection unit in a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of forming the charge detection unit shown in FIG.

3A and 3B are a cross-sectional view and a plan view showing a structure of a contact portion between an impurity region of a charge detection unit and a pickup electrode in a conventional solid-state imaging device.

FIG. 4 is a cross-sectional view illustrating a method of forming the charge detection unit illustrated in FIG.

[Explanation of symbols]

110 ... N-type silicon substrate, 112 ... channel part,
114... N + region, 116... Contact hole, 1
18 ... Pickup electrode, 118A ... Contact part, 120 ... Insulating film.

Claims (7)

[Claims] 1. A method of manufacturing a solid-state imaging device having an FD-type charge detection unit, comprising: an impurity implantation step of forming an impurity region into which a signal charge from a charge transfer unit is introduced in a semiconductor substrate; An etching step of forming a contact hole for making contact with the semiconductor device, wherein the impurity implantation step is performed after the etching step. 2. The method according to claim 1, wherein the impurity implantation step is performed in a continuous step immediately after the etching step. 3. The method according to claim 2, wherein after the etching step, the impurity implantation step is performed without providing a new photoresist pattern. 4. The solid-state imaging device according to claim 1, wherein after an insulating film is provided on the semiconductor substrate, an etching step for forming the contact hole is performed, and the impurity implantation step is performed through the contact hole. Manufacturing method. 5. The method according to claim 4, wherein in the impurity implantation step, the impurity is implanted a plurality of times from a plurality of different directions while maintaining a certain angle with respect to the substrate surface of the semiconductor substrate. A method for manufacturing a solid-state imaging device. 6. The method according to claim 1, wherein, in the etching step, the step of opening the contact hole is performed separately from the step of opening other contact holes. 7. The method according to claim 1, wherein the impurity region is a region to which a high concentration N-type impurity is added.