JP2002223371A - Synchronizing separator circuit, its separating method, phase detection circuit, its detecting method, phase synchronizing circuit and its synchronizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To construct a PLL system provided with excellent jitter performance. SOLUTION: Video data converted into digital data by an A/D converter 21 is outputted to an adder 24 by a switch 23 which is controlled based on a signal inputted from a comparator 22 when a video signal is lower than a threshold level. The adder 24 adds the outputs of the switch 23 and a register 25. A switch 26 supplies the output of the adder 24 to a register 27 when a reference pulse (pulse A) is an H level and to a register 28 in the case of L level. The output of an adder 29 is obtained by subtracting the output of the register 28 from the output of the register 27 and, then, a filter 30 performs calculation once in one cycle of the pulse A by synchronization with the timing of a pulse B. An oscillator 31 changes an oscillation frequency in accordance with the output of the filter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronization separation circuit and a synchronization separation method, a phase detection circuit and a phase detection method, and a phase synchronization circuit and a phase synchronization method.
The present invention relates to a synchronization separation circuit and a synchronization separation method, a phase detection circuit and a phase detection method, and a phase synchronization circuit and a phase synchronization method suitable for performing digital signal processing.

[0002]

2. Description of the Related Art In a horizontal synchronizing circuit in a television system, a horizontal synchronizing signal is used as a comparison pulse and a VCO (Vo
PLL that uses the output of a ltage controlled oscillator (voltage controlled oscillator) divided by the dividing ratio N as a reference pulse
(Phase Locked Loop) Various timing pulses are generated by the system. PLL means that a reference signal input from the outside and an output of an oscillator (VCO) in a loop or an output of the oscillator are divided by a dividing ratio N.
Is an oscillation circuit that adjusts the oscillation frequency by performing feedback control on the oscillator in the loop so that the pulse signal divided by the above has the same frequency and phase.

FIG. 1 shows a circuit configuration of a PLL system used in a conventional television system.

A comparator 1 receives a video signal including a horizontal synchronizing signal, compares the threshold level with the video signal, separates the horizontal synchronizing signal from the video signal, and outputs it to a phase detector 2. .

The phase detector 2 receives a horizontal synchronizing signal input from the comparator 1 and a reference pulse (ref pulse) which is an output signal of a 1 / N frequency divider 5 described later.
The phase comparison is performed, and the phase difference component is output to the filter 3 as a pulse-like phase difference signal. The filter 3 removes high frequency components from the input signal and outputs the signal to the 1 / N frequency divider 5.

FIG. 2 shows a detailed configuration of the phase detector 2 and the filter 3.

The current sources 11-1 and 11 of the phase detector 2
-2 is turned ON only in the horizontal synchronization section based on the input horizontal synchronization signal. When the output signal (reference pulse) of the 1 / N divider 5, which is the reference pulse, is at the H level, the switch 12-1 is turned on and the switch 12-2 is turned off, so that a current is injected into the filter 3. (Route 1 in the figure
Current flows in the direction shown in FIG. On the other hand, when the reference pulse is at the L level, the switch 12-2
Is turned on and the switch 12-1 is turned off, so that current is drawn from the filter 3 (current flows in the direction indicated by the path 2 in the figure).

As the filter 3, a lag lead type filter is used. Also, a capacitor C2 provided in parallel with the resistor R1, the resistor R2 and the capacitor C1.
Is provided to stabilize the system at high frequencies.

Returning to the description of FIG. The phase difference signal from which the high frequency component output from the filter 3 has been removed is input to the VCO 4. The VCO 4 changes the oscillation frequency in a direction to eliminate the phase difference between the input reference pulse and the output pulse based on the input phase difference signal, and outputs the oscillation frequency to the 1 / N divider 5. For the VCO 4, for example, a crystal oscillator is used.
A so-called VC that changes the load capacitance of the crystal with a varicap (variable capacitance diode) to slide the oscillation frequency
XO (Voltage Controlled X-tal Oscillator) is used.

The 1 / N frequency divider 5 divides the input signal by a frequency division ratio N to generate a reference pulse, and outputs the reference pulse to the phase detector 2.

[0011]

At present, so-called digital signal processing, which does not process video signals as analog signals but processes them as discrete numerical values, has become mainstream.
Therefore, since the video signal is also represented by a discrete numerical value, its temporal change in the numerical value also takes a discrete value. However, the PLL system described with reference to FIGS. 1 and 2 is a circuit for processing an analog signal. Therefore, when the PLL system receives a digital video signal, the output of the horizontal synchronizing signal takes a discrete value limited by the clock frequency (sampling frequency). Therefore, the output of the phase detector 2 is also discrete, so that the output from the VCO 4 has a lot of jitter.

In order to avoid such a problem, it is necessary to make the time constant of the filter 3 sufficiently large, but by doing so, the transient response characteristic is greatly deteriorated. Also, by increasing the resolution of the phase detector 2,
There is also a method of substantially increasing the clock frequency.
However, the jitter performance required for a PLL system used for horizontal synchronization in a television system is about 1 nS, and there is a limit to simply increasing the clock frequency.

The present invention has been made in view of such a situation, and the output of the horizontal sync separation circuit is the video data itself or the difference between the video data and a comparison level (threshold level), Within these, the data is added and treated as a signal corresponding to the output of the phase detector, so that the resolution and jitter performance of the phase detection can be improved.

[0014]

A first synchronizing separation circuit according to the present invention includes a comparing means for comparing a video signal containing a composite synchronizing signal and represented by a discrete numerical value with a predetermined threshold value, and a comparing means. And output means for outputting the video signal as a synchronization signal when it is determined that the video signal is in the synchronization section based on the comparison result of the above.

According to a first synchronization separation method of the present invention, a comparison step of comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value; An output step of outputting the video signal as a synchronization signal when the video signal is determined to be in the synchronization section based on the video signal.

A second synchronization separating circuit according to the present invention includes a comparing means for comparing a video signal, which includes a composite synchronizing signal and is represented by a discrete numerical value, with a predetermined threshold value, based on a comparison result by the comparing means. And output means for outputting a difference between the video signal and the threshold value as a synchronization signal when the video signal is determined to be in the synchronization section.

According to a second synchronization separation method of the present invention, a comparison step of comparing a video signal containing a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value, and comparing the comparison result by the processing of the comparison step An output step of outputting a difference between the video signal and the threshold value as a synchronization signal when the video signal is determined to be in the synchronization section based on the video signal.

A phase detection circuit according to the present invention includes a comparing means for comparing a video signal, which includes a composite synchronization signal and is represented by a discrete numerical value, with a predetermined threshold value, and a video signal based on a comparison result by the comparing means. If the signal is determined to be in the synchronization interval,
A first output unit that outputs a synchronization signal, a first signal holding unit that adds and holds an input signal at a constant cycle, and adds and holds an input signal at a fixed cycle. A second signal holding unit, an input unit receiving a reference pulse, and a synchronization signal output from the first output unit.
A second output unit for selectively outputting to the first signal holding unit or the second signal holding unit based on a phase of the reference pulse input by the input unit; a first signal holding unit; And a calculating means for calculating a difference between the signals held by the second signal holding means and a phase difference between the reference pulse and the synchronization signal.

[0019] The synchronization signal output by the first output means may be a video signal.

The synchronization signal output from the first output means may be a difference between the video signal and a threshold.

According to the phase detection method of the present invention, a comparison step of comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value is performed based on a comparison result by the processing of the comparison step. A first output step of outputting a synchronization signal when the video signal is determined to be in a synchronization section; a first signal holding step of adding and holding the input signal at a constant cycle; A second signal holding step of adding and holding the obtained signals at a constant cycle, an input step of receiving an input of a reference pulse, and a synchronization signal output by the processing of the first output step. Based on the phase of the reference pulse input by the processing, selected to be held by the processing of the first signal holding step or to be held by the processing of the second signal holding step And the difference between the signal held by the processing of the first signal holding step and the signal held by the processing of the second signal holding step, and the difference between the reference pulse and the synchronization signal. Calculating a phase difference.

A phase synchronization circuit according to the present invention includes a comparison means for comparing a video signal, which includes a composite synchronization signal and is represented by a discrete numerical value, with a predetermined threshold value, and a video signal based on a comparison result by the comparison means. If the signal is determined to be in the synchronization interval,
First output means for outputting a synchronization signal, oscillating means for oscillating a signal of a predetermined frequency, and reference pulse generation for generating a reference pulse by dividing the frequency of the signal oscillated by the oscillating means by a natural number N Means, first signal holding means for adding and holding an input signal at a fixed cycle, second signal holding means for adding and holding an input signal at a fixed cycle, The synchronization signal output from the first output means is converted to the first signal holding means or the second signal holding means based on the phase of the reference pulse generated by the reference pulse generation means.
Second output means for selectively outputting the signal to the signal holding means;
Calculating means for calculating a difference between signals held in the first signal holding means and the second signal holding means as a phase difference between the reference pulse and the synchronization signal; and a phase difference calculated by the calculating means. Signal smoothing means for smoothing and outputting a signal to be output, wherein the oscillating means changes an oscillating frequency based on a signal corresponding to the phase difference outputted by smoothing by the signal smoothing means. .

[0023] The synchronization signal outputted by the first output means may be a video signal.

The synchronization signal output by the first output means may be a difference between a video signal and a threshold.

According to the phase synchronization method of the present invention, a comparison step of comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value is performed based on a comparison result by the processing of the comparison step. When it is determined that the video signal is in the synchronization section, a first output step of outputting a synchronization signal, an oscillation step of oscillating a signal of a predetermined frequency, and a frequency of the signal oscillated by the processing of the oscillation step are performed. A reference pulse generating step of generating a reference pulse by dividing by a natural number N, a first signal holding step of adding and holding an input signal at a fixed cycle, and A second signal holding step of adding and holding the signals in a cycle, and a synchronizing signal output by the processing of the first output step, the position of the reference pulse generated by the processing of the reference pulse generating step. A second output step of selectively outputting the first signal holding step for holding the signal by the processing of the first signal holding step or holding the signal by the processing of the second signal holding step based on A calculating step of calculating a difference between the signal held by the processing of the step and the signal held by the processing of the second signal holding step as a phase difference between the reference pulse and the synchronization signal; A signal smoothing step of smoothing and outputting a signal corresponding to the calculated phase difference. The oscillating step oscillates based on a signal corresponding to the phase difference smoothed and output by the processing of the signal smoothing step. It is characterized in that the frequency is changed.

In the first synchronization separation circuit and the first synchronization separation method of the present invention, a video signal including a composite synchronization signal and represented by a discrete numerical value is compared with a predetermined threshold, and the comparison result is obtained. If the video signal is determined to be in the synchronization section based on the video signal, the video signal is output as a synchronization signal.

In the second sync separation circuit and the second sync separation method of the present invention, a video signal including a composite sync signal and represented by a discrete numerical value is compared with a predetermined threshold value, and the comparison result is obtained. If the video signal is determined to be in the synchronization section based on the difference, the difference between the video signal and the threshold is output as a synchronization signal.

In the phase detection circuit and the phase detection method of the present invention, a video signal including a composite synchronization signal and represented by a discrete numerical value is compared with a predetermined threshold value, and based on the comparison result, the video signal is determined. Is determined to be a synchronization section, a synchronization signal is output, a reference pulse is input, and the output synchronization signal is selectively output to two locations based on the phase of the input reference pulse. The signals are added and held at a constant cycle, and the difference between these signals is calculated as the phase difference between the reference pulse and the synchronization signal.

In the phase synchronization circuit and the phase synchronization method according to the present invention, a video signal including a composite synchronization signal and represented by a discrete numerical value is compared with a predetermined threshold, and based on the comparison result, the video signal is determined. Is determined to be a synchronization section, a synchronization signal is output, a signal of a predetermined frequency is oscillated, and the frequency of the oscillated signal is divided by a natural number N to generate a reference pulse. The synchronization signal is selectively output to two locations based on the phase of the generated reference pulse, added and held at a constant period, and the difference between those signals is defined as the phase difference between the reference pulse and the synchronization signal. The calculated and corresponding signal corresponding to the phase difference is smoothed and output, and the oscillating frequency is changed based on the smoothed and output signal corresponding to the phase difference.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram showing a configuration of a PLL system to which the present invention is applied.

The A / D converter 21 samples an input analog video signal based on a clock signal (CLK) of 13.5 MHz or 27 MHz, for example, oscillated from the oscillator 31 and converts the sampled analog video signal into a digital signal. And output. The input video signal passes through a low-pass filter having a band equal to or lower than the Nyquist frequency in order to prevent aliasing of the signal. The signal limited to the low band is sampled at a predetermined sampling rate. A / D
In the converter 21, a filter is also provided at a stage after the sampling. In order to obtain a good synchronization performance even for a signal having a deteriorated S / N ratio, a band limitation at a lower frequency is performed before performing synchronization separation. Done.

The comparator 22 compares the input digital video signal with a predetermined threshold level, and controls the switch 23 based on the result of the comparison. The switch 23 selects a signal to be supplied to the adder 24 based on the comparison result input from the comparator 22. That is, when the level of the video signal is lower than the threshold level, the terminal a is selected, and the output signal of the A / D converter 21 is supplied to the adder 24. When the level of the video signal is higher than the threshold level, the terminal b is connected. Selected, adder 2
4 is supplied with a ground level signal (voltage 0 V).

The adder 24 adds the signal supplied through the switch 23 and the output of the register 25. The output of the adder 24 is supplied to a register 25 and a switch 26. The register 25 is reset by an output signal of the OR gate 32 that has received a pulse B and a pulse C output from the timing generator 33 described later.

The switch 26 selects the supply destination of the output signal of the adder 24 based on the pulse A (reference pulse) output from the timing generator 33. Here, when the pulse A is at the H level, the output of the adder 24 is
When the pulse A is supplied to the register 27 and the pulse A is at the L level,
The output of the adder 24 is supplied to the register 28. The register 27 is reset by a pulse B generated by the timing generator 33, and the register 28 is reset by a pulse C generated by the timing generator 33.

The outputs of the register 27 and the register 28 are supplied to an adder 29, where the difference between them is calculated and output to the filter 30. In the filter 30, for example,
A lag lead filter is used. The signal input to the filter 30 is supplied to the oscillator 31 from which high-frequency components have been removed. Here, it is assumed that the filter 30 performs the calculation in synchronization with the pulse B output from the timing generator 33.

The oscillator 31 changes the oscillation frequency of the output signal based on the signal input from the filter 30. The type of the oscillator 31 is, for example, a VCO (Voltage Co.)
ntrolled Oscillator) and DTO (Discrete Timing)
Oscillator). The clock output from the oscillator 31 is supplied to the A / D converter 21, the register 25, the register 27, and the register 28 as a clock signal for controlling the operation. Supplied as a signal.

The timing generator 33 includes the oscillator 3
A pulse A, which is a reference pulse (ref pulse) obtained by dividing the clock signal output from 1 by 1 / N, a pulse B output in synchronization with the falling edge of the reference pulse, and a reference pulse And generates and outputs a pulse C output in synchronization with the rising edge of.

Here, the output of the filter 30 is composed of a horizontal synchronizing signal combined with an input video signal and an oscillator 3
Timing generator 3 based on the signal oscillated from 1
3 and the phase of the reference pulse generated in step 3. Therefore, the switches 23 to the adders 29
It can be seen that the same operation as that of the phase detector 2 in the conventional PLL system described with reference to FIG.

FIG. 4 is a timing chart showing the operation of each unit when the PLL system described with reference to FIG. 3 is stabilized.

The A / D converter 21 limits the input video data to low-frequency components, converts the data into digital data, and outputs the digital data to the switch 23. The switch 23 outputs a signal supplied from the A / D converter 21 to the adder 24 when the video signal is lower than the threshold level based on the signal input from the comparator 22.

The pulse A output from the timing generator 33 is a reference pulse obtained by dividing the output of the oscillator 31 by 1 / N. The pulse B is output in synchronization with the falling edge of the reference pulse. The pulse C is output in synchronization with the rising edge of the reference pulse.

The output of the adder 24 is supplied to the register 27 by the switch 26 when the pulse A is at the H level and to the register 28 when the pulse A is at the L level.

The register 27 is reset by the pulse B. That is, the register 27 holds data when the reference pulse changes from the H level to the L level. The register 28 is reset by the pulse C. That is, the register 28 holds data when the reference pulse changes from the L level to the H level.

The output of the adder 29 is
7, the output of the register 28 is subtracted from the output of 7, and the filter 30 performs an operation once in one cycle of the pulse A in synchronization with the timing of the pulse B.

FIG. 5 shows an example of the phase between the input video signal and the reference pulse.

The video signal is sampled at a predetermined sampling rate. The video signal is sampled m times within a period below the threshold level.
If n times are sampled when the reference pulse is at the H level and the remaining (mn) times are sampled when the reference pulse is at the L level, the value held in the register 27 is D1 + D2 +. + Dn, and the value held in the register 28 is D (n + 1) +
D (n + 2) +... + Dm.

In the case of FIG. 5, it is assumed that the video signal is sampled 16 times in a period in which the video signal is lower than the threshold level, but the sampling rate may be other values.

In FIG. 5, when the PLL system is stabilized to some extent and the video signal sampled when the reference pulse is at the H level is the signal D1 to the signal D8 out of the 16 samplings, it is held in the register 27. .. + D8, and the value held in the register 28 is D9 + D10 +.
D16.

The bottom part of the synchronization signal (D in FIG. 5)
3 to D14) ideally always take the same data, so that D3 to D14 are all equal values.
Therefore, assuming that the output of the adder 29 for obtaining the difference between the register 27 and the register 28 is ΔD, the output ΔD can be expressed as follows: ΔD = D1 + D2−D15−D16 (1)

Even if the oscillation frequency of the oscillator 31 is slightly changed based on the value of ΔD and the phase of the sampling point changes, the change is slight, and the total number of sampling points does not change. ,
When the next output of the adder 29 is ΔD ′, the output ΔD ′
ΔD ′ = D1 ′ + D2′−D15′−D16 ′ (2) Therefore, the change amount ΔD−ΔD ′ of the output of the adder 29 is given by ΔD−ΔD ′ = (D1 + D2−D15−D16) − (D1 ′ + D2′−D15′−D16) from Expressions (1) and (2). ') = ΔD1 + ΔD2-ΔD15-ΔD16 (3), which is equal to the change of each sampling point.

The oscillation frequency of the oscillator 31
Is controlled by the output. Therefore, if the oscillation frequency of the oscillator 31 is set to fosc, fosc is expressed by the following equation (4) as a function controlled by the change amount ΔD−ΔD ′ of the output of the adder 29 input to the filter 30. Can be. fosc = f (ΔD−ΔD ′) (4)

Here, the variation ΔD−
Since ΔD ′ is a discrete numerical value, the oscillation frequency fosc of the oscillator 31 also takes a discrete numerical value. Considering the transition of the oscillation frequency fosc of the oscillator 31 per step, that is, the resolution, if the oscillation frequency fosc is a linear function, the resolution is represented by the reciprocal of ΔD−ΔD ′. In order to improve the jitter performance as a PLL system, it is necessary to improve this resolution. To do so, the resolution of the change amount ΔD−ΔD ′ (ie,
Bit accuracy).

The resolution of the variation ΔD−ΔD ′ is 1 bit,
That is, in the case of a pulse, the jitter performance is the reciprocal of the sampling frequency. The input video signal is A / D
When converted into a digital signal by the converter 21, even if the signal passes through a low-pass filter that passes only signals in the band equal to or lower than the Nyquist frequency,
In order to obtain good synchronization performance, band limitation at a lower frequency is performed. Therefore, the switch 26 does not receive such a steep signal that no sampling data exists in the slope portion of the pulse in FIG.

For example, when a video signal limited to a band of 6.75 MHz or less is sampled at a clock frequency of 13.5 MHz and is limited to 1 MHz (time constant of 0.16 μS) by a subsequent filter, the video signal is From the pedestal level to the bottom portion of the horizontal synchronizing signal, it falls to about 63.2% with a time constant of 0.16 μS.
At this time, since the sampling cycle is 74.07 nS, the A / D converter 21 can obtain two pieces of sampling data in the section of 0.16 μS corresponding to the slope portion of the pulse.

Here, the jitter performance of the PLL system is 1
In order to suppress the change amount to about nS, it is sufficient that the resolution of the change amount ΔD−ΔD ′ is X and the bit precision satisfies the following expression (5). That is, when the data of the video signal can be sampled with an accuracy of 6 bits or more, the jitter performance of the PLL system can be suppressed to about 1 nS.

By adopting such a configuration, a PLL system having good jitter performance can be constructed without increasing the sampling frequency more than necessary. Further, a phase detection portion (from the switch 23 to the adder 2)
The output of 9) has information on the integrated value of the signal level in the horizontal synchronizing signal section, and the total loop gain of the PLL system is varied by the integrated value.
Therefore, a signal having a poor S / N ratio such as a weak electric field is input,
When the level of the horizontal synchronizing signal is reduced, the total loop gain of the PLL system is automatically reduced, so that the sensitivity to noise is reduced and good synchronization performance can be obtained.

When the sampled video signal is close to the threshold level of the comparator 22, in the PLL system described with reference to FIG. 3, when the sampling data near the threshold level is selected due to slight phase fluctuation. May not be considered. P
Even in a state where LL is stable, slight phase fluctuation occurs. Therefore, whether or not sampling data near the threshold level is input to the adder 24 affects the final oscillation frequency of the oscillator 31. Would. For this reason, the jitter performance of the PLL system may be deteriorated.

FIG. 6 shows a PLL system in which this is improved. Parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. That is, FIG.
In the PLL system of the first embodiment, an adder 41 is newly provided, and the difference between the output of the A / D converter 21 and the threshold level is output to the switch 23 with reference to FIG. It has the same configuration as the PLL system described above.

The comparator 22 compares the output of the A / D converter 21 with the threshold level, as in the case described with reference to FIG. 3, so that the video signal converted to a digital signal is at a level higher than the threshold level. If so,
The switch 23 is controlled to be connected to the terminal b so that the adder 24 is supplied with the ground level voltage (voltage 0 V). When the video signal converted into the digital signal is at a level lower than the threshold level, the switch 23 is turned on. Is connected to the terminal a, and the output of the adder 41 (A
The difference between the output of the / D converter 21 and the threshold level) is supplied to the adder 24.

With the circuit configuration shown in FIG. 6, when the output of the A / D converter 21 has a value close to the threshold level, the data supplied to the adder 24 has a value close to zero. Therefore, when the video signal is close to the threshold level, the fluctuation of the output result as the phase detector can be suppressed regardless of the comparison result of the comparator 22, thereby improving the jitter performance as the PLL system. Can be.

[0062]

According to the present invention, the first synchronization separating circuit and the first synchronization separating circuit of the present invention are provided.
According to the sync separation method, the video signal including the composite sync signal and represented by a discrete numerical value is compared with a predetermined threshold, and based on the comparison result, the video signal is determined to be in the synchronization section. In this case, since the video signal is output as a synchronization signal, the data of the video signal can be used for phase detection.

According to the second synchronization separation circuit and the second synchronization separation method of the present invention, a video signal including a composite synchronization signal and represented by a discrete numerical value is compared with a predetermined threshold value.
Based on the comparison result, when it is determined that the video signal is in the synchronization section, the difference between the video signal and the threshold is output as a synchronization signal, so even when the video signal is close to the threshold level, the output result is Can be suppressed, and the jitter performance as a PLL system can be improved.

According to the phase detection circuit and the phase detection method of the present invention, a video signal including a composite synchronization signal and represented by a discrete numerical value is compared with a predetermined threshold value, and based on the comparison result, If it is determined that the signal is a synchronization section, output a synchronization signal, receive the input of the reference pulse, the output synchronization signal, based on the phase of the input reference pulse,
The signals are selectively output to two points, added and held at a constant period, and the difference between these signals is calculated as the phase difference between the reference pulse and the synchronization signal. Even in the case of inputting, good synchronization performance can be obtained.

According to the phase synchronization circuit and the phase synchronization method of the present invention, a video signal including a composite synchronization signal and represented by a discrete numerical value is compared with a predetermined threshold value, and based on the comparison result, When it is determined that the signal is in the synchronous section, a synchronous signal is output, a signal of a predetermined frequency is oscillated, a frequency of the oscillated signal is divided by a natural number N to generate a reference pulse, and the signal is output. The synchronization signal is selectively output to two locations based on the phase of the generated reference pulse, added and held at a constant period, and the difference between those signals is calculated as the phase difference between the reference pulse and the synchronization signal. The signal corresponding to the phase difference is smoothed and output, and the frequency of oscillation is changed based on the signal corresponding to the smoothed and output phase difference, so that it has good jitter performance. Building a PLL system It can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conventional PLL system.

FIG. 2 is a diagram illustrating a detailed configuration of a phase detector and a filter of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a PLL system to which the present invention is applied.

FIG. 4 is a timing chart showing an operation of the PLL system of FIG. 3;

FIG. 5 shows the phases of a video signal and a reference pulse,
FIG. 3 is a diagram for describing a signal to be sampled.

FIG. 6 is a block diagram showing a configuration of a PLL system to which the present invention is applied.

[Explanation of symbols]

21 A / D converter, 22 comparator, 23 switch, 24 adder, 25 register, 26
Switch, 27, 28 register, 29 adder,
Reference Signs List 30 filter, 31 oscillator, 32 OR gate, 33 timing generator, 41 adder

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takayu Nagamine 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Satoshi Miura 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo No. within Sony Corporation (72) Inventor Yumiko Mito 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo F-term within Sony Corporation (reference) 5C020 AA09 BA01 BA11 BB01 CA15 5J106 AA04 CC01 CC25 CC38 CC41 DD06 DD09 DD13 DD38 DD42 DD43 DD46 DD48 FF06 JJ02 KK22 KK25

Claims (12)

[Claims] 1. A comparing means for comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value, and based on a comparison result by the comparing means, the video signal is used in a synchronization section. Output means for outputting the video signal as a synchronization signal when it is determined that there is a synchronization signal. 2. A comparing step of comparing a video signal containing a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value; and synchronizing the video signal based on a comparison result by the processing of the comparing step. Outputting the video signal as a synchronization signal when it is determined to be a section. 3. A comparison means for comparing a video signal, which includes a composite synchronization signal and is represented by a discrete numerical value, with a predetermined threshold value, based on a comparison result by the comparison means, Output means for outputting a difference between the video signal and the threshold value as a synchronization signal when it is determined that there is a synchronization signal. 4. A comparing step of comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value, and synchronizing the video signal based on a comparison result by the processing of the comparing step. Outputting a difference between the video signal and the threshold value as a synchronizing signal when it is determined that the section is a section. 5. A comparing means for comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value, and based on a comparison result by the comparing means, the video signal is synchronized in a synchronization section. If it is determined that the first and second signals are the same, a first output means for outputting a synchronization signal, and a first means for adding and holding the input signal at a constant cycle
And a second signal holding means for adding and holding the input signals at a constant cycle.
A signal holding means, an input means for receiving an input of a reference pulse, and a synchronizing signal output from the first output means.
A second output unit for selectively outputting to the first signal holding unit or the second signal holding unit based on a phase of the reference pulse input by the input unit; A phase detection circuit comprising: signal holding means; and calculation means for calculating a difference between signals held in the second signal holding means as a phase difference between the reference pulse and the synchronization signal. 6. The phase detection circuit according to claim 5, wherein the synchronization signal output by the first output means is the video signal. 7. The phase detection circuit according to claim 5, wherein the synchronization signal output by the first output means is a difference between the video signal and the threshold. 8. A comparing step of comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value, and based on a comparison result by the processing of the comparing step, the video signal is A first output step of outputting a synchronization signal when it is determined to be a synchronization section; and a first step of adding and holding the input signal at a constant cycle.
And a second signal holding step of adding and holding the input signals at a constant cycle.
A signal holding step, an input step of receiving an input of a reference pulse, and the synchronizing signal output by the processing of the first output step, based on a phase of the reference pulse input by the processing of the input step. A second output step of selectively outputting for holding by the processing of the first signal holding step or holding by the processing of the second signal holding step; and the first signal holding step. And a calculating step of calculating a difference between the signal held by the processing of step (b) and the signal held by the processing of the second signal holding step as a phase difference between the reference pulse and the synchronization signal. Phase detection method. 9. A comparing means for comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value, and based on a comparison result by the comparing means, When it is determined that the signal is a first signal, a first output means for outputting a synchronization signal, an oscillating means for oscillating a signal having a predetermined frequency, A reference pulse generating means for generating a reference pulse by circulating a signal;
And a second signal holding means for adding and holding the input signals at a constant cycle.
Signal holding means, and the synchronization signal output by the first output means,
A second output unit that selectively outputs the signal to the first signal holding unit or the second signal holding unit based on a phase of the reference pulse generated by the reference pulse generation unit; Calculating means for calculating a difference between signals held by the first signal holding means and the second signal holding means as a phase difference between the reference pulse and the synchronization signal; and Signal smoothing means for smoothing and outputting a signal corresponding to the phase difference, wherein the oscillating means oscillates based on the signal corresponding to the phase difference output smoothed by the signal smoothing means. A phase-locked loop characterized by changing the following. 10. The phase synchronization circuit according to claim 9, wherein said synchronization signal output by said first output means is said video signal. 11. The phase synchronization circuit according to claim 9, wherein said synchronization signal output by said first output means is a difference between said video signal and said threshold value. 12. A comparison step of comparing a video signal including a composite synchronization signal and represented by a discrete numerical value with a predetermined threshold value, and based on a comparison result by the processing of the comparison step, the video signal is A first output step of outputting a synchronization signal when it is determined to be a synchronization section; an oscillation step of oscillating a signal of a predetermined frequency; and the frequency of the signal oscillated by the processing of the oscillation step, A first reference pulse generating step of generating a reference pulse by dividing by a natural number N; and a first step of adding and holding an input signal at a constant cycle.
And a second signal holding step of adding and holding the input signals at a constant cycle.
A signal holding step based on a phase of the reference pulse generated by the processing of the reference pulse generating step, based on a phase of the reference pulse generated by the processing of the reference pulse generating step. Or a second output step of selectively outputting, for holding by the processing of the second signal holding step, and holding by the processing of the first signal holding step. A calculating step of calculating a difference between the signal and the signal held by the processing of the second signal holding step as a phase difference between the reference pulse and the synchronization signal; and calculating the difference by the processing of the calculating step. And a signal smoothing step of smoothing and outputting a signal corresponding to the phase difference. A phase synchronization method comprising: changing the oscillating frequency based on a signal corresponding to the phase difference output after being smoothed by a process.