JP2002221943A - Liquid crystal display and image display application apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a horizontal stripe generated in the display part at the time the display mode of a screen-divided liquid crystal display panel is switched and to improve the display quality level. SOLUTION: The liquid crystal display consists of a liquid crystal display panel 5A provided with a source driver and a gate driver, an image display signal control circuit 11, a timing signal generating circuit 12A, a partial display control circuit 19 which controls the generation of a timing signal, a selection switching circuit 17 which sends a display mode signal to the partial display control circuit 19, and an opposite signal voltage generating circuit 18A. When the display part is driven at the time of display mode switching in two screen display, the image display signal control circuit and the timing signal generating circuit are controlled, and when the nondisplay part is driven, the operation start point of the opposite voltage control signal VCC is slightly delayed. In this way, horizontal stripe generation can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for displaying information used in a notebook type personal computer or a small information terminal and for displaying an image on a television monitor and the like, and an image display application device using the same. .

[0002]

2. Description of the Related Art In recent years, as information terminals such as personal computers and portable telephones and video display monitors, devices equipped with a liquid crystal display panel having a light, thin and small size are increasing. The driving of the liquid crystal display panel will be briefly described.

FIG. 6 shows a configuration diagram of this conventional active matrix type liquid crystal display panel. Each display pixel 1 of the liquid crystal display panel is formed by elements surrounded by a broken line composed of one thin film transistor (hereinafter abbreviated as TFT) 2, a liquid crystal display element 3 and a storage capacitor 4. A matrix-type liquid crystal display panel 5 is configured. The image signal electrode lines (S1 to Sm) 6 are electrode lines for supplying a voltage corresponding to the display data signal to the pixels, and the scanning signal electrode lines (X1 to Xn) 7 are selective scanning for performing line sequential scanning. This is an electrode line for supplying a signal. TF
T2 is a switching element controlled by a selection scanning signal from the scanning signal electrode line 7, the liquid crystal display element 3 is a display material having a pixel electrode, and the storage capacitor 4 reduces the image voltage charged in the liquid crystal display element 3. It is for suppressing. Further, a counter electrode 8 for supplying a reference voltage to the liquid crystal display element 3 with the liquid crystal layer of the display panel interposed therebetween is formed. The source driver 9 is a driver that supplies an image signal voltage to each image signal electrode line 6, and the gate driver 10 is a driver that supplies a selection scanning signal for performing line sequential scanning to each scanning signal electrode line 7. A timing control signal for performing timing control and an image display signal are input to the logic circuit of the source driver 9. Gate driver 1
Similarly, a timing control signal for performing timing control is input to the logic circuit 0.

The image signal electrode lines 6 and the scanning signal electrode lines 7 are arranged in a matrix. On the other hand, the source terminal of the TFT 2 is connected to the image signal electrode line 6, the gate terminal is connected to the scanning signal electrode line 7, and the drain terminal is connected to the pixel electrode of the liquid crystal display element 3 and one electrode of the storage capacitor 4. Storage capacity 4
The other electrode is commonly connected to the counter electrode 8. The opposing electrode 8 is supplied with an opposing signal voltage Vcom. The counter signal voltage Vcom uses a DC voltage or a voltage whose polarity is inverted every horizontal synchronization period (1H) depending on the type of driving method of the image signal voltage from the source driver 9.

In order to display an image, an image signal voltage corresponding to a display data signal is supplied from a source driver 9 to a source terminal (S) of each TFT 2 via each image signal electrode line 6. In synchronization with this, a selected scanning signal is supplied to the gate terminal (G) of each TFT 2 via the scanning signal electrode line 7 selected by the gate driver 10. This allows
The TFTs 2 on the selected scanning signal electrode line are simultaneously turned on, and the image signal voltage corresponding to the display data signal supplied from the drain terminal (D) and the counter signal voltage Vcom supplied to the counter electrode 8. The potential difference between the liquid crystal display element 3 and each storage capacitor 4 is the image display voltage of the final image information.
Is accumulated in This voltage is maintained for one field period during which the next information is written, even after the TFT 2 is turned off. The liquid crystal display element 3 changes the twist angle of liquid crystal molecules corresponding to the amount of accumulated voltage, thereby controlling the amount of transmission of light that has been given directionality by a polarizing plate, thereby providing a high-contrast, high-quality image. Can be displayed.

The liquid crystal display device includes a liquid crystal display panel and a driving circuit for driving the liquid crystal display panel, and this is shown in a block circuit of FIG. Here, a case will be described in which a two-screen mode display is divided into two in the vertical direction. In the figure, an image display signal control circuit 11 is a liquid crystal display panel 5
A timing signal generating circuit 12 for supplying a signal for controlling a drive timing to a logic circuit of the source driver 9 and a gate driver 10 of the liquid crystal display panel 5; The display signal source 13 is a signal source necessary for driving the liquid crystal display panel 5. Further, the liquid crystal display device includes a power supply 14 for supplying power to each unit, a voltage conversion circuit 15 for converting the power supply 14 to a required voltage level, and a power supply switch circuit 1 for controlling on / off of an output voltage supply from the voltage conversion circuit 15.
6, a switching circuit 17 for switching the display mode in the two-screen display control, and an opposing signal voltage generating circuit 18 for supplying an opposing signal voltage to the opposing signal electrode are provided.
The opposite signal voltage may be either a voltage that is inverted every horizontal synchronization period or a DC voltage. Here, it is assumed that the opposite signal voltage is inverted every horizontal synchronization period.

A signal from the liquid crystal display signal source 13 is supplied to an image display signal control circuit 11 and a timing signal generation circuit 12, and from each of them, an image signal voltage and a timing control signal necessary for the display operation of the liquid crystal display panel 5 are generated. Can be Various voltages required for display driving are supplied to the liquid crystal display panel 5 from a voltage conversion circuit 15, an image signal voltage is supplied from an image display signal control circuit 11 to a source driver 9, a timing signal generation circuit 12 is supplied with a source driver 9 and a gate driver 10. Is supplied with a timing control signal. Normally, the voltage conversion circuit 15 is driven by the ON control of the power switch circuit 16,
The display of the liquid crystal display panel 5 is performed by supplying a voltage to each control circuit and the liquid crystal display panel. The display operation on the liquid crystal display panel 5 is terminated by stopping the voltage conversion circuit 15 by turning off the power switch circuit 16 and stopping the voltage supply.

The two-screen display is a display method in which the liquid crystal display panel 5 is divided into a display section A and a display section B in the vertical scanning direction as shown in FIG. Taking mobile phone display as an example,
The display unit A is a partial display unit for displaying simple information such as character symbols and reception status display symbols, and the display unit B is a detailed information display as a main display or an image display unit such as a TV phone. As a display method, only the display section A is displayed when displaying general information in a standby state or the like, and the display section A is displayed when displaying general information.
And the display section B are displayed. The display mode changeover switch circuit 17 is a circuit for generating a control signal for switching the display state, and is either a partial display mode for the display section A alone or a full screen display mode for both the display sections A and B. This is for selecting a display mode. In particular, since low power consumption is emphasized in a portable device, it is preferable that the display unit B be in the non-display state in the partial display mode so that the driving power is reduced as much as possible. Therefore, for example, by stopping the gate selection scanning signal voltage supplied from the gate driver 10 and keeping the TFT 2 in the off state, the liquid crystal display element 3 is not charged with the image signal voltage, and the display unit B is reset. Make it invisible.

FIG. 9 is a timing chart of the display mode switching control. When the partial display mode change-over switch circuit 17 at time t ₁ in the figure, the display switching signal V
M becomes high (Hi), and the image display signal control circuit 11,
It is added to the timing signal generation circuit 12. The image display signal control circuit 11 changes the image display signal VS to only a partial display signal corresponding to the period of the display section A from the timing synchronized with the vertical synchronization signal VD. The timing signal generation circuit 12 sets the gate selection signal voltage from the gate driver 10 to low (Lo) except for the period during which partial display is performed by the gate selection stop signal GSC and changes the gate selection signal voltage normally supplied to the gate terminal of the TFT 2. I'm stopping. In the partial display mode, the supply of the gate selection signal voltage from the gate driver 10 to the display unit B is stopped, and the TFT 2 is always turned off to charge the liquid crystal display element 3 with the image signal voltage. In this case, the power consumption is reduced by hiding the display of the display unit B and stopping the line-sequential scanning drive during this period. Note that the image display signal V for the display section B
S is a regular signal VS1 for displaying information or displaying an image in the entire screen display period, but may be any signal VS2 not particularly limited in the non-display period in the partial display mode.

[0010]

In a case where a part of the control operation is stopped for the non-display period other than the partial display period and the low-power driving is performed, the display quality is reduced as shown in FIG. As shown in the figure, a phenomenon occurs in which uneven streaks occur when the display is switched from the full screen display to the partial display of only the display section A. There are two types of the stripes, one is a horizontal stripe L1 generated in the display unit A and seen as a luminance difference for each scanning electrode line, and the other is a vertical stripe L2 generated in the display unit B in which display is not performed. is there.

First, the horizontal streak is a write driving stop operation for performing the above-described non-display display portion B for lowering the power consumption. The display portion A in the partial display period is compared with the display portion B in the non-display period. It is thought that the AC driving balance of the liquid crystal display element 3 of the display unit A is broken and a luminance difference occurs between the lines due to a long time. The vertical streak changes in accordance with the image signal level of the last line in the display unit A, and tends to be darker in white display. Therefore, an image signal such as a gray scale signal or a lamp signal that changes from black to white or a black and white image signal is displayed. In the case of the display of the vertical stripe signal, the display portion B has a remarkable vertical stripe shape particularly under the white display portion. If the operation in this state continues for a long time, a vertical stripe-shaped pattern is burned. Since this phenomenon appears for a relatively long time of several tens to several hundreds of milliseconds from the time of switching the display mode, the image signal voltage written to the floating capacitance of the image signal electrode line 6 of the liquid crystal panel 5 is reduced. It is presumed that a leakage current flows into the liquid crystal element of the display section B, which is not displayed by being held in the accumulated state, and the potential accumulation occurs. This phenomenon does not occur in normal scanning driving because writing is performed every field (16.7 milliseconds at 60 Hz).

Here, the horizontal unevenness is caused by the fact that the display portion B of the non-display period continues for a long time with respect to the display portion A of the partial display period, so that the AC driving balance of the liquid crystal display element 3 of the display portion A is lost and the luminance between the lines is reduced. It is considered that a difference occurs. As a measure to solve this, it is necessary to suppress the influence of the voltage change on the liquid crystal display element 3 of the display unit A as much as possible when the display unit A enters the display unit B during the non-display period from the display unit A during the partial display period.

The present invention has been made in view of the above points, and has as its object to suppress uneven streaks that occur in an image display unit at the time of non-display, and in particular, to suppress horizontal streaks.

[0014]

According to a first aspect of the present invention, there is provided a matrix-like electrode comprising an image signal electrode and a scanning signal electrode, and a function of controlling an output current capability in response to an external signal. A source driver for supplying an image signal voltage to a signal electrode, a gate driver for supplying a scanning selection voltage to the scanning signal electrode, and an image provided in an area of each matrix electrode controlled by the image signal voltage and the scanning selection voltage A liquid crystal display panel including a display element group and a counter electrode commonly connected to one of the liquid crystal display elements; an image display signal control circuit for outputting an image signal to the liquid crystal display panel; and driving of the liquid crystal display panel A timing signal generating circuit for controlling a timing signal, and dividing a vertical synchronization period into a plurality of image display periods to display only a part of the screen of the liquid crystal display panel. A switching circuit for switching between a partial display mode to be displayed and a full-screen display mode for displaying a full screen; a counter signal voltage supplied to the liquid crystal display panel; and a DC voltage is output as a counter voltage based on an external control signal. A counter signal voltage generation circuit, and a partial display control circuit that controls the image display signal control circuit, the timing signal generation circuit, and the counter voltage generation circuit based on a display mode signal from the changeover switch circuit. A drive period of a non-display image display area among control signals from the timing signal generation circuit by the partial display control circuit that detects the display mode signal when the changeover switch circuit switches from the screen display mode to the partial display mode. To stop supplying the scan selection voltage from the gate driver,
The output current capability of the image signal voltage output from the source driver is suppressed, and the counter signal voltage is stopped in a part of the non-display image display area to supply only the DC voltage component.

According to a second aspect of the present invention, in the liquid crystal display device according to the first aspect, the timing signal generating circuit delays the counter signal voltage by a predetermined delay time from the start of driving of a non-display image display area. A DC voltage is output from the generating circuit.

According to a third aspect of the present invention, in the liquid crystal display device of the second aspect, the delay period is a horizontal synchronization period of H.
Is in the range of 1H to 10H.

According to a fourth aspect of the present invention, there is provided the liquid crystal display device according to any one of the first to third aspects.

The present invention provides such a liquid crystal display device.
When non-display of the image display unit B is performed in the display mode of only the image display unit A, it is possible to suppress the occurrence of the horizontal streak in the image display unit A.

[0019]

FIG. 1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention. In this embodiment, a partial display control circuit 19 for detecting the state of the changeover switch circuit 17 and controlling the image display signal control circuit 11 and the timing signal generation circuit 12A is provided. The timing signal generating circuit 12A generates a power save control signal PSC which becomes H level only in the non-display section based on the display switching control signal VMC. The liquid crystal display panel 5A has substantially the same configuration as that of the liquid crystal display panel described above, as shown in FIG. 2, but differs in the configuration of the source driver 9A. The source driver 9A has a current capability control function that can receive a power save signal and control the output current of the image signal voltage. A buffer circuit composed of an operational amplifier is provided on the output side of the source driver 9A, and is configured so that its output current can be cut off based on a control signal. The output current is controlled based on the power control signal PSC. The timing signal generation circuit 12A sets the power control signal PSC to the H level when switching from the partial display period to the non-display period of each field, and suppresses the output current from the source driver based on the power control signal.

FIG. 3 is a timing chart showing the main control signals. The detailed operation will be described below. The display mode is switched from the changeover switch circuit 17 for selecting the display mode to low (L
o) In the partial display mode of only the image display section A, the display switching signal VM which becomes high (Hi) is output. Here, it is assumed that switched to the partial display mode from the full-screen mode at time t ₁ by the change-over switch circuit 17. When receiving the high (Hi) signal of the display switching signal VM from the changeover switch circuit 17, the partial display control circuit 19 switches to the state shown in FIG.
From the time t ₂ of the timing synchronized with one field (1F) period of the vertical synchronizing signal VD as shown in, and sends a display switching control signal VMC to the image display signal control circuit 11 and a timing signal generating circuit 12A. When the image display signal control circuit 11 receives the display switching control signal VMC, the image display signal of the display section B during the non-display period of t _{3 to} t ₄ , t _{5 to} t _6. It has a function of switching VS2 to a specific signal. This signal VS2 may be any signal that is not particularly limited. Display period t ₂ ~t _3, t
₄ outputs a display signal to be displayed on ~t ₅ · · · In the image display unit A. On the other hand, when the timing signal generation circuit 12A receives the display switching control signal VMC, the source driver 9A
Power save control signal PSC to change output current capability of
And a gate selection stop signal GSC of the gate driver 10A.
Is output. The power save control signal PSC changes from time t ₃ to
and high (Hi) to the non-display period of _{t 4, t 5 ~t 6 ···} , the source driver 9 in response to which the high-impedance state as much as possible eliminate the output current capability. The gate selection stop signal GSC is also set to high (Hi) during the non-display period, and the supply of the gate selection signal voltage from the gate driver 10 is stopped, so that the TFT 2 is always turned off and the image signal voltage to the liquid crystal display element 3 is changed. Not to charge the battery.

By performing such a control operation, the liquid crystal panel 5A in the non-display period is output by the output of the source driver 9A.
Image signal electrode line 6 is in a high impedance state.
Accordingly, the image signal voltage is not supplied, and the energy of the stored charge written in the floating capacitance of the image signal electrode line 6 becomes extremely small. Therefore, almost no leak current occurs in the liquid crystal element of the display section B. Therefore, it is possible to suppress the occurrence of vertical stripes in the non-display portion.

Next, a potential for suppressing horizontal streaks is supplied.
Measures will be described. Low power consumption in partial display mode
Drive in the display section B during the non-display period to perform
Power save system mainly involving the source driver 9A
Control signal PSC, gate selection related to gate driver 10
Selection stop signal GSC and involved in counter voltage generation circuit 18
Of the counter voltage control signals VCC.
In this embodiment, as shown in FIG.
Delay operation start point for control signal VCC
I have. FIG. 4 shows an image immediately after the start on the display unit B during the non-display period.
The main control signal of the signal electrode line is enlarged and displayed on the time axis.
It is an imaging chart. In this embodiment, the partial table
From the display part A to the non-display part during the partial display period in the display mode
At the time of switching to the display section B of the counter voltage control signal VCC
Is controlled to delay. Figure 4 shows the partial display mode
From the partial display period (display part A) to the non-display period when entering
Time t near the boundary of (display unit B)₇ ~ T₉ Main control signal
Signal in the cycle (1H) of the horizontal synchronization signal HD
This shows a fine timing state. In FIG. 4, the time
t₇ Indicates the partial display state, and the time t₈ In the hidden part
It switches to motion. Time t ₉ Is the time of the non-display state. So
Counter voltage output from the counter signal voltage generation circuit 18A
Drives voltage control signal VCC to delay operation start point
Time t delayed by period α₁₁From a constant DC voltage
I have.

In the conventional driving method, the gate selection stop signal GSC
Is active, the counter voltage becomes a center bias DC voltage from the beginning of the non-display period in which the supply of the counter voltage, which is inverted every horizontal period, is stopped, and is supplied from the source driver 9 to the pixel signal electrode 6. The image signal voltage is not supplied due to high impedance. Since these are simultaneously applied to both ends of the liquid crystal display element 3, the change in potential immediately after the start of the non-display period becomes a very unstable state. Therefore, control is performed to delay the operation start point for the counter voltage control signal VCC. As a result, in the first period t _{8 to} t ₁₁ of the non-display periods t _{8 to} t ₁₀ , the counter voltage is still supplied as an alternating current, which acts to reduce the potential change to the liquid crystal display element 3. Is considered to be eliminated. Note that the delay time α is effective if it is at least three horizontal synchronization periods (3H) or more. Therefore, it is desirable to minimize the delay time in consideration of power reduction. Therefore, α ≒ 3H to 10H is preferable in terms of margin. .

In this embodiment, the delay period α is set immediately after the start of the non-display period. However, the present invention is not limited to this. T ₈ the non-display period, as shown in FIG. 5, for example ~t
_If it is set to 10, the stop period may be set in the middle of the non-display period, and the AC drive may be performed only during this period. Further, as shown at the bottom of FIG. 5, for example, the period for performing the AC drive of the voltage may be divided into a plurality of periods, and the AC drive may be performed a plurality of times, for example, by 1H.

A variety of image display application devices having a plurality of display areas, such as a mobile phone, using the above-described liquid crystal display device and displaying only a partial display area at all times and displaying the entire screen as needed. Can be realized.

[0026]

According to the liquid crystal driving device of the present invention, the horizontal streak generated in the partial display portion when the display mode is switched by dividing the screen is temporarily released from the stop of the opposing voltage during the non-display period. This can be suppressed. Therefore, both improvement of display quality and reduction of power consumption of the liquid crystal panel can be achieved, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a display panel of this embodiment.

FIG. 3 is a timing chart of the liquid crystal display device according to the present embodiment.

FIG. 4 is an enlarged view of a timing chart in a time axis direction.

FIG. 5 is an enlarged view in a time axis direction of a timing chart showing a modification of the embodiment of the present invention.

FIG. 6 is a configuration diagram of a general active type liquid crystal display panel using an amorphous TFT.

FIG. 7 is an example of a block circuit diagram in a conventional active-type liquid crystal display panel driving device.

FIG. 8 is an example of a configuration diagram of a two-screen split display of a liquid crystal display panel.

9 is a timing chart of main control signals in the divided display of the liquid crystal display device of FIG. 6;

FIG. 10 is an explanatory diagram illustrating vertical streak generation in a non-display portion when partial display is performed in a two-screen split display of a liquid crystal display panel.

[Explanation of symbols]

 5, 5A Liquid crystal display panel 9, 9A Source driver 10 Gate driver 11 Image display signal control circuit 12, 12A Timing signal generation circuit 17 Changeover switch circuit 18, 18A Counter signal voltage generation circuit 19 Partial display control circuit

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Dai Fukuda 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F term (reference) 2H093 NA16 NA45 ND10 ND60 5C006 AA16 AC24 AF42 BB16 FA05 FA22 5C080 AA10 BB05 DD05 EE26 FF11 JJ01 JJ02 JJ03 JJ04

Claims (4)

[Claims] A source driver for supplying an image signal voltage to said image signal electrode, said electrode driver having a matrix-shaped electrode comprising an image signal electrode and a scanning signal electrode, and having an output current capability control function in response to an external signal; A gate driver for supplying a scan selection voltage to a scan signal electrode, a common image display element group provided in a region of each matrix electrode controlled by the image signal voltage and the scan selection voltage, and one of the liquid crystal display elements A liquid crystal display panel including a connected counter electrode; an image display signal control circuit for outputting an image signal to the liquid crystal display panel; a timing signal generation circuit for controlling a drive timing signal of the liquid crystal display panel; A partial display mode in which a period is divided into a plurality of image display periods and only a part of the screen of the liquid crystal display panel is displayed, and a full screen is displayed A changeover switch circuit for switching between a full-screen display mode, an opposing signal voltage generating circuit for supplying an opposing signal voltage to the liquid crystal display panel, and outputting a DC voltage as an opposing voltage based on an external control signal; A partial display control circuit that controls the image display signal control circuit, the timing signal generation circuit, and the counter voltage generation circuit based on a display mode signal from a circuit, and switches from the full screen display mode to the partial display mode. A scan selection voltage from the gate driver for a drive period of a non-display image display area among control signals from the timing signal generation circuit by the partial display control circuit that has detected the display mode signal when the changeover switch circuit is switched. Supply of the image signal to suppress the output current capability of the image signal voltage output from the source driver. The liquid crystal display device and supplying only a DC voltage component stops the counter signal voltage portion of the non-display image display area of the. 2. The method according to claim 1, wherein the timing signal generation circuit outputs a DC voltage from the counter signal voltage generation circuit with a delay of a predetermined delay time from the start of driving of a non-display image display area. The liquid crystal display device according to claim 1. 3. The delay period according to claim 2, wherein the horizontal synchronization period is H, and the delay period is 1H to 10H.
The liquid crystal display device as described in the above. 4. An image display application device using the liquid crystal display device according to claim 1.