JP2002221942A - Liquid crystal display and image display application apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a vertical stripe generated in the nondisplay part at the time the display mode of a screen-divided liquid crystal display panel is switched and to improve the display quality level. SOLUTION: The liquid crystal display consists of a liquid crystal display panel 5A provided with a source driver and a gate driver, an image display signal control circuit 11, a timing signal generating circuit 12A; a vertical stripe suppression circuit 19 which controls the image display signal control circuit 11 and timing signal generating circuit 12A, and a selection switching circuit 17 which sends a display mode signal to the vertical stripe suppression circuit. For the period in which the nondisplay part of the image display part is driven at display mode switching in two screen display, the vertical stripe suppression circuit controls the image display signal control circuit and the timing signal generating circuit, suppresses the current output capacity of the source driver, and always suspends supply of the scanning selection voltage from the gate driver. In this way, vertical stripe generation can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for displaying information used in a notebook type personal computer or a small information terminal and for displaying an image on a television monitor and the like, and an image display application device using the same. .

[0002]

2. Description of the Related Art In recent years, as information terminals such as personal computers and portable telephones and video display monitors, devices equipped with a liquid crystal display panel having a light, thin and small size are increasing. The driving of the liquid crystal display panel will be briefly described.

FIG. 6 shows a configuration diagram of this conventional active matrix type liquid crystal display panel. Each display pixel 1 of the liquid crystal display panel is formed by being surrounded by a dashed line composed of one thin film transistor (hereinafter abbreviated as TFT) 2, a liquid crystal display element 3, and a storage capacitor 4.
Thus, an active matrix type liquid crystal display panel 5 is constituted. The image signal electrode lines (S1 to Sm) 6 are electrode lines for supplying a voltage corresponding to the display data signal to the pixels, and the scanning signal electrode lines (X1 to Xn) 7 are selective scanning for performing line sequential scanning. This is an electrode line for supplying a signal. The TFT 2 is a switching element controlled by a selection scanning signal from the scanning signal electrode line 7, the liquid crystal display element 3 is a display material having a pixel electrode, and the storage capacitor 4 reduces the image voltage charged in the liquid crystal display element 3. It is for suppressing. Further, a counter electrode 8 for supplying a reference voltage to the liquid crystal display element 3 with the liquid crystal layer of the display panel interposed therebetween is formed. The source driver 9 is a driver that supplies an image signal voltage to each image signal electrode line 6, and the gate driver 10 is a driver that supplies each scanning signal electrode line 7.
Is a driver that supplies a selection scanning signal for performing line-sequential scanning. A timing control signal for performing timing control and an image display signal are input to the logic circuit of the source driver 9. Similarly, a timing control signal for performing timing control is input to the logic circuit of the gate driver 10.

The image signal electrode lines 6 and the scanning signal electrode lines 7 are arranged in a matrix. On the other hand, the source terminal of the TFT 2 is connected to the image signal electrode line 6, the gate terminal is connected to the scanning signal electrode line 7, and the drain terminal is connected to the pixel electrode of the liquid crystal display element 3 and one electrode of the storage capacitor 4. Storage capacity 4
The other electrode is commonly connected to the counter electrode 8. The opposing electrode 8 is supplied with an opposing signal voltage Vcom. The counter signal voltage Vcom uses a DC voltage or a voltage whose polarity is inverted every horizontal synchronization period (1H) depending on the type of driving method of the image signal voltage from the source driver 9.

In order to display an image, an image signal voltage corresponding to a display data signal is supplied from a source driver 9 to a source terminal (S) of each TFT 2 via each image signal electrode line 6. In synchronization with this, a selected scanning signal is supplied to the gate terminal (G) of each TFT 2 via the scanning signal electrode line 7 selected by the gate driver 10. This allows
The TFTs 2 on the selected scanning signal electrode line are simultaneously turned on, and the image signal voltage corresponding to the display data signal supplied from the drain terminal (D) and the counter signal voltage Vcom supplied to the counter electrode 8. The potential difference between the liquid crystal display element 3 and each storage capacitor 4 is the image display voltage of the final image information.
Is accumulated in This voltage is maintained for one field period during which the next information is written, even after the TFT 2 is turned off. The liquid crystal display element 3 changes the twist angle of liquid crystal molecules corresponding to the amount of accumulated voltage, thereby controlling the amount of transmission of light that has been given directionality by a polarizing plate, thereby providing a high-contrast, high-quality image. Can be displayed.

The liquid crystal display device includes a liquid crystal display panel and a driving circuit for driving the liquid crystal display panel, and this is shown in a block circuit of FIG. Here, a case will be described in which a two-screen mode display is divided into two in the vertical direction. In the figure, an image display signal control circuit 11 is a liquid crystal display panel 5
A timing signal generating circuit 12 for supplying a signal for controlling a drive timing to a logic circuit of the source driver 9 and a gate driver 10 of the liquid crystal display panel 5; The display signal source 13 is a signal source necessary for driving the liquid crystal display panel 5. Further, the liquid crystal display device includes a power supply 14 for supplying power to each unit, a voltage conversion circuit 15 for converting the power supply 14 to a required voltage level, and a power supply switch circuit 1 for controlling on / off of an output voltage supply from the voltage conversion circuit 15.
6, a switching circuit 17 for switching the display mode in the two-screen display control, and an opposing signal voltage generating circuit 18 for supplying an opposing signal voltage to the opposing signal electrode are provided.
The opposite signal voltage may be either a voltage that is inverted every horizontal synchronization period or a DC voltage. Here, it is assumed that the opposite signal voltage is inverted every horizontal synchronization period.

A signal from the liquid crystal display signal source 13 is supplied to an image display signal control circuit 11 and a timing signal generation circuit 12, and from each of them, an image signal voltage and a timing control signal necessary for the display operation of the liquid crystal display panel 5 are generated. Can be Various voltages required for display driving are supplied to the liquid crystal display panel 5 from a voltage conversion circuit 15, an image signal voltage is supplied from an image display signal control circuit 11 to a source driver 9, a timing signal generation circuit 12 is supplied with a source driver 9 and a gate driver 10. Is supplied with a timing control signal. Normally, the voltage conversion circuit 15 is driven by the ON control of the power switch circuit 16,
The display of the liquid crystal display panel 5 is performed by supplying a voltage to each control circuit and the liquid crystal display panel. The display operation on the liquid crystal display panel 5 is terminated by stopping the voltage conversion circuit 15 by turning off the power switch circuit 16 and stopping the voltage supply.

The two-screen display is a display method in which the liquid crystal display panel 5 is divided into a display section A and a display section B in the vertical scanning direction as shown in FIG. Taking mobile phone display as an example,
The display unit A is a partial display unit for displaying simple information such as character symbols and reception status display symbols, and the display unit B is a detailed information display as a main display or an image display unit such as a TV phone. As a display method, only the display section A is displayed when displaying general information in a standby state or the like, and the display section A is displayed when displaying general information.
And the display section B are displayed. The display mode changeover switch circuit 17 is a circuit for generating a control signal for switching the display state, and is either a partial display mode for the display section A alone or a full screen display mode for both the display sections A and B. This is for selecting a display mode. In particular, since low power consumption is emphasized in a portable device, it is preferable that the display unit B be in the non-display state in the partial display mode so that the driving power is reduced as much as possible. Therefore, for example, by stopping the gate selection scanning signal voltage supplied from the gate driver 10 and keeping the TFT 2 in the off state, the liquid crystal display element 3 is not charged with the image signal voltage, and the display unit B is reset. Make it invisible.

FIG. 9 is a timing chart of the display mode switching control. When the partial display mode change-over switch circuit 17 at time t ₁ in the figure, the display switching signal V
M becomes high (Hi), and the image display signal control circuit 11,
It is added to the timing signal generation circuit 12. The image display signal control circuit 11 changes the image display signal VS to only a partial display signal corresponding to the period of the display section A from the timing synchronized with the vertical synchronization signal VD. The timing signal generation circuit 12 sets the gate selection signal voltage from the gate driver 10 to low (Lo) except for the period during which partial display is performed by the gate selection stop signal GSC and changes the gate selection signal voltage normally supplied to the gate terminal of the TFT 2. I'm stopping. In the partial display mode, the supply of the gate selection signal voltage from the gate driver 10 to the display unit B is stopped, and the TFT 2 is always turned off to charge the liquid crystal display element 3 with the image signal voltage. In this case, the power consumption is reduced by hiding the display of the display unit B and stopping the line-sequential scanning drive during this period. Note that the image display signal V for the display section B
S is a regular signal VS1 for displaying information or displaying an image in the entire screen display period, but may be any signal VS2 not particularly limited in the non-display period in the partial display mode.

[0010]

In driving such a liquid crystal display panel, the display section A is switched from the full screen display mode.
When the display mode is switched to the partial display mode, only the vertical streak occurs in the non-displayed display section B as shown in FIG. This vertical streak changes in accordance with the image signal level of the last line in the display unit A, and tends to be darker in white display. Therefore, an image signal such as a gray scale signal or a lamp signal which changes from black to white or a black and white image signal is displayed. In the case of displaying a vertical stripe signal, the display portion B is particularly below the white display portion.
And noticeable vertical stripes. If the operation in this state continues for a long time, a vertical stripe-shaped pattern is burned. This phenomenon appears over a relatively long time of several tens to several hundreds of milliseconds from the time of switching the display mode. From this, the image signal voltage written in the stray capacitance of the image signal electrode line 6 of the liquid crystal panel 5 is held in an accumulated state, so that the liquid crystal element of the display portion B which is not displayed is maintained. It is presumed that the leakage current flows and the potential accumulation occurs. In the normal scanning drive, one field (6
This phenomenon does not occur because data is written every 16.7 ms in the case of 0 Hz.

SUMMARY OF THE INVENTION In view of the above, the present invention provides a liquid crystal display device capable of suppressing vertical streaks occurring in an image display section when non-display is performed, and an image display application device using the same. .

[0012]

According to a first aspect of the present invention, there is provided a matrix-like electrode comprising an image signal electrode and a scanning signal electrode, and a function of controlling an output current capability in response to an external signal. A source driver for supplying an image signal voltage to a signal electrode, a gate driver for supplying a scanning selection voltage to the scanning signal electrode, and an image provided in an area of each matrix electrode controlled by the image signal voltage and the scanning selection voltage A liquid crystal display panel including a display element group and a counter electrode commonly connected to one of the liquid crystal display elements; an image display signal control circuit for outputting an image signal to the liquid crystal display panel; and driving of the liquid crystal display panel A timing signal generating circuit for controlling a timing signal, and dividing a vertical synchronization period into a plurality of image display periods to display only a part of the screen of the liquid crystal display panel. Switch circuit for switching between a partial display mode to be displayed and a full screen display mode for displaying a full screen, and a vertical stripe for controlling the image display signal control circuit and the timing signal generation circuit based on a display mode signal from the switch circuit. A suppression control circuit, comprising: a vertical streak suppression control circuit that detects the display mode signal when the changeover switch circuit switches from a full screen display mode to a partial display mode; Wherein the supply of the scanning selection voltage from the gate driver is stopped during the driving period of the non-display image display area, and the output current capability of the image signal voltage output from the source driver is suppressed. And

According to a second aspect of the present invention, there is provided a matrix-like electrode comprising an image signal electrode and a scanning signal electrode, an output current capability control function according to an external signal, and an image signal voltage applied to the image signal electrode. A source driver, a gate driver for supplying a scanning selection voltage to the scanning signal electrode, an image display element group provided in a region of each matrix electrode controlled by the image signal voltage and the scanning selection voltage, and A liquid crystal display panel including a common electrode commonly connected to one of the liquid crystal display elements; an image display signal control circuit for outputting an image signal to the liquid crystal display panel; and a timing for controlling a drive timing signal of the liquid crystal display panel A signal generation circuit, and a partial display mode for dividing the vertical synchronization period into a plurality of image display periods and displaying only a part of the screen of the liquid crystal display panel. And a changeover switch circuit for switching between a full-screen display mode and a full-screen display mode for displaying a full-screen. A full-screen display, comprising: a generation circuit; and a vertical streak suppression control circuit that controls the image display signal control circuit, the timing signal generation circuit, and the counter voltage generation circuit based on a display mode signal from the changeover switch circuit. During the drive period of the non-display image display area, of the control signals from the timing signal generation circuit by the vertical streak suppression control circuit that has detected the display mode signal when the changeover switch circuit switches from the mode to the partial display mode, On the other hand, the supply of the scanning selection voltage from the gate driver is stopped, and the image signal voltage output from the source driver is stopped. While suppressing the current capability, the counter signal voltage is stopped and only the DC voltage component is supplied, and the image display signal control circuit controls the image signal voltage supplied to the source driver during the driving period of the non-display image area. A binary signal level inverted every one horizontal synchronization period or one vertical synchronization period or a DC voltage level equal to or lower than a threshold voltage of the liquid crystal display element.

The invention of claim 3 of the present application is directed to claim 1 or 2
A liquid crystal display device according to any one of the preceding claims is used.

According to the present invention, it is possible to suppress the occurrence of vertical streaks in the non-image display section in the partial display mode of only the image display section A by the driving device described above.

[0016]

FIG. 1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention. In this embodiment, a vertical streak suppression control circuit 19 that detects the state of the changeover switch circuit 17 and controls the image display signal control circuit 11 and the timing signal generation circuit 12A is provided. The timing signal generating circuit 12A outputs a power save control signal PSC which becomes H level only in the non-display section based on the display switching control signal VMC.
Is to occur. The liquid crystal display panel 5A has substantially the same configuration as that of the liquid crystal display panel described above, as shown in FIG. 2, but differs in the configuration of the source driver 9A. The source driver 9A has a current capability control function that can receive a power save signal and control the output current of the image signal voltage. A buffer circuit composed of an operational amplifier is provided on the output side of the source driver 9A, and is configured so that its output current can be cut off based on a control signal. The output current is controlled based on the power control signal PSC.

FIG. 3 is a timing chart showing the main control signals. The detailed operation will be described below. The display mode is switched from the changeover switch circuit 17 for selecting the display mode to low (L
o) In the partial display mode of only the image display section A, the display switching signal VM which becomes high (Hi) is output. Here, it is assumed that switched to the partial display mode from the full-screen mode at time t ₁ by the change-over switch circuit 17. When receiving the high (Hi) signal of the display switching signal VM from the changeover switch circuit 17, the vertical streak suppression control circuit 19, as shown in FIG. ₂ sends a display switching control signal VMC to the image display signal control circuit 11 and the timing signal generation circuit 12A. When the image display signal control circuit 11 receives the display switching control signal VMC, the image display signal of the display section B during the non-display period of t _{3 to} t ₄ , t _{5 to} t _6. It has a function of switching VS2 to a specific signal. This signal VS2 may be any signal that is not particularly limited. Display period t ₂ ~t _3,
From t _{4 to} t ₅ , a display signal to be displayed on the image display unit A is output. On the other hand, when the timing signal generation circuit 12A receives the display switching control signal VMC, the source driver 9
A power save control signal PSC that changes the output current capability of A
And a gate selection stop signal GSC of the gate driver 10A.
Is output. The power save control signal PSC changes from time t ₃ to
High (Hi) during the non-display period of t ₄ , t _{5 to} t ₆ ..., and in response to this, the source driver 9 minimizes the output current capability and enters the high impedance state. Similarly, the gate selection stop signal GSC is also set to high (Hi) during the non-display period, and the supply of the gate selection signal voltage from the gate driver 10 is stopped, so that the TFT 2 is always turned off and the image to the liquid crystal display element 3 is displayed. Avoid charging the signal voltage.

By performing such a control operation, the image signal electrode line 6 of the liquid crystal panel 5 in the non-display period is brought into a high impedance state by the output of the source driver 9A. Therefore, the image signal voltage is not supplied and the image signal electrode line 6 is not supplied.
Since the energy of the stored charge written in the floating capacitance becomes extremely small, a leak current hardly occurs in the liquid crystal element of the display section B. Therefore, it is possible to suppress the occurrence of vertical stripes in the non-display portion. The opposing signal voltage Vcom may be an opposing inversion drive in which the opposing signal voltage is inverted every horizontal synchronization period as shown in the figure, or an opposing constant drive that is driven by a constant DC voltage is also effective. In this case, the image display signal VS2 of the display unit B during the non-display period may be any signal that is not particularly limited. Further, by making the output of the source driver 9A high impedance by the power save control during the non-display period, there is also an advantage that the power consumption of the source driver system can be significantly reduced.

Next, a second embodiment of the present invention will be described. In the opposing inversion drive in which the opposing signal voltage is inverted every horizontal synchronization period, if the opposing signal voltage is also driven during the non-display period, the opposing electrode 8 of the liquid crystal panel 5 and the image signal electrode line 6
And the capacitance between the scanning signal electrode lines 7 is charged / discharged, resulting in power loss. This embodiment is intended to further reduce the power consumption when performing the opposing inversion drive, and FIG. 4 shows a block diagram thereof. In the present embodiment, the opposing voltage control signal VCC is supplied from the timing signal generating circuit 12B to the opposing signal voltage generating circuit 18A.
Is output. The counter voltage control signal VCC is low (Lo) during the display period, and the voltage control signal VCC is high (H).
i). The counter voltage generation circuit 18A outputs the control signal V
In the non-display period of the partial display mode, the counter signal voltage Vcom is fixed to a DC voltage by stopping the voltage amplitude based on the CC. In this example, the center bias voltage of the opposite signal voltage is used.

However, it has been found that when the power save control signal PSC is set to high (Hi) in this state, the vertical streak cannot be sufficiently suppressed particularly when the image display signal of the display section B in the non-display period is at a halftone level. . As a condition of the image display signal VS3 of the display unit B in the non-display period in which the vertical streak does not occur, a binary signal level inverted every one horizontal synchronization period or one vertical synchronization period or a DC voltage lower than the threshold voltage of the liquid crystal display element. The voltage level has been found to be effective. Therefore, the image display signal control circuit 11A outputs such an image display signal V3 during the non-display period.

By selecting the image display signal VS3 in this way, vertical streak suppression can be realized even if the counter signal voltage Vcom is changed to a DC voltage in the non-display period. Note that the DC voltage level when the voltage amplitude of the opposing signal voltage is stopped is optimal near the center bias voltage level of the opposing signal voltage amplitude in terms of overall display quality and long-term reliability.

A variety of image display application devices having a plurality of display areas, such as a mobile phone, using the above-described liquid crystal display device and displaying only a partial display area at all times and displaying the entire screen as needed. Can be realized.

[0023]

According to the liquid crystal display device of the present invention, the vertical streak generated in the non-display portion when the display mode is switched by dividing the screen is controlled by the output current capability of the source driver and the gate selection voltage of the gate driver. Can be suppressed by stopping. In addition, an excellent effect that the power consumption of the liquid crystal panel can be greatly reduced by controlling the output current capability of the source driver can be obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a display panel according to the first embodiment.

FIG. 3 is a timing chart of the liquid crystal display device according to the first embodiment.

FIG. 4 is a block diagram of a liquid crystal display device according to a second embodiment.

FIG. 5 is a timing chart of the liquid crystal display device according to the second embodiment.

FIG. 6 is a configuration diagram of a general active type liquid crystal display panel using an amorphous TFT.

FIG. 7 is an example of a block circuit diagram in a conventional active-type liquid crystal display panel driving device.

FIG. 8 is an example of a configuration diagram of a two-screen split display of a liquid crystal display panel.

9 is a timing chart of main control signals in the divided display of the liquid crystal display device of FIG. 6;

FIG. 10 is an explanatory diagram illustrating vertical streak generation in a non-display portion when partial display is performed in a two-screen split display of a liquid crystal display panel.

[Explanation of symbols]

 5, 5A Liquid crystal display panel 9, 9A Source driver 10 Gate driver 11, 11A Image display signal control circuit 12, 12A, 12B Timing signal generation circuit 17 Changeover switch circuit 18, 18A Counter signal voltage generation circuit 19 Vertical streak suppression control circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G09G 3/20 622 G09G 3/20 622Q 660 660Q 680 680S (72) Inventor Fukuda Dai Okadoma, Kadoma, Osaka 1006 Matsushita Electric Industrial Co., Ltd.F-term (reference)

Claims (3)

[Claims] A source driver for supplying an image signal voltage to said image signal electrode, said electrode driver having a matrix-shaped electrode comprising an image signal electrode and a scanning signal electrode, and having an output current capability control function in response to an external signal; A gate driver for supplying a scan selection voltage to a scan signal electrode, a common image display element group provided in a region of each matrix electrode controlled by the image signal voltage and the scan selection voltage, and one of the liquid crystal display elements A liquid crystal display panel including a connected counter electrode; an image display signal control circuit for outputting an image signal to the liquid crystal display panel; a timing signal generation circuit for controlling a drive timing signal of the liquid crystal display panel; A partial display mode in which a period is divided into a plurality of image display periods and only a part of the screen of the liquid crystal display panel is displayed, and a full screen is displayed A changeover switch circuit for switching between a full screen display mode and a vertical streak suppression control circuit for controlling the image display signal control circuit and the timing signal generation circuit based on a display mode signal from the changeover switch circuit; When the changeover switch circuit is switched from the screen display mode to the partial display mode, the vertical streak suppression control circuit that detects the display mode signal drives the non-display image display area in the control signals from the timing signal generation circuit. A liquid crystal display device, wherein the supply of the scan selection voltage from the gate driver is stopped during a period, and the output current capability of the image signal voltage output from the source driver is suppressed. 2. A source driver which has a matrix-like electrode composed of an image signal electrode and a scanning signal electrode, has an output current capability control function according to an external signal, and supplies an image signal voltage to the image signal electrode. A gate driver for supplying a scan selection voltage to a scan signal electrode, a common image display element group provided in a region of each matrix electrode controlled by the image signal voltage and the scan selection voltage, and one of the liquid crystal display elements A liquid crystal display panel including a connected counter electrode; an image display signal control circuit for outputting an image signal to the liquid crystal display panel; a timing signal generation circuit for controlling a drive timing signal of the liquid crystal display panel; A partial display mode in which a period is divided into a plurality of image display periods and only a part of the screen of the liquid crystal display panel is displayed, and a full screen is displayed A changeover switch circuit for switching between a full screen display mode, an opposing signal voltage generating circuit for supplying an opposing signal voltage to the liquid crystal display panel, and outputting a DC voltage as an opposing voltage based on an external control signal; A vertical streak suppression control circuit for controlling the image display signal control circuit, the timing signal generation circuit, and the counter voltage generation circuit based on a display mode signal from a circuit; When the changeover switch circuit is switched from the display mode to the partial display mode, the supply of the scan selection voltage from the gate driver is stopped during the drive period of the non-display image display area among the control signals from the timing signal generation circuit. In addition, the output current capability of the image signal voltage output from the source driver is suppressed, and the counter signal voltage is stopped. The image display signal control circuit supplies the image signal voltage supplied to the source driver to the non-display image area driving period for each horizontal synchronization period or for one vertical synchronization period. A liquid crystal display device characterized in that a binary signal level inverted every time or a DC voltage level equal to or lower than a threshold voltage of the liquid crystal display element is used. 3. An image display application device using the liquid crystal display device according to claim 1.