JP2002218410A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device capable of converting input image signals of a plurality of formats into a single format that is practically the most excellent and displaying the input image signals of the single format. SOLUTION: An I-P converting part 1 converts 480i and 1080i signals into 480p and 1080p signals. An enlarging and reducing part 2 converts 480p, 720p and 1080p signals into a 1440p signal. A P-I converting part 3 converts the 1440p signal into a 1440i signal. Thus, all of the signals are unified into 1440i single format whose horizontal frequency is 45 kHz.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video display device suitable for displaying video signals of a plurality of formats.

[0002]

2. Description of the Related Art In recent years, in a video display device such as a television receiver, it has become necessary to display video signals in a plurality of formats with the start of digital broadcasting. As the format of the video signal, the total number of scanning lines is 52
5 interlaces (480 effective scanning lines)
i), an interlace (1080i) having a total number of scanning lines of 1,125 and an effective scanning number of 1080, and a total number of scanning lines of 525
480 effective scanning lines progressive (480
p), progressive (720p) with 750 total scanning lines and 720 effective scanning lines.

In these formats, the vertical frequency is the same, but the number of effective scanning lines per field is 480/2 for 480i and 10 for 1080i.
80/2 lines, 480 lines at 480p, 72 lines at 720p
It is different from zero. On the other hand, the horizontal frequency is
15.75 kHz for 480i, 33.80 for 1080i.
75 kHz and 480p are 31.5 kHz, and 720p are 45 kHz, which are different from each other.

When an image display device attempts to display all of these plural formats of image signals, the horizontal scanning frequency of the image display device is set to 15.75 kHz, 3
Switching at 3.75 kHz, 31.5 kHz, and 45 kHz can be considered. In this case, the video display device is 4
Type of horizontal scanning frequency. 4
If an 80i video signal is converted into a 480p video signal by interlace-progressive (IP) conversion,
What is necessary is just to correspond to three types of horizontal scanning frequencies. Even so, it is necessary to correspond to three types of horizontal scanning frequencies.
The format to be displayed on the video display device is 1080
The use of i is also being considered.

[0005]

As described above, in order to support a plurality of formats of video signals in a video display device, for example, in the case of a display device using a cathode ray tube (CRT), a CRT of each format is used for each format. It is necessary to change the synchronization, and a large voltage fluctuation occurs in the deflection circuit, and a large load is applied to the deflection circuit. Even in a display device that does not use a CRT, supporting a plurality of formats of video signals imposes a heavy burden on the drive circuit.

Further, since synchronization must be re-established every time the format is switched, it is necessary to temporarily mask (blanking) the display of video on the screen due to quality problems. Therefore, the control operation of the video display device becomes complicated, and a problem that a video is not displayed temporarily is caused. As described above, in the video display device, supporting various formats of video signals causes various problems.

Therefore, in order to solve these problems,
The format displayed on the video display device may be unified to 1080i. However, if the format is 1080
When unified to i, there are the following problems. When 480i is converted to 1080i, the number of scanning lines becomes 9/4 times,
When 720p is converted to 1080i, the number of scanning lines becomes 3/4.
Double. Therefore, if the format is unified to 1080i, the format conversion process involves both the enlargement and reduction of the number of scanning lines, and the hardware scale of the interpolation filter constituting the format conversion processing circuit increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an image display device capable of converting input image signals in a plurality of formats into a single format which is most practical and displaying the same. The purpose is to provide. It is another object of the present invention to provide an image display device capable of displaying an extremely high-quality image while minimizing an increase in hardware scale and complexity of signal processing.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art by using a horizontal frequency of 15.75 k.
And a second video signal which is an interlace signal having a horizontal frequency of 33.75 kHz. In a video display device using the first and second video signals as input video signals, the first and second video signals are Horizontal frequency 45
a video signal processing unit (1 to 3) for processing so as to convert to a third video signal which is an interlace signal of kHz, a cathode ray tube display unit (9) for displaying the third video signal, and the third A deflection circuit (8) for horizontally and vertically deflecting the electron beam of the cathode ray tube display unit to display a video signal on the cathode ray tube display unit, and a predetermined lock range; A PLL circuit (7) for supplying a synchronization signal, wherein the PLL circuit has a frequency of 45 kHz.
In the lock range, and supplying a horizontal synchronization signal having a frequency included in the lock range to the deflection circuit as the single horizontal synchronization signal. is there.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image display device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration example of a video signal processing device (video signal processing unit) used in the video display device of the present invention, and FIG.
FIG. 3 is a diagram showing scan line conversion from 0p, 1080p to 1440p, FIG. 3 is a block diagram showing a configuration example of an interpolation filter, FIG. 4 is a diagram showing a phase offset in scan line conversion from 480p, 720p, 1080p to 1440p; FIG.
FIG. 6 shows a progressive-interlace conversion, and FIG.
Is a block diagram showing an embodiment of the video display device of the present invention, FIG. 7 is a diagram for explaining the video display device of the present invention,
FIG. 8 is a diagram showing a display example of a multi-screen, and FIG. 9 is a block diagram showing a configuration example of a video signal processing device for realizing the multi-screen shown in FIG.

[0011] The video display apparatus of the present invention has an interlaced (1440i) with 1440 effective scanning lines or 1440 effective scanning lines, regardless of whether the input video signal is 480i, 1080i, 480p, or 720p. It is characterized in that the format is converted to progressive (1440p). FIG. 1 shows a specific configuration for format conversion to 1440i or 1440p.
In the present embodiment described below, as the most preferred embodiment, the input video signal is 480i, 1080i, 480.
Although there are four types, p and 720p, the video display device of the present invention does not need to use all of these video signals as input video signals. The present invention can be applied to a case where any combination of two or more of them is used as an input video signal.

In FIG. 1, a 480i video signal supplied from a video signal supply source (not shown) is input to an IP converter 11 of an IP converter 1 and is converted into a 480p progressive signal. You. A 1080i video signal supplied from a video signal source (not shown) is I-
1080p input to the IP converter 12 of the P conversion unit 1
Is converted to a progressive signal. The reason why the interlace signal is converted into the progressive signal is to increase the amount of information in the field and to perform the enlargement / reduction processing in the subsequent enlargement / reduction unit 2 with higher image quality.

In this embodiment, the IP converters 11 and 12
However, instead of actually increasing the scanning line density twice, interpolation data for converting to a progressive signal may be stored in a buffer or the like to generate a signal equivalent to the progressive signal. In short, it suffices if the signal has the number of scanning lines of 480p and 1080p.

480p output from the IP converter 11
Is input to the 6/2 converter 21 of the scaling unit 2. The 1080p signal output from the IP converter 12 is input to the 4/3 converter 23 of the scaling unit 2. 480p supplied from a video signal source not shown
Is input to the 6/2 converter 21 as it is. 7 supplied from a video signal source (not shown)
The 20p video signal is supplied to the 2/1 converter 22 of the scaling unit 2.
Is input to

Here, a video signal supply source (not shown) includes, for example, a digital television broadcast receiving unit,
An external device such as a video tape recorder or a video disk player. The format of the input video signal is discriminated, and a switch (switch) is used.
For the converter 12, if it is 480p, to the 6/2 converter 21,
If it is 720p, it is selectively supplied to the 2/1 converter 22, respectively.

The 6/2 converters 21 and 2/1 of the scaling unit 2
The converter 22 and the 4/3 converter 23 receive the input 480
The number of scanning lines for each of the signals p, 720p, and 1080p is increased by 6/2, 2/1, and 4/3, respectively, to obtain 1440.
It is for converting to a signal of p. In the present embodiment, since the processing for the signals of 480p, 720p, and 1080p is all enlargement, reduction processing is not necessary. FIG. 2 shows a manner in which signals of 480p, 720p, and 1080p are subjected to scan line conversion to 1440p.
As shown in FIG. 2, in the conversion from 480p, 720p, 1080p to 1440p, the number of scanning lines is 3, 2, and 4/3, respectively.

Therefore, the scanning line conversion processing for format conversion in the enlargement / reduction unit 2 is all performed by enlargement, and there is no information loss due to the reduction in the scanning line conversion as in the case of unifying to 1080i as described above. There is no. Further, since the interpolation ratio of the interpolation filters constituting the 6/2 converters 21, 21/2 converter 22, and 4/3 converter 23 is a simple integer ratio, the filter coefficients can be easily configured. Therefore, the 6/2 converters 21 and 2/1 converters 22,
The hardware scale of the 4/3 converter 23 does not increase so much.

This will be described more specifically in comparison with the case where the number is unified to 1080i. The interpolation phase in each format, that is, the position of 1440p with respect to the input signal is: 480p → {0, 1/3, 2/3} 720p → {0, 1/2} 1080p → {0, 3/4, 1 / 2, 1/4}, and the scaling unit 2 may have an interpolation filter for each interpolation phase.

On the other hand, when unified to 1080i, 480p → {0, 4/9, 8/9, 3/9, 5/9, 2
/ 9, 6/9, 1/9} 720p → {0, 2/3, 1/3}, and a much larger number of interpolation phases are generated as compared with the case of unifying 1440p.

In the case of unifying them to 1440p, as described above, the enlargement / reduction unit 2 can be constituted by six sets of interpolation filters, so that only an adder is used without using a multiplier as an interpolation filter. Therefore, it is possible to accurately realize the operation on a small scale. On the other hand, in the case of unifying to 1080p, as many as 10 sets of interpolation filters are required, it is necessary to adopt a configuration using a multiplier having high calculation accuracy and a large degree of freedom of the filter coefficient. Therefore, the hardware scale becomes large. In addition, since the denominator has a phase of 9, the interpolation accuracy also deteriorates.

Referring to FIG. 3, the fact that the present invention can reduce the hardware scale will be described. In FIG.
An interpolation filter with coefficients {1/2, 1/2} is taken as an example. 3A and 3B, the same reference numerals are given to the same functional portions. FIG. 3A shows a case where the interpolation filter is constituted by the delay unit 4 and the adder 5. Note that the adder 5 in FIG. 3A is a 1/2 adder. A filter equivalent to the interpolation filter shown in FIG. 3A can also be realized by a delay unit 4, an adder 5, and multipliers 6 and 7, as shown in FIG. The multipliers 6, 7
Is for halving the input signal and outputting it.

FIG. 3B shows the calculation accuracy of the configuration shown in FIG.
In the case of (A), the hardware scale is required to be about 33 times. This is because, assuming that the input signal is 8 bits, a multiplier of 8 bits of the input signal × 8 bits of the coefficient requires 16 adders. Note that the configuration in FIG. 3A has no degree of freedom in the coefficient, but the coefficient can be freely given within the bit precision.

As described above, in the present invention in which the format is unified to 1440p, the interpolation filter of the scaling unit 2 can be realized by the adder, so that the hardware scale can be reduced. Further, even if the interpolation filter is realized by an adder in the case of unifying to 1080p, the hardware scale of the present invention in which the interpolation filter is unified to 1440p is smaller. Thus, the format is 1440
In the present invention that unifies to p, the hardware scale can be reduced in the first place as compared with the case of unifying to 1080p, and the interpolation filter can be configured by an adder. Therefore, the hardware scale can be further reduced. is there.

Further, according to the present invention, it is possible to perform interpolation with high accuracy and little image quality deterioration. When the phase of the interpolation filter is diversified as in the case of unifying to 1080p, a large difference occurs in the image quality depending on the phase, and as a result, the image quality is deteriorated. This is because a component near the phase of 0 or 1 preserves the component closest to the original signal, and a component near the phase 1/2 where the peripheral original signal is mixed has the highest frequency component falling. 1
If there are many interpolation phases in one image, interpolation fringes are generated depending on the presence or absence of a high frequency component. Therefore, 1080p which requires many interpolation phases (same for 1080i)
1440p which requires less interpolation phase compared to conversion to
(The same applies to 1440i)
High image quality.

In FIG. 2, 480p, 72
The interpolation phase of the scan line conversion from 0p, 1080p to 1440p has been described, but the output pixel of phase 0, which outputs the original pixel as it is, has a higher band component than the other interpolation pixels. Therefore, in the scanning line conversion process in the scaling unit 2, the interpolation phase is uniformly offset as shown in FIG. By shifting the interpolation phase, it is possible to prevent image quality deterioration such as line flicker. Shifting the interpolation phase as shown in FIG. 4 can be easily realized by appropriately setting the coefficients of the interpolation filter.

Even if the sharpness of the image quality is slightly lost by shifting the interpolation phase as shown in FIG.
After the signal of 440p or 1440i, the image quality can be controlled by an enhancer or the like that compensates for the high frequency component, so that there is no problem.

Returning to FIG. 1 again, the 1440p signal output from the scaling unit 2 is input to the progressive-interlace (PI) conversion unit 3. When the image display device of the present invention displays a signal of 1440p,
The PI conversion unit 3 becomes unnecessary. In the present embodiment, a case will be described in which a signal of 1440i is finally output and displayed. The PI conversion unit 3 performs interlace conversion on the input 1440p signal and outputs a 1440i signal.

That is, as shown in FIG. 5, one scanning line of the 1440p signal is thinned out for every two scanning lines, and the thinning phase is offset by one scanning line (one line) for each field. Thus, the 1440p progressive signal becomes a 1440i interlace signal having a horizontal frequency of 45 kHz interlaced between the first field and the second field. The signal 1440i is output from the video signal processing device to the outside or displayed on a display unit such as a CRT of the video display device. In the case of an image display device, the output of the PI conversion unit 3 is supplied to a drive circuit for driving the display unit, and the drive circuit drives the display unit to display an image.

In the case of a video display device using a CRT as a display unit, a deflection circuit capable of displaying a 720p signal is used as a base, and the phase of vertical deflection is offset according to the output phase of signal processing to 1440i. A signal may be displayed. Therefore, the video display device of the present invention can be realized by only slightly improving the existing driving circuit (deflection circuit or the like). Even in an interlace-compatible dot matrix display device, a signal of 1440i can be displayed by writing a signal in accordance with an output field of signal processing. Therefore, the video display device of the present invention can be realized without a significant increase in cost.

Further, in the IP conversion section 1, as described above, the input 480i or 1080i signal is not actually made twice the scanning line density, but only a signal equivalent to progressive is generated. In such a case, the following advantages are provided. In this case, the circuits subsequent to the enlargement / reduction unit 2 perform all processing at a clock rate of 74.25 MHz, which is equivalent to the 720p format. 1
080i format clock is the same as 720p7
Since the frequency is 4.25 MHz, 720p,
The signals of 1080i and 1440i can be processed by the same clock.

As described above, when the clocks are unified, the horizontal period and the horizontal effective pixels are 128, which is equivalent to 720p.
It becomes 0 pixels. Since 1080i horizontal effective pixels are 1920 pixels, processing at 74.25 MHz reduces the horizontal effective pixels from the original 1920 pixels to 1280 pixels.
In a consumer television receiver or a dot matrix type display device, 1280 pixels are sufficient for practical use. Of course, the horizontal effective pixel when converted to 1440i is 1
The clock rate of the output of the PI conversion unit 3 may be increased so as to have 920 pixels.

As described above, in the video display apparatus of the present invention, since the format of the video signal is unified to 1440i (or 1440p), it can be converted to a single format by an interpolation filter having a small hardware scale. Becomes possible.

Now, a specific configuration in the case where a CRT is used as a display unit used in the video display device of the present invention will be described with reference to FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
In the above description, various effects associated with unifying the number of effective scanning lines have been described. However, when a CRT is used as a display unit, unifying the horizontal frequency has a significant meaning.

In FIG. 6, the signal of 1440i output from the PI converter 3 is supplied to the CRT 9. Note that the signal of 1440i is actually subjected to various kinds of video signal processing and supplied to the CRT 9, but is not shown.

The synchronous conversion circuit 6 includes a horizontal synchronizing signal (input horizontal synchronizing signal) of an input video signal, a vertical synchronizing signal (input vertical synchronizing signal), a sampling clock (input clock) of the input video signal, and a CRT 9. A display clock required to display the signal of 1440i is input. If the input video signal is 480i, for example, the frequency of the input clock is 13.5 MHz. The frequency of the input vertical synchronization signal is 60 Hz or 59.94 Hz.
When the frequency of the display clock is 60
Hz, and 74.176 MHz when the frequency of the vertical synchronization signal is 59.94 Hz.
z.

The input clock, the input horizontal synchronizing signal, and the input vertical synchronizing signal are also input to the IP conversion unit 1 and the scaling unit 2, and the display clock is also input to the scaling unit 2 and the PI conversion unit 3. You. In FIG. 1, the input clock and the display clock, the input horizontal synchronization signal and the input vertical synchronization signal are
Illustration relating to input to the P converter 1 to the PI converter 3 is omitted.

The synchronization conversion circuit 6 converts the input horizontal synchronization signal to a frequency of 45 k based on the input clock and the display clock.
Synchronous conversion to a horizontal synchronizing signal in the vicinity of Hz. Synchronous conversion may include adjusting the width or phase of the synchronization signal. The synchronization conversion circuit 6 does not convert the frequency of the input vertical synchronization signal,
Adjust the width and phase and output. The horizontal synchronization signal near the frequency of 45 kHz and the frequency are 60 Hz / 59.94 Hz.
Is input to the PLL circuit 7. The horizontal synchronization signal and the vertical synchronization signal output from the synchronization conversion circuit 6 are also input to the scaling unit 2 and the PI conversion unit 3.

The PLL circuit 7 outputs a stable display horizontal synchronizing signal at a frequency of 45 kHz necessary for displaying a 1440i signal on the CRT 9 based on the input horizontal synchronizing signal. The vertical synchronization signal passes through the PLL circuit 7 and is output as a display vertical synchronization signal. PLL circuit 7
Is also an automatic frequency control (AFC) circuit. The display horizontal synchronization signal and the display vertical synchronization signal are supplied to the deflection circuit 8. The deflection circuit 8 includes a deflection yoke (not shown) mounted on the CRT 9, and deflects the electron beam of the CRT 9 in the horizontal and vertical directions. Thereby, the signal of 1440i output from the PI conversion unit 3 has a horizontal scanning frequency of 45 kHz.
Is displayed on the screen of the CRT 9.

In this embodiment, since the video signal supplied to the CRT 9 is a 1440i signal having a horizontal frequency of 45 kHz, the PLL circuit 7 supplies a single display horizontal synchronizing signal having a frequency of 45 kHz to the deflection circuit 8. However, it is not necessary that the horizontal frequency of the video signal supplied to the CRT 9 and the frequency (horizontal scanning frequency) of the display horizontal synchronization signal supplied to the deflection circuit 8 completely match.

FIG. 6 shows a lock range (frequency pull-in range) of the PLL circuit 7. The PLL circuit 7 has a frequency of ± 5% around a center frequency having a resonance gain of 1.0.
Within the range, the frequency can be pulled in, and the CRT
9 can be driven stably. Therefore, PL
The L circuit 7 not only has a frequency of 45 kHz as a center frequency as shown in FIG. 6 but also includes a frequency of 45 kHz in a lock range and supplies a display horizontal synchronization signal having a frequency included in the lock range to the deflection circuit 8. do it.

As in the present invention, making all the input video signals have a horizontal frequency of 45 kHz is extremely effective in displaying a plurality of formats. For example, the horizontal frequency of the XGA format (vertical frequency 60 Hz) according to the VESA standard is 48.4 kHz. As mentioned above, the PLL
The circuit 7 can have a horizontal frequency of 48.4 kHz within the lock range. Therefore, the video display device of the present invention can provide the XG without changing the horizontal scanning frequency.
It also has the ability to display A-format video signals.

The video display apparatus of the present invention configured as described above has an effect that a multi-screen can be displayed with extremely high image quality as described below, in addition to the various basic effects described above. A case of displaying a multi-screen will be described with reference to FIGS.

FIG. 8A shows a 1440i aspect ratio 4: 3 screen displayed at the left end of a 16: 9 aspect ratio screen, and a 480i aspect ratio 4: 3 aspect screen on the remaining portion. The case where is displayed is shown. 1
Since the format of 440i is 480i × 3,
The 480i screens can be displayed side by side in the vertical direction. In this case, the pixels of the screen are thinned out by reduction in the horizontal direction, but in the vertical direction, the original image has the same image quality, and there is no image quality deterioration. As the screen, a screen with an aspect ratio of 4: 3 of 480p may be displayed. In this case, the progressive signal 480p
May be converted to an interlaced signal, and image quality degradation is extremely small.

FIG. 8 (B) shows a 720i screen having an aspect ratio of 16: 9, which is obtained by converting a 720p signal into an interlaced signal, substantially at the center of the screen having an aspect ratio of 16: 9.
Are displayed side by side in the vertical direction. In this case as well, since only the progressive signal is converted into the interlaced signal, the image quality degradation is extremely small.

An example of a configuration for realizing the above-described multi-screen will be described with reference to FIG. The configuration example shown in FIG. 9 shows a case where a maximum of four screens is realized. Inputs 1-4 are 480i, 1080i, 480
p, 720p. Inputs 1-4 are
The signals are input to the IP converters 101 to 104 of the IP conversion unit 10, respectively. The inputs 1 to 4 are connected to the switching unit 4 of the switching unit 40.
01 to 404 are also input. Switches 401 to 404
Selectively switches the outputs of the IP converters 101 to 104 and the inputs 1 to 4 in accordance with a switching control signal (SWCTL) and outputs the signals.

As described above, if the video signals input as inputs 1 to 4 are interlaced signals such as 480i and 1080i, they are converted into progressive signals by IP converters 101 to 104, and enlarged / reduced in the subsequent stage. Part 20
Need to be supplied to If the video signal input as inputs 1 to 4 is a progressive signal such as 480p or 720p, it is necessary to supply the progressive signal as it is to the subsequent enlargement / reduction section 20. Switch 401-
Reference numeral 404 denotes IP converters 101 to 10 according to input signals.
4 is used to switch between using the output 4 and using the input signal as it is. The switching control signal (SW
CTL) can be easily generated by determining the format of the inputs 1 to 4.

The output of the switching section 40 is input to the scaling section 20. The scaling unit 20 includes horizontal scaling units 201H to 201H.
204H, and vertical scalers 201V to 204V. The vertical scaling units 201V to 204V have the same configuration as the scaling unit 2 in FIG. That is, the vertical scalers 201V to 204V include the 6/2 converter 21, the 2/1 converter 22, and the 4/3 converter 23, respectively.
However, depending on the mode of the multi-screen, the vertical scalers 201V to 204V may output the input signal without conversion to 1440p. Horizontal scaler 20
1H to 204H enlarge or reduce the horizontal direction according to each multi-screen.

In the example of FIG. 8A, inputs 1 to
Assuming that 4 corresponds to the screen 〜, the vertical scaler 201V converts the input 1 to 1440p, and the vertical scalers 202V to 204V do not convert the inputs 2 to 4 to 1440p and output as 480p. . In the example of FIG. 8B, assuming that the inputs 1 and 2 in FIG. 9 correspond to the screen, the vertical scaler 201V converts the inputs 1 and 2 to 144
It is output as 720p without conversion to 0p. The horizontal reduction in the horizontal scalers 201H to 204H is in accordance with the size of each screen.

1440p output from the scaling unit 20
(480p or 720p in some cases)
It is input to the PI converters 301 to 304 of the -I converter 30. The PI converters 301 to 304 convert the input progressive signal into an interlace signal. Although not shown here, the PI converter 30
1 to 304 are supplied with a field signal, and the PI converters 301 to 304 receive PI signals based on the field signal.
Convert.

The outputs of the PI converters 301 to 304 are input to the screen synthesizing unit 50. The screen synthesizing unit 50 has a PI
The outputs of the converters 301 to 304 are combined to output a multi-screen 1440i video signal.

As can be seen from the above description, the 1440i or 1440p can be used for the currently existing 480i, 1080i, 480p, 7 while minimizing the increase in hardware scale.
It can be said that this is a format extremely excellent in practical use in that all 20p images are displayed with high image quality.

[0052]

As described above in detail, the video display apparatus of the present invention comprises a first video signal which is an interlace signal having a horizontal frequency of 15.75 kHz, and a horizontal video signal having a horizontal frequency of 33.75 kHz.
A video signal processing unit that processes a second video signal that is a 75 kHz interlace signal as an input video signal and converts the first and second video signals into a third video signal that is an interlace signal with a horizontal frequency of 45 kHz And the third
A CRT display section for displaying the video signal of the CRT, a deflection circuit for horizontally and vertically deflecting the electron beam of the CRT display section to display the third video signal on the CRT display section, and a predetermined lock range. And a PLL circuit for supplying a single horizontal synchronization signal to the deflection circuit. The PLL circuit includes a frequency of 45 kHz in a lock range, and a frequency included in the lock range as a single horizontal synchronization signal. The horizontal synchronization signal is supplied to the deflection circuit. Accordingly, input video signals in a plurality of formats can be converted into a single format that is most practical and displayed. In addition, extremely high-quality video can be displayed while minimizing an increase in hardware scale and complexity of signal processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a video signal processing device used in the present invention.

FIG. 2 from 480p, 720p, 1080p to 1440
FIG. 7 is a diagram showing scan line conversion to p.

FIG. 3 is a block diagram illustrating a configuration example of an interpolation filter.

[FIG. 4] 480p, 720p, 1080p to 1440
FIG. 9 is a diagram illustrating a phase offset in scanning line conversion to p.

FIG. 5 is a diagram showing PI conversion.

FIG. 6 is a block diagram showing one embodiment of the present invention.

FIG. 7 is a diagram for explaining the present invention.

FIG. 8 is a diagram showing a display example of a multi-screen.

FIG. 9 is a block diagram illustrating a configuration example of a video signal processing device when the multi-screen illustrated in FIG. 8 is realized.

[Explanation of symbols]

1,10 interlace-progressive conversion unit (I
-P conversion unit) 2,20 Enlargement / reduction unit 3,30 Progressive-interlace conversion unit (P
-I conversion unit) 6 Synchronous conversion circuit 7 PLL circuit 8 Deflection circuit 9 CRT (cathode ray tube display unit) 11, 12, 101 to 104 IP converter 21 6/2 converter 22 2/1 converter 23 4 / 3 converters 40 switching unit 50 screen synthesizing unit 201H-204H horizontal scaling unit 201V-204V vertical scaling unit 301-304 PI converter 401-404 switching unit

[Procedure amendment]

[Submission date] October 19, 2001 (2001.10.
19)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0048

[Correction method] Change

[Correction contents]

In the example of FIG. 8A, inputs 1 to
Assuming that 4 corresponds to screen ~, vertical scaling
201V converts input 1 to 1440p, and performs vertical scaling.
Small devices 202V to 204V change inputs 2 to 4 to 1440p.
Instead, it is output at 480p. In the example of FIG.
And the inputs 1 and 2 in FIG. , Is compatible with
Then, the vertical scaler 201V inputs the inputs 1 and 2 to 144
It is output as 720p without conversion to 0p. Horizontal scaling
The horizontal reduction in the small devices 201H to 204H
It depends on the size of each screen.

Claims (3)

[Claims] 1. A first video signal which is an interlace signal having a horizontal frequency of 15.75 kHz, and a horizontal frequency of 33.7.
In a video display apparatus using a second video signal, which is an interlace signal of 5 kHz, as an input video signal, the first and second video signals are converted into a third video signal, which is an interlace signal of a horizontal frequency of 45 kHz. A video signal processing unit for processing; a cathode ray tube display unit for displaying the third video signal; and an electron beam of the cathode ray tube display unit for horizontally displaying the third video signal on the cathode ray tube display unit. And a deflection circuit for vertical deflection, and a PLL circuit having a predetermined lock range and supplying a single horizontal synchronization signal to the deflection circuit, wherein the PLL circuit includes a frequency of 45 kHz in the lock range, An image, wherein a horizontal synchronization signal having a frequency included in the lock range is supplied to the deflection circuit as the single horizontal synchronization signal. Display devices. 2. The method according to claim 1, wherein a fourth video signal, which is a progressive signal having a horizontal frequency of 31.5 kHz, is used as an input video signal in addition to said first and second video signals. The video display device according to claim 1, wherein the video signal is converted into the third video signal. 3. In addition to the first and second video signals, a fifth video signal, which is a progressive signal having a horizontal frequency of 45 kHz, is used as an input video signal.
3. The video display device according to claim 1, wherein the fifth video signal is converted into the third video signal.