JP2002218279A - Image processor, image processing method, image display device and image display method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly accurately convert digital signals to analog signals in an image processor for inputting digital image signals, performing a prescribed processing, then converting them to analog image signals and outputting them. SOLUTION: The D/A conversion circuit 10 of an R channel converts inputted digital image signals to corresponding analog signals (current signals) and outputs them and a resistor 11 converts them to voltage signals. Output signals from a buffer 12 are compared with a reference voltage 27 by a comparator 13 at the timing at which a comparator enable signal becomes 'H' and a voltage corresponding to a compared result is outputted. Output from the comparator 13 is supplied through an integrator constituted of the resistor 14 and a capacitor 15 to the adjusting terminal of the D/A conversion circuit 10 and the amplitude level of the output voltage is adjusted. The similar operations are performed in a G channel and a B channel as well. At the time, since all the channels are adjusted with the same reference voltage 27 as a reference, deviations among the channels are offset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, an image processing method, and an image display apparatus and an image display method, and more particularly, to an image to which a digital image signal is input, converted into an analog image signal, and output or displayed. The present invention relates to a processing device, an image processing method, an image display device, and an image display method.

[0002]

2. Description of the Related Art For example, in an image display device such as a digital television receiver or an image processing device such as a graphic accelerator, a plurality of image signals (for example, R, G, B signals) constituting one image are converted. After performing predetermined processing (for example, image quality adjustment processing, drawing processing, etc.) on such digital image signals, each image signal is converted into an analog signal for output or display.

[0003]

By the way, when converting a digital image signal into an analog image signal, D / A
It is necessary to use a (Digital to Analog) conversion circuit. However, since the D / A conversion circuit has a conversion error, it is necessary to perform adjustment at the time of shipment to compensate for the conversion error. Here, a D / A conversion circuit is provided for each image signal, and since human vision is very sensitive to color differences, it is necessary to accurately adjust a plurality of D / A conversion circuits. Had a problem that it required a great deal of labor.

In addition, the D / A conversion circuit and the circuit accompanying it have a problem that the color tone may change due to long-term use because the conversion characteristics change even with aging.

The present invention has been made in view of the above situation, and has as its object to provide an image processing apparatus and an image display apparatus which can easily adjust a D / A conversion circuit. And

It is another object of the present invention to provide an image processing apparatus, an image processing method, an image display apparatus, and an image display method in which the image quality does not change even with aging.

[0007]

According to the present invention, there is provided an image processing apparatus for inputting a digital image signal, performing predetermined processing, converting the digital image signal into an analog image signal, and outputting the analog image signal. Input means for inputting an image signal; converting means for converting a digital image signal into a corresponding analog image signal; detecting means for detecting a signal level of a predetermined portion of the analog image signal; An image processing apparatus comprising: an adjusting unit that adjusts a converting unit; and an output unit that outputs an analog image signal adjusted by the adjusting unit.

The input means inputs a digital image signal. The conversion means converts the digital image signal into a corresponding analog image signal. The detecting means detects a signal level of a predetermined portion of the analog image signal. The adjusting means adjusts the converting means according to the detection result of the detecting means. The output means outputs the analog image signal adjusted by the adjusting means.

An image display device which receives a digital image signal, performs predetermined processing, converts the digital image signal into an analog image signal, and displays the analog image signal. Conversion means for converting the signal into a signal; detection means for detecting a signal level of a predetermined portion of the analog image signal; adjustment means for adjusting the conversion means in accordance with the detection result of the detection means; and adjustment by the adjustment means. And a display means for displaying the analog image signal.

Here, the input means inputs a digital image signal. The conversion means converts the digital image signal into a corresponding analog image signal. The detecting means detects a signal level of a predetermined portion of the analog image signal. The adjusting means adjusts the converting means according to the detection result of the detecting means. The display means displays the analog image signal adjusted by the adjustment means.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, an image processing device refers to a circuit for image processing mounted on a digital television receiver or the like, a graphic accelerator, or the like. The image display device refers to a digital television receiver or the like.

FIG. 1 is a diagram showing a configuration example of a first embodiment of the present invention. As shown in this figure, the image processing apparatus of the present invention includes D / A conversion circuits 10, 20, 30 (conversion means), resistors 11, 21, 31, buffers 12, 22, and 3.
2 (output means), comparators 13, 23, 33 (detection means, adjustment means), resistors 14, 24, 34 (adjustment means), capacitors 15, 25, 35 (adjustment means), and reference voltage 27 (adjustment means) ).

Here, the D / A conversion circuits 10, 20, 30
Are the input R (Red), G (Green), and B, respectively.
The digital image signal of the (Blue) channel (ch) is converted into a corresponding analog image signal and output.

The resistors 11, 21, 31 convert analog image signals (current signals) output from the D / A conversion circuits 10, 20, 30 into corresponding voltage signals. Buffer 1
2, 22, and 32 eliminate electrical interference with a subsequent circuit by impedance conversion.

When the comparator enable signal is at "H", the comparators 13, 23, and 33 output the result of comparing the output signals of the buffers 12, 22, and 32 with the reference voltage 27, and output the comparator enable signal. When the signal is in the "L" state, the output impedance is kept in the high impedance state.

The resistors 14, 24, 34 and the capacitor 1
5, 25, and 35 are lossy integration circuits (or L
A PF (Low Pass Filter) is configured, and the output signals of the comparators 13, 23, and 33 are integrated and supplied to adjustment terminals of the D / A conversion circuits 10, 20, and 30.

The adjustment terminals of the D / A conversion circuits 10, 20, 30 are terminals for adjusting the output amplitude in the D / A conversion according to the applied voltage. Next, the operation of the above embodiment will be described. Since the operations of the circuits of the R, G, and B channels are the same, only the operation of the R channel alone will be described below.

When an R channel digital image signal is input, the D / A conversion circuit 10 converts the digital image signal into an analog image signal (current signal) in synchronization with a predetermined clock signal and outputs the analog image signal.

The resistor 11 converts a current signal output from the D / A conversion circuit 10 into a voltage signal. Buffer 12
Outputs a voltage multiplied by 1 at the resistor 11.

At this time, since the D / A conversion circuit 10 has a conversion error and the resistor 11 and the buffer 12 also have an error, a true signal is output from the buffer 12 according to the error. (≠ 1) The multiplied signal is output.

FIG. 2A shows D / D in the unadjusted case.
FIG. 3 is a diagram illustrating an example of a signal output from an A-conversion circuit. The example of this figure shows a case where k> 1, where the pedestal level corresponding to the black level in the non-display state is larger than the prescribed level shown by the broken line.
The signal amplitude is also greater than the true level.

When the comparator enable signal shown in FIG. 2D becomes "H", the comparator 13 compares the reference voltage 27 with the output signal of the buffer 12, and outputs a comparison result. .

Here, the reference voltage 27 is equal to the prescribed level (broken line) shown in FIG. When the comparator enable signal is in the “H” state,
That is, when the pedestal section is output from the buffer 12, the reference voltage 27, which is a specified level, and the buffer 12
And outputs a negative signal when the output level of the buffer 12 is higher, and outputs a positive signal when the output level is the opposite.

The resistor 14 and the capacitor 15 integrate the output of the comparator 13 and supply it to the adjustment terminal of the D / A conversion circuit 10. When the comparator 13 enters the high impedance state, the output voltage is held.

Since the output amplitude of the D / A conversion circuit 10 changes according to the voltage applied to the adjustment terminal, the D / A conversion circuit 10, the resistor 11, the buffer 12, and the comparator 1
The pedestal level is adjusted to be equal to the prescribed level, the reference voltage 27, by a feedback loop constituted by 3, a resistor 14, and a capacitor 15.

When the adjustment of the D / A conversion circuit 10 is completed,
The comparator enable signal input to the comparator 13 becomes “L”. Then, the comparator 13
Is in a high impedance state, and the electric charge accumulated in the capacitor 15 is held, so that the D / A conversion circuit 10
Will maintain the adjusted state. Therefore, the buffer 12 outputs an analog image signal containing no error as shown in FIG. In the example shown in FIG. 3, the pedestal level of the signal matches the prescribed level indicated by the broken line, and the amplitude of the signal is adjusted to a normal state.

At this time, the same operation is performed in circuits of other channels. FIGS. 2B and 2C are diagrams illustrating an example of signals output from the unadjusted D / A conversion circuits 20 and 30. FIG. In the signal shown in FIG. 2B, the pedestal level is smaller than the prescribed level shown by the broken line, and the signal amplitude is also small. In the signal shown in FIG. 2C, the pedestal level is higher than the prescribed level shown by the broken line, and the amplitude of the signal is also higher.

The analog image signal adjusted as described above is supplied to a display unit (not shown) (for example, a CRT (Cathode
Ray Tube) monitor). By the way, the adjustment for the R, G, B channels
Since the same reference voltage 27 is used as a reference, deviations between the respective channels are cancelled, and when the input signals are at the same level, as shown in FIG.
The output signals of the channels are at the same level.

As described above, human vision is color difference, that is,
It is very sensitive to deviations between channels. However, by adjusting all the channels on the basis of the same reference voltage 27 as described above, it is possible to reliably cancel the deviation between the channels and generate an image having no color difference.

Next, a second embodiment of the present invention will be described. FIG. 4 is a diagram illustrating a configuration example of the second embodiment of the present invention. In this figure, the image processing device 1
It includes the circuit shown in FIG. The superimposing units 36 to 38 (input means, superimposing means) superimpose an amplitude adjustment signal on each of the Rch, Gch, and Bch digital image signals and output the resultant signal. The digital image signals output from the superimposing units 36 to 38 are supplied to the D / A conversion circuits 10 and 2 shown in FIG.
0, 30 respectively. In the second embodiment, the timing at which the comparator enable signal input to the comparators 13, 23, and 33 shown in FIG. 1 becomes "H" and the point that the reference voltage 27 is at the same level as the amplitude adjustment signal. This is different from the case of the first embodiment.

Next, the operation of the above embodiment will be described. The superimposing units 36 to 38 superimpose an amplitude adjustment signal as shown in FIGS. 5A to 5C on the pedestal part of the digital image signal and output the superimposed signals. Since the signals input to the superimposing units 36 to 38 are digital signals, it is possible to easily superimpose the amplitude adjustment signal on the pedestal unit. It is desirable to set the amplitude adjustment signal to a value close to the maximum amplitude of the digital image signal from the viewpoint of reducing errors.

The digital image signal of each channel on which the amplitude adjustment signal is superimposed is supplied to the D / A conversion circuit 1 shown in FIG.
0, 20, and 30 are converted to analog image signals and output from the buffers 12, 22, and 32, respectively. In the following, for the same reason as described above,
The operation of only the R channel will be described.

As shown in FIG. 5 (D), the comparator 13 synchronizes with a comparator enable signal which becomes “H” at the timing when the amplitude adjustment signal is output, and outputs a reference voltage 27 (in this embodiment, , The voltage of the same level as the amplitude adjustment signal) and the output of the buffer 12, and perform feedback control so that the amplitude adjustment signal becomes equal to the reference voltage 27. As a result, as shown in FIG. 6, since the amplitude adjustment signal is adjusted to have a prescribed level, the analog image signal is also adjusted to have a normal amplitude.

Similar operations are performed in circuits of other channels. FIGS. 5B and 5C are diagrams illustrating examples of signals output from the unadjusted D / A conversion circuits 20 and 30. FIG. In the example of the G channel shown in FIG. 5B, the pedestal level is smaller than the prescribed level shown by the broken line, and the signal amplitude is also small. In the example of the B channel shown in FIG. 5C, the pedestal level is higher than the prescribed level shown by the broken line, and the amplitude of the signal is also higher.

As described above, the adjustment for the R, G, and B channels is performed with reference to the same reference voltage 27. Therefore, the deviation between the channels is canceled out, and when the input signals are at the same level, the adjustment is performed. As shown in FIG. 6, R, G, B
The output signals of the channels are at the same level.

According to the above embodiment, the A / D is adjusted with reference to the amplitude adjustment signal having an amplitude close to the maximum amplitude.
Since the conversion circuits 10, 20, 30 are adjusted,
More precise adjustment is possible than when the pedestal level is used as a reference.

Next, a third embodiment of the present invention will be described. FIG. 7 shows a configuration example of the third embodiment of the present invention. In this embodiment, as compared with the case of FIG. 1, the image quality adjustment units 40 to 42 include D / A conversion circuits 10, 20, and 30 of each channel and buffers 12, 22, and 32.
Is inserted between each. Other configurations are the same as those in FIG.

FIG. 8 is a diagram showing a detailed configuration example of the image quality adjusting section 40 shown in FIG. In this figure, a multiplier 40
a (adjustment means) multiplies the output of the D / A conversion circuit 10 by a predetermined coefficient and outputs the result.

When the image quality adjustment enable signal is at "H", the switch 40b (stopping means) switches the multiplier 4
0a and the image quality adjustment enable signal is "L".
In this case, the output of the D / A conversion circuit 10 is selected and output.

Since the image quality adjusting sections 41 and 42 have the same configuration, detailed description thereof will be omitted. next,
The operation of the above embodiment will be described.

In order to adjust the image quality, it is necessary to adjust the amplitude of the analog image signal for each channel by the image quality adjustment units 40 to 42 shown in FIG. by the way,
If the amplitude of the signal output from the D / A conversion circuits 10, 20, 30 is simply changed, malfunction may occur because feedback control is performed. Therefore,
With such a configuration, it is difficult to adjust the image quality normally.

Therefore, in the present embodiment, the image quality adjusting unit 4
Switches 40b, 41b, 42b for 0 to 42
(Partly not shown) is provided, and when the pedestal unit is output from the D / A conversion circuits 10, 20, and 30, a signal bypassing the multipliers 40a, 41a, and 42a (partly not shown) is used. The feedback control is performed to adjust the amplitude to be normal. Also, the D / A conversion circuits 10 and 2
When a signal other than the pedestal signal is output from 0 and 30, an analog image signal multiplied by a predetermined coefficient by multipliers 40a, 41a and 42a (partially not shown) is selected and output, so that the image quality is improved. Adjustment is possible.

FIG. 9 is a timing chart for explaining the operation of the third embodiment of the present invention. FIG.
2A illustrates an example of an analog image signal output from the D / A conversion circuit 10. In this example, the pedestal level is higher than a prescribed level indicated by a broken line.

When the image quality adjustment enable signal shown in FIG. 9E becomes "H",
The output of the multiplier 40a is selected and output. Otherwise, the output of the D / A conversion circuit 10 is selected and output.

The pedestal section output from the image quality adjustment section 40 is obtained by the comparator 13 in synchronization with the comparator enable signal shown in FIG. 10
Is adjusted. At this time, the image quality adjustment unit 40
Since the output of the A-conversion circuit 10 is directly output, the adjustment is performed normally regardless of the adjustment state of the image quality adjustment unit 40.

On the other hand, when a signal other than the pedestal portion is output from the D / A conversion circuit 10, the image quality adjustment enable signal is set to "H" as shown in FIG. The analog image signal (the signal whose amplitude has been adjusted) output from the conversion circuit 10 is output after being multiplied by a predetermined coefficient by the multiplier 40a.

FIGS. 9B and 9C show examples of analog image signals output from the D / A conversion circuits 20 and 30, respectively. In the example shown in FIG. 9B, the pedestal level is lower than a prescribed level indicated by a broken line. In the example shown in FIG. 9C, the pedestal level is higher than the prescribed level indicated by the broken line. For these signals, the pedestal level is adjusted in synchronization with the comparator enable signal shown in FIG. 9D, and the image quality adjustment enable signal shown in FIG. The image quality is adjusted in synchronization with.

The analog image signal whose pedestal level has been adjusted and the image quality has been adjusted in this way are output to the outside from buffers 12, 22, and 32. FIG.
The same digital image signal is input, and the
42 is different from the buffer 12,
In this figure, the analog image signals output from 22, 22 are superimposed. As shown in this figure, the R channel,
The analog image signals of the G channel and the B channel are adjusted so that the pedestal level matches a prescribed level, and the amplitude is adjusted according to a coefficient for image quality adjustment.

As described above, according to the third embodiment of the present invention, even when the image processing apparatus includes the image quality adjustment units 40 to 42, the D / A conversion circuits 10, 20, and 30 can be used. It is possible to adjust and to offset the deviation between each channel.

Next, a fourth embodiment of the present invention will be described. FIG. 11 is a diagram illustrating a configuration example of the fourth embodiment of the present invention. In the embodiment shown in this figure, the circuit configuration is such that a DC level does not remain in an analog image signal. As shown in FIG.
The superimposition units 36 to 38 for superimposing the amplitude adjustment signal are added at the preceding stage of 0, 20, and 30. In this figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. In this embodiment, capacitors 50 to 52 (removal means), resistors 53 to 55, clamp circuits 56 to 58 (clamp means), and a reference voltage 59 are newly added as compared with the case of FIG. I have.

The capacitors 50 to 52 include resistors 53 to 55
At the same time, a high-pass filter is configured to remove a DC component included in the analog image signals output from the D / A conversion circuits 10, 20, and 30.

The clamp circuits 56 to 58 are connected to the buffer 1
The analog image signals output from 2, 22, and 32 are latched in synchronization with the clamp pulse, and the DC level thereof is adjusted to be equal to the reference voltage 59.

The reference voltage 59 outputs a prescribed voltage corresponding to the pedestal level. Next, the operation of the above embodiment will be described. In the following, only the operation of the R channel will be described.

The digital image signal of the R channel is superimposed on the amplitude adjustment signal in the superimposing section 36 and supplied to the D / A conversion circuit 10. The D / A conversion circuit 10 converts the input digital image signal into an analog signal (current signal).
And output. The resistor 11 converts a current signal into a corresponding voltage signal. FIG. 12 (A) shows unregulated D / A
FIG. 4 is a diagram illustrating an example of an output of the conversion circuit 10.

The capacitor 50 and the resistor 53 are connected to the resistor 1
Only the high frequency signal determined according to the time constant among the voltage signals generated in 1 is passed and supplied to the buffer 12.
The buffer 12 multiplies the voltage generated at the resistor 53 by one and outputs it. Here, since the DC level is not stored in the analog image signal output from the buffer 12, the DC level of the signal fluctuates according to the amplitude of the signal.

The clamp circuit 56 is supplied with the clamp pulse shown in FIG. 12 (D) and the reference voltage 59. When the clamp pulse becomes "H", the output signal of the buffer 12 is output. Latching is performed and the level of the latched signal is adjusted to be equal to the reference voltage 59. Here, the clamp pulse becomes “H” when the pedestal section is output, and the reference voltage 59 is equal to the prescribed level of the pedestal section. The pedestal part is clamped to a prescribed level, and the state shown in FIG.

The comparator 13 compares the signal output from the clamp circuit 56 with the reference voltage 27 at the timing when the comparator enable pulse becomes “H” shown in FIG. 13D, and outputs the result. I do. Since the reference voltage 27 is equal to the level of the amplitude adjustment signal, if the amplitude adjustment signal included in the signal supplied from the clamp circuit 56 is larger than the reference voltage 27, a negative voltage is applied. When the signal is smaller than the reference voltage 27, a positive voltage is output.

The output from the comparator 13 is a resistor 14
After being integrated by the integrator constituted by the capacitor 15 and the output, the signal is supplied to the adjustment terminal of the D / A conversion circuit 10.

Since the output amplitude of the D / A conversion circuit 10 changes according to the voltage applied to the adjustment terminal, the D / A conversion circuit 10, the resistor 11, the capacitor 50, the resistor 53, the buffer 12, the clamp circuit The level of the amplitude adjustment signal is controlled to be equal to the reference voltage 27 by a feedback loop including 56, the comparator 13, the resistor 14, and the capacitor 15.

The above operation is also performed on the G channel and the B channel, as shown in FIGS.
The analog image signals output from the D / A conversion circuits 20 and 30 shown in (C) are shown in FIGS. 13 (B) and 13 (C).
After the pedestal level is adjusted to be equal to the reference voltage 59, the level of the amplitude adjustment signal is adjusted to be equal to the reference voltage 27, as shown in FIG.

FIG. 14 is a diagram showing the R, G, and B channel analog image signals output from the buffers 12, 22, 32 when the same digital image signal is input. As shown in this figure, when the same digital image signal is input to each channel, a signal having the same pedestal level and amplitude level is output.

As described above, according to the fourth embodiment of the present invention, the D / A conversion circuits 10, 20, and 30 can be accurately adjusted even in an image processing apparatus that does not store a DC level. Becomes possible. Also, R channel, G
Since the same reference voltages 27 and 59 are used to adjust the pedestal level and the amplitude for all the channels and the B channel, it is possible to eliminate the deviation between the channels.

Next, a configuration example of the fifth embodiment of the present invention will be described. FIG. 15 is a diagram illustrating a configuration example of the fifth embodiment of the present invention. In this embodiment, FIG.
The image quality adjustment units 60 to 62 are newly added to the embodiment shown in FIG. Other configurations are the same as those in FIG.

Each of the image quality adjustment units 60 to 62 has the same configuration as that shown in FIG. 8, and multiplies the input analog image signal by a coefficient. When the image quality adjustment enable signal is "H", Outputs a signal multiplied by a coefficient, and outputs a signal not multiplied by a coefficient when the image quality adjustment enable signal is in an “L” state.

Next, the operation of the above embodiment will be described. In the following, only the operation of the R channel will be described. The digital image signal of the R channel is
In the superimposing section 36, the amplitude adjustment signal is superimposed and D / A
It is supplied to the conversion circuit 10.

The D / A conversion circuit 10 converts the input digital image signal into an analog signal (current signal) and outputs it. The resistor 11 converts a current signal into a corresponding voltage signal. FIG. 16A shows an unadjusted D / A conversion circuit 10.
FIG. 6 is a diagram showing an example of the output of FIG.

The capacitor 50 and the resistor 53 are connected to the resistor 1
Only the high frequency signal determined according to the time constant among the voltage signals generated in 1 is passed and supplied to the image quality adjustment unit 60. When the image quality adjustment enable signal is “L”, the image quality adjustment unit 60 outputs the voltage generated at the resistor 53 as it is, and when the image quality adjustment enable signal is “H”, the image quality adjustment unit 60 outputs the voltage to the resistor 53. The resulting voltage is multiplied by a coefficient and output.

The buffer 12 multiplies the signal output from the image quality adjustment unit 60 by one and outputs it. Here, the buffer 12
Since the DC level is not stored in the analog image signal output from, the DC level of the signal fluctuates according to the amplitude of the signal.

The clamp pulse shown in FIG. 16 (D) and the reference voltage 59 are supplied to the clamp circuit 56, and when the clamp pulse becomes "H", the output signal of the buffer 12 is output. Latching is performed and the level of the latched signal is adjusted to be equal to the reference voltage 59. Here, the clamp pulse becomes “H” when the pedestal section is output, and the reference voltage 59 is equal to the specified level, so that the signal output from the clamp circuit 56 has the pedestal level specified. 17A, and the state shown in FIG.

The comparator 13 compares the signal output from the clamp circuit 56 with the reference voltage 27 at the timing when the comparator enable pulse becomes “H” shown in FIG. 17D, and outputs the result. I do. Since the reference voltage 27 is equal to the level of the amplitude adjustment signal, if the amplitude adjustment signal included in the signal supplied from the clamp circuit 56 is larger than the reference voltage 27, a negative voltage is applied. When the signal is smaller than the reference voltage 27, a positive voltage is output.

The output from the comparator 13 is
After being integrated by the integrator constituted by the capacitor 15 and the output, the signal is supplied to the adjustment terminal of the D / A conversion circuit 10.

Since the output amplitude of the D / A conversion circuit 10 changes according to the voltage applied to the adjustment terminal, the D / A conversion circuit 10, the resistor 11, the capacitor 50, the resistor 53, the image quality adjustment unit 60, A feedback loop constituted by the buffer 12, the clamp circuit 56, the comparator 13, the resistor 14, and the capacitor 15 controls the level of the amplitude adjustment signal to be equal to the reference voltage 27.

The above operation is also performed on the G channel and the B channel, as shown in FIGS.
The analog image signals output from the unadjusted D / A conversion circuits 20 and 30 shown in FIG.
As shown in FIG. 7 (C), the pedestal level is
After being clamped to be equal to 9, the level of the amplitude adjustment signal is adjusted to be equal to the reference voltage 27.

FIG. 18 shows the case where the same digital image signal is input and the R channel when the image quality adjusting units 60 to 62 are set to be different from each other.
FIG. 3 is a diagram in which analog image signals of a G channel and a B channel are superimposed. As shown in this figure, the output signals of the respective channels have the same pedestal level and amplitude adjustment signal, and output signals having different amplitudes according to the settings of the image quality adjustment units 60 to 62.

As described above, according to the fifth embodiment of the present invention, even in an image processing apparatus that does not store a DC level and has an image quality adjusting unit, the D / A conversion is performed. The circuits 10, 20, 30 can be adjusted precisely. In addition, all of the R channel, the G channel, and the B channel have the same reference voltage 2.
Since the pedestal level and the amplitude are adjusted using 7, 59, the deviation between channels can be eliminated.

As described above, according to the embodiment of the present invention, it is possible to reduce the loss of white, black, and white balance caused by the shift in signal amplitude due to the temperature rise or aging of the image processing apparatus. Can be prevented.

Further, according to the embodiment of the present invention, it is not necessary to adjust the amplitude between channels at the time of manufacturing, so that production costs can be reduced. The above-described first to fifth embodiments are merely examples, and it goes without saying that the present invention is not limited to only such circuits.

[0078]

As described above, according to the present invention, there is provided an image processing apparatus which receives a digital image signal, performs predetermined processing, converts the digital image signal into an analog image signal, and outputs the analog image signal.
Input means for inputting a digital image signal; converting means for converting the digital image signal into a corresponding analog image signal; detecting means for detecting a signal level of a predetermined portion of the analog image signal; And adjusting means for adjusting the converting means, and output means for outputting the analog image signal adjusted by the adjusting means, so that the digital image signal can be converted to the analog image signal with high accuracy. Becomes possible.

Further, in an image display device for inputting a digital image signal, performing predetermined processing, converting the digital image signal into an analog image signal and displaying the analog image signal, input means for inputting the digital image signal corresponds to the digital image signal. Converting means for converting to an analog image signal, detecting means for detecting a signal level of a predetermined portion of the analog image signal, and adjusting means for adjusting the converting means according to a detection result of the detecting means,
And display means for displaying the analog image signal adjusted by the adjustment means, so that the digital image signal can be converted into the analog image signal with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 4 is a circuit diagram showing a configuration example according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the embodiment shown in FIG. 4;

FIG. 6 is a timing chart for explaining the operation of the embodiment shown in FIG. 4;

FIG. 7 is a circuit diagram showing a configuration example of a third embodiment of the present invention.

8 is a diagram illustrating a detailed configuration example of an image quality adjustment unit illustrated in FIG. 7;

FIG. 9 is a timing chart for explaining the operation of the embodiment shown in FIG. 7;

FIG. 10 is a timing chart for explaining the operation of the embodiment shown in FIG. 7;

FIG. 11 is a circuit diagram illustrating a configuration example of a fourth embodiment of the present invention.

FIG. 12 is a timing chart for explaining the operation of the embodiment shown in FIG. 11;

FIG. 13 is a timing chart for explaining the operation of the embodiment shown in FIG. 11;

FIG. 14 is a timing chart for explaining the operation of the embodiment shown in FIG. 11;

FIG. 15 is a circuit diagram illustrating a configuration example according to a fifth embodiment of the present invention.

FIG. 16 is a timing chart for explaining the operation of the embodiment shown in FIG. 15;

FIG. 17 is a timing chart for explaining the operation of the embodiment shown in FIG. 15;

18 is a timing chart for explaining the operation of the embodiment shown in FIG.

[Explanation of symbols]

1. Image processing apparatus, 10, 20, 30 ... D / A conversion circuit, 11, 21, 31 ... Resistance, 12, 22, 32 ...
... Buffer, 13, 23, 33 ... Comparator, 1
4, 24, 34 ... resistor, 15, 25, 35 ... capacitor, 36, 37, 38 ... superimposed part, 40, 41, 42
... Image quality adjustment section, 40a... Multiplier, 40b... Switch, 50, 51, 52... Capacitors, 53, 54, 5
5 ... resistance, 56, 57, 58 ... clamp circuit, 2
7, 59... Reference voltage, 60, 61, 62.

Claims (9)

[Claims] 1. An image processing apparatus which receives a digital image signal, performs predetermined processing, converts the digital image signal into an analog image signal, and outputs the analog image signal. Converting means for converting to a corresponding analog image signal; detecting means for detecting a signal level of a predetermined portion of the analog image signal; adjusting means for adjusting the converting means according to a detection result of the detecting means; An output unit that outputs an analog image signal adjusted by the adjustment unit. 2. An adjusting means for adjusting a signal level of an analog image signal output from the converting means for the purpose of adjusting image quality, and when a predetermined portion of the analog image signal is output from the converting means. The image processing apparatus according to claim 1, further comprising: a stopping unit configured to stop an operation of the adjusting unit. 3. An image processing apparatus according to claim 1, wherein said detecting means detects a pedestal level of said analog image signal as said predetermined portion. 4. The image processing apparatus according to claim 1, further comprising a superimposing unit configured to superimpose an adjustment signal for adjusting the converting unit on the digital image signal before being input to the converting unit. The image processing apparatus according to claim 1, wherein the image is detected as the predetermined portion. 5. The image processing apparatus according to claim 1, further comprising: a removing unit configured to remove a DC component included in the analog image signal output from the converting unit; and a clamp unit configured to clamp the analog image signal output from the converting unit to a predetermined level. The output unit outputs an analog image signal from which a DC component has been removed by the removal unit, and the detection unit detects an adjustment signal superimposed by the superimposition unit after being clamped by the clamp unit. The image processing apparatus according to claim 4, wherein: 6. The digital image signal includes a plurality of digital image signals constituting one image, and the adjusting means includes a predetermined portion included in each of the plurality of digital image signals, 2. An image processing apparatus according to claim 1, wherein each digital image signal is adjusted by comparing the digital image signal with a reference level. 7. An image processing method for inputting a digital image signal, performing predetermined processing, converting the digital image signal into an analog image signal, and outputting the analog image signal, wherein: an inputting step of inputting the digital image signal; A conversion step of converting to a corresponding analog image signal; a detection step of detecting a signal level of a predetermined portion of the analog image signal; an adjustment step of adjusting the conversion step according to a detection result of the detection step; Outputting an analog image signal adjusted by the adjusting step. 8. An image display device which receives a digital image signal, performs predetermined processing, converts the digital image signal into an analog image signal, and displays the analog image signal. Converting means for converting to a corresponding analog image signal; detecting means for detecting a signal level of a predetermined portion of the analog image signal; adjusting means for adjusting the converting means according to a detection result of the detecting means; Display means for displaying the analog image signal adjusted by the adjusting means. 9. An image display method for inputting a digital image signal, subjecting the digital image signal to predetermined processing, converting the digital image signal into an analog image signal and displaying the analog image signal, wherein: an input step of inputting the digital image signal; A conversion step of converting to a corresponding analog image signal; a detection step of detecting a signal level of a predetermined portion of the analog image signal; an adjustment step of adjusting the conversion step according to a detection result of the detection step; A display step of displaying the analog image signal adjusted by the adjusting step.