JP2002217688A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit with a PLL function which can realize a required output frequency regardless of a phase comparing frequency. SOLUTION: A plurality of stages of buffers 11-15 which can selectively generate different delay values respectively are provided as buffer means provided in a voltage control oscillation circuit comprising a PLL, and a required output frequency is obtained by a combination of the delay values (td1-td5) of the buffers of the respective stages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a PLL (Phase Locke) in a circuit.
d Loop) AS with a built-in circuit as a synthesizer
The present invention relates to a semiconductor integrated circuit such as an IC.

[0002]

2. Description of the Related Art In recent years, the speed of information communication devices such as personal computers has been increasing, and it is necessary to perform high-speed processing inside an ASIC. Therefore, a PLL (Phase Locke)
It has become essential to incorporate and use a (d Loop) circuit as a synthesizer. However, in a frequency synthesizer using a PLL circuit, if the phase comparison frequency is low (the number of times of phase matching is small), the output frequency cannot be stabilized.
The effect on peripheral circuits connected to this output is also a problem. For this reason, there is a need for a circuit that can perform fine frequency modulation and obtain a stable output frequency without being caused by a low phase comparison frequency.

FIG. 17 is a block diagram showing the overall configuration of a semiconductor integrated circuit according to the prior art. In the figure, 1 is a reference frequency (fin) input terminal, PC is a phase comparator (P
phase detector, CP is a charge pump (Charge Pump), and LPF is a loop filter composed of a low-pass filter (Low Pass Filter). 2 is VCO (Voltage Con)
tolled Oscillator), 2a,
2b is an oscillation PMOS transistor, and 2c and 2d are oscillation NMOS transistors. Reference numerals 3, 4, 5, 6, and 7 are VCO: 2 buffers. 8 is the output frequency (fou
t) Output terminal, 9 is a frequency divider: DIV1 (1 / N), 1
0 is a frequency dividing circuit: DIV2 (1 / M). Oscillation PM
The OS transistors 2a and 2b and the oscillation NMOS transistors 2c and 2d are connected to the buffers 3, 4,
A voltage source composed of an amplifier circuit that supplies a voltage to 5, 6, and 7 is configured.

In the circuit shown in FIG. 17, a reference frequency input from a reference frequency input terminal 1, ie, a reference clock (f
in) The input and a comparison input fed back from the VCO: 2 via the frequency dividing circuit 10 are compared by a phase comparator PC to detect a phase comparison frequency, and this phase comparison frequency is used as a charge pump CP and a low-pass filter. The output frequency is obtained by processing with the LPF and VCO: 2.

[0005]

In such a conventional circuit, the output frequency is uniquely determined according to the phase comparison frequency detected and compared by the phase comparator PC. And it is difficult to obtain an output frequency stably.

An object of the present invention is to provide a semiconductor integrated circuit having a PLL function capable of realizing a desired output frequency regardless of a phase comparison frequency.

[0007]

A PLL according to the first invention
In a semiconductor integrated circuit having a function, a plurality of buffers capable of selectively generating different delay values are provided as buffer means provided in a voltage-controlled oscillator constituting a PLL, and a combination of delay values of buffers in each stage is provided. Thus, a desired output frequency is obtained.

In a semiconductor integrated circuit according to a second aspect of the present invention, a plurality of voltage sources for selectively generating different delay values are provided in the respective buffers.

In a semiconductor integrated circuit according to a third aspect of the present invention, a plurality of voltage sources each generating a different voltage value, and a selection means for selecting one of the plurality of voltage sources and connecting to one of the buffers at each stage. Are provided.

In a semiconductor integrated circuit according to a fourth aspect of the present invention, the plurality of voltage sources are each constituted by a constant current source circuit.

In a semiconductor integrated circuit according to a fifth aspect of the present invention, a plurality of amplifier circuits for selectively generating different delay values are provided in the respective buffers.

In a semiconductor integrated circuit according to a sixth aspect of the present invention, a plurality of amplifier circuits each generating a different voltage value, and a selection means for selecting one of the plurality of amplifier circuits and connecting to one of the buffers at each stage. Are provided.

In a semiconductor integrated circuit according to a seventh aspect of the present invention, a plurality of PLL circuits for selectively generating different delay values are provided in each of the buffers.

In a semiconductor integrated circuit according to an eighth aspect of the present invention, a plurality of PLL circuits each generating a different voltage value, and selecting means for selecting one of the plurality of PLL circuits and connecting to any of the buffers in each of the stages. Are provided.

In a semiconductor integrated circuit according to a ninth aspect of the present invention, a plurality of PLL circuits operating at the same reference clock and having different output frequencies are used as the plurality of PLL circuits.

In the semiconductor integrated circuit according to the tenth aspect,
A plurality of PLL circuits having different reference clocks and output frequencies are used as the plurality of PLL circuits.

In the semiconductor integrated circuit according to the eleventh aspect,
As the plurality of PLL circuits, a plurality of PLL circuits operating with the same reference clock and having different numbers of buffer stages of the voltage controlled oscillation circuit are used.

In the semiconductor integrated circuit according to the twelfth aspect,
As the plurality of PLL circuits, a plurality of PLL circuits having different numbers of buffer stages of a reference clock and a voltage controlled oscillation circuit are used.

In the semiconductor integrated circuit according to the thirteenth aspect,
As the plurality of PLL circuits, a plurality of PLL circuits operating with the same reference clock and having different transistor sizes of the voltage controlled oscillation circuit are used.

In a semiconductor integrated circuit according to a fourteenth aspect,
As the plurality of PLL circuits, a plurality of PLs having different transistor sizes of a reference clock and a voltage controlled oscillation circuit.
This uses an L circuit.

In the semiconductor integrated circuit according to the fifteenth aspect,
Each stage buffer is provided with a plurality of D / A converters for generating different delay values.

In a semiconductor integrated circuit according to a sixteenth aspect,
A plurality of D / A converters each generating a different voltage value, and a selection means for selecting one of the plurality of D / A converters and connecting to one of the buffers in each of the stages are provided.

In a semiconductor integrated circuit according to a seventeenth aspect,
A plurality of D / A converters having different gradations are used as the plurality of D / A converters.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. Figure 1
FIG. 3 is a configuration diagram for supplying a voltage from an amplifier circuit as a voltage source to a buffer of each stage of the VCO according to the first embodiment of the present invention. In the figure, 8 is an output frequency (fo)
out) Output terminal, 11 is a first stage buffer of the VCO, 12 is a second stage buffer, 13 is a third stage buffer, 14 is a fourth stage buffer, and 15 is a fifth stage buffer, and constitutes a VCO. 18, 19, 20, 21, and 22 are buffers 1
PM that controls the delay time of 1, 12, 13, 14, 15
OS transistors, 23, 24, 25, 26, 27
5 shows an NMOS transistor that controls the delay times of the buffers 11, 12, 13, 14, and 15. In this description, VC
O is performed in five stages, and five amplifier circuits are also performed.

As shown in FIG. 1, PMOS transistors 18, 19, 20, 21, and 22 constituting buffers at each stage are provided.
And NMOS transistors 23, 24, 25, 26, 2
7 inputs 28, 29, 30, 31, 32 and 33, 3
4, 35, 36 and 37 are independently controlled by an amplifier circuit (described later) shown in FIG. By independently controlling, the buffers 11, 12, 1 of each stage of the VCO are controlled.
It is characterized in that the voltages supplied to 3, 14, and 15 can be freely varied, and the delay time of each stage can be adjusted arbitrarily.

FIG. 2 is a configuration diagram of a voltage source circuit to be supplied to buffers at each stage of the VCO according to the first embodiment of the present invention. Reference numerals 38, 39, 40, 41, and 42 denote amplifier circuits as voltage sources.
It is a voltage source for supplying a potential to the stage buffer 12, the third stage buffer 13, the fourth stage buffer 14, and the fifth stage buffer 15. 43 denotes each of the voltage sources 38, 39, 40, 4
1 shows a selector (or switch) for arbitrarily selecting any one of 1 and 42.

The voltage source 38 composed of an amplifier circuit includes oscillation PMOS transistors 38a and 38b and an oscillation PM
A voltage source 39 composed of OS transistors 38c and 38d and composed of an amplifier circuit is composed of oscillation PMOS transistors 39a and 39b and oscillation PMOS transistors 39c and 39d. A voltage source 40 composed of an amplifier circuit is composed of an oscillation PMOS transistor. 40a, 40
b and oscillation PMOS transistors 40c and 40d, and a voltage source 41 composed of an amplifier circuit includes oscillation PMOS transistors 41a and 41b and oscillation PMOS transistors 41a and 41b.
The voltage source 42 composed of MOS transistors 41c and 41d and composed of an amplifier circuit is composed of oscillation PMOS transistors 42a and 42b and oscillation PMOS transistors 42c and 42d. Then, voltage sources 38, 39, 40, 41, 4 composed of these amplifier circuits
Numeral 2 is configured to supply a voltage for generating a delay value to each stage buffer of the VCO and, at that time, to function as a constant current source circuit for supplying a constant current.

Here, in the first embodiment, components other than the specific configuration described in the first embodiment have the same overall configuration as the conventional semiconductor integrated circuit shown in FIG. That is, also in the first embodiment, reference frequency (f) similar to that shown in FIG.
in) input terminal 1, phase comparator PC (Phase De)
ector), charge pump CP (Charge)
Pump, low-pass filter LPF (Low Pas)
The s-filter 10 is provided with a frequency divider circuit: DIV2 (1 / M) and a VCO having a specific configuration in place of the VCO: 2 in FIG. These components including the VCO are integrated as a single semiconductor integrated circuit.

VCO buffer 1 shown in FIGS. 1 and 2
1, 12, 13, 14, 15 and the amplifier circuits 38, 39, 40, 41, 42 as the voltage source and the selector 43 constitute a unique VCO as a whole. As described above, the VCO: 2 in FIG. It is provided instead. Amplifier circuits 38, 39, 40, 4 as voltage sources
Oscillating NMOS transistors 38 constituting the first and second transistors 42
The gates of c, 39c, 40c, 41c and 42c are shown in FIG.
7 is connected to receive the output of the low-pass filter LPF. Amplifier circuits 38 and 3 as voltage sources
Reference numerals 9, 40, 41, and 42 output different voltage values due to a difference in input voltage or a difference in circuit characteristics, respectively.
The back gates of the oscillating PMOS transistors 38b, 39b, 40b, 41b, 42b constituting the transistors 39, 40, 41, 42, and the oscillating NMOS transistor 38
The gates of d, 39d, 40d, 41d and 42d are shown in FIG.
As shown in (1), different voltage values for generating different delay values are supplied to the VCO buffers 11, 12, 13, 14, and 15 by the selection operation of the selector 43, respectively. .

FIG. 3 shows the operation of the selector (switch). FIG. 3A is an explanatory diagram showing a terminal arrangement of the selector, and FIG. 3B is an explanatory diagram showing an operation state. FIG. 4 is a connection diagram showing an internal circuit of the selector. In this description, the VCO has five stages, five voltage sources, and each selector (switch) is controlled by a 3-bit signal. Reference numerals 43 denote S0 and S, respectively, based on a 3-bit control signal from the inside of the chip (microcomputer or the like).
1, five voltage sources are arbitrarily selected. Each of the selected voltages is connected to the VCO buffers 11, 12,.
13, 14, and 15 to generate independent delay times. By controlling independently, VC
It is characterized in that the current supplied to the buffers 11, 12, 13, 14, 15 of each stage of O can be freely varied, and the delay time of each stage can be adjusted arbitrarily.

According to this method, each stage buffer 1 of the VCO
The adjustment times of 1, 12, 13, 14, 15 are td1, td
2, td3, td4, td5, the delay time Td of the entire VCO is Td = td1 + td2 + td3 + t
It can be expressed by d4 + td5 (conventionally, Td = td × 5).
Therefore, regardless of the comparison frequency from the input,
Since the remarkable buffer of the VCO generates a different delay time to obtain the delay time Td, an effect that the variable width of the output frequency can be freely changed can be obtained.
In addition, since the potential supplied to the buffer unit at each stage is an arbitrary constant potential, the output of the VCO does not fluctuate, and an effect of stably reducing the output frequency and jitter can be obtained.

According to the first embodiment of the present invention, P
The buffer means provided in the voltage controlled oscillation circuit constituting the LL include a plurality of stages of buffers 11, 12, 13, 14, and 15 capable of selectively generating different delay values, and the plurality of stages of buffers 11, 12,. Amplifier circuit 3 for selectively generating different delay values for each of 13, 14, and 15
A plurality of voltage sources consisting of 8, 39, 40, 41, 42;
A selection unit including a selector 43 for selecting any one of the plurality of voltage sources and connecting to any of the buffers 11, 12, 13, 14, and 15;
Delay values td1, td2 of 1, 12, 13, 14, 15
Since a desired output frequency is obtained by a combination of td3, td4, and td5, the amplifier circuits 38, 3
9, 40, 41, 42, any one of a plurality of voltage sources, and selects each of the buffers 11, 12, 13, 14, 1,
5, a semiconductor integrated circuit having a PLL function capable of realizing a desired output frequency regardless of the phase comparison frequency can be obtained.

According to the first embodiment of the present invention, the plurality of voltage sources including the amplifier circuits 38, 39, 40, 41, and 42 are each constituted by a constant current source circuit. A PLL that can achieve a desired output frequency regardless of the jitter amount and reduce the amount of jitter.
A semiconductor integrated circuit having a function can be obtained.

Embodiment 2 Second Embodiment A second embodiment according to the present invention will be described with reference to FIGS. FIG. 5 is a configuration diagram of a voltage source circuit that supplies a buffer of each stage of the VCO according to the second embodiment of the present invention. FIG. 6 shows a VCO of a PLL for a voltage source according to a second embodiment of the present invention.
FIG. 3 is a configuration diagram showing a buffer provided in the system. 44,4
5, 46, 47 and 48 are PLL (Phase Lock).
ed Loop), and the buffer 1 of each stage of the VCO
1, 12, 13, 14, and 15.
Reference numeral 43 denotes the same selector as in the first embodiment.
Reference numerals 0, 51, 52, 53, and 54 denote frequency divider circuits. The buffers provided in the VCOs of the voltage source PLLs 44, 45, 46, 47, and 48 are each configured as shown in FIG.

Here, the second embodiment has the same overall configuration as that of the first embodiment except for the specific configuration described in the second embodiment. That is, the voltage sources 38, 39, 40, 41, and 4 composed of the amplifier circuits according to the first embodiment shown in FIG.
PLL for voltage source: 44, 45, 46, 4 instead of 2
7, 48 and a frequency dividing circuit 49 are provided. Dividing circuit 4
To 9, a reference clock, that is, a reference frequency input (fin) is input from the reference frequency input terminal 1.

Each frequency dividing circuit 49, 50, 51, 52, 5
Like the selector 43, the selectors 3 and 54 are controlled by independent external signals, and can change the frequency division value. In this description, the VCO has five stages, the PLL is also five, and the selector (switch) is controlled by a 3-bit signal.
The dividing values of the dividing circuits 49, 50, 51, 52, 53, 54 are set to 1 / N, 1 / M1, 1 / M2, 1 / M3, 1 / M
4, 1 / M5. PLL: 44, 45, 46,
47 and 48 operate with the same external reference clock. The frequency dividing circuits 49, 50, 51, 52, 53, 54
The frequency division value is set by an external signal, and the PLL: 4
4, 45, 46, 47, 48 oscillation frequencies,
Output frequency (for PLL: 44, fout1 = fin
/ N × M1) is determined. Similarly, the selector 43 receives three-bit control signals from the outside of the chip (microcomputer or the like) at S0, S1, and S2, respectively, and arbitrarily selects five voltage sources. Each selected voltage is supplied to buffers 11, 12, 13, 14, and 15 of the VCO, so that an independent delay time can be generated. By independently controlling, the buffers 11, 12, 13, and
The present invention is characterized in that the currents supplied to 14 and 15 are freely varied, and the delay time of each stage is arbitrarily adjusted.

According to this method, each stage buffer 1 of the VCO
The delay times of 1, 12, 13, 14, 15 are td1, td
2, td3, td4, td5, the delay time Td of the entire VCO is Td = td, as in the first embodiment.
1 + td2 + td3 + td4 + td5. The same applies to the basic effects.

According to the second embodiment of the present invention, in order to selectively generate different delay values in the buffers 11, 12, 13, 14, and 15, respectively, a plurality of voltages generating different voltage values are used. Source PLL circuits 44, 45, 4
6, 47, 48 and the plurality of PLL circuits 44, 45,
Selecting means comprising a selector 43 for selecting any one of 46, 47 and 48 and connecting to any of the buffers 11, 12, 13, 14 and 15, and a plurality of voltage source PLL circuits 44 , 45,46,47,4
8, a plurality of PLL circuits 44, 45, 46, 47, and 48 operating at the same reference clock and having different output frequencies are used. Therefore, a plurality of PLL circuits 44 and 45 operating at the same reference clock and having different output frequencies are used. , 46,47,48
A semiconductor having a PLL function capable of realizing a desired output frequency irrespective of the phase comparison frequency by selecting any one of a plurality of voltage sources consisting of the following and connecting to each of the buffers 11, 12, 13, 14, and 15: An integrated circuit can be obtained.

Embodiment 3 Third Embodiment A third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a configuration diagram of a voltage source circuit to be supplied to buffers at respective stages of a VCO according to a third embodiment of the present invention. 44, 45, 46, 47,
48 is a PLL (Phase Locked Loop)
And buffers 11, 12, 13, and 1 at each stage of the VCO.
4 and 15 are voltage sources to be supplied. In addition, each PLL
(Phase Detector), C
P (Charge Pump), LPF (Low Pa)
ss Filter) and VCO are the same. 43
Are the same selectors as in the first embodiment.
52, 53, 54, 60, 61, 62, 63, 64
3 shows a frequency dividing circuit. Each of the frequency dividing circuits 50, 51, 52, 53,
54, 60, 61, 62, 63, 64
In the same manner as described above, the frequency division value can be varied by being controlled by independent external signals.

Here, the third embodiment has the same general configuration as that of the first embodiment except for the specific configuration described in the third embodiment. That is, the voltage sources 38, 39, 40, 41, and 4 composed of the amplifier circuits according to the first embodiment shown in FIG.
PLL for voltage source: 44, 45, 46, 4 instead of 2
7, 48 and frequency dividing circuits 60, 61, 62, 63, 64
Is provided.

In the present description, the VCO has five stages, the PLL is also five, and the selector (switch) is controlled by a 3-bit signal.
Frequency dividing circuits 49, 50, 51, 52, 53, 54, 60,
The division values of 61, 62, 63 and 64 are 1 / N1, 1 / N
2,1 / N3,1 / N4,1 / N5,1 / M1,1 / M
2, 1 / M3, 1 / M4, 1 / M5. PL
L: 44, 45, 46, 47, 48 operate by supplying an independent reference clock from outside. Frequency dividing circuit 50,
51, 52, 53, 54, 60, 61, 62, 63, 6
Reference numeral 4 denotes a frequency division value set by an external signal.
L: oscillation frequencies of 44, 45, 46, 47, and 48, that is, output frequencies (for PLL: 44, fout1 =
fin / N1 × M1). Selector 4
3 is also received by S0, S1, and S2, respectively, according to a 3-bit control signal from the outside of the chip (microcomputer or the like).
Select one voltage source. Each selected voltage is VCO
Are supplied to the buffers 11, 12, 13, 14, and 15,
An independent delay time can be generated. By independently controlling, the buffers 11, 1 of each stage of the VCO are controlled.
It is characterized in that the current supplied to 2, 13, 14, 15 can be freely varied, and the delay time of each stage can be adjusted arbitrarily.

According to this method, each buffer 1 of the VCO
The delay times of 1, 12, 13, 14, 15 are td1, td
2, td3, td4, td5, the delay time Td of the entire VCO is Td = td, as in the first embodiment.
1 + td2 + td3 + td4 + td5. The same applies to the basic effects.

According to the third embodiment of the present invention, in order to selectively generate different delay values in the buffers 11, 12, 13, 14 and 15, a plurality of voltages generating different voltage values are used. Source PLL circuits 44, 45, 4
6, 47, 48 and the plurality of PLL circuits 44, 45,
Selecting means comprising a selector 43 for selecting any one of 46, 47 and 48 and connecting to any of the buffers 11, 12, 13, 14 and 15, and a plurality of voltage source PLL circuits 44 , 45,46,47,4
8, a plurality of PLL circuits 44, 45, 46, 47, and 48 having different reference clocks and output frequencies are used.
One of a plurality of voltage sources consisting of L circuits 44, 45, 46, 47, and 48 is selected and the buffers 11, 12,
By connecting them to 13, 14, and 15, a semiconductor integrated circuit having a PLL function that can realize a desired output frequency regardless of the phase comparison frequency can be obtained.

Embodiment 4 FIG. Embodiment 4 of the present invention will be described with reference to FIGS. FIG. 8 is a configuration diagram of a voltage source circuit to be supplied to buffers at each stage of a VCO according to a fourth embodiment of the present invention. 70, 71,
72, 73 and 74 are PLL (Phase Locked)
Loop), and the buffers 11, 1 of each stage of the VCO
2, 13, 14 and 15. Also,
PD (Phase Detect) that constitutes each PLL
tor), CP (Charge Pump), LPF
(Low Pass Filter) is the same. For VCOs 65, 66, 67.68, 69,
The configuration is the same, but the number of stages is different.

FIG. 9 shows a voltage source PLL: 70 and a VCO: 6
5 (VCO1), FIG. 10 shows a voltage source P
FIG. 11 is a block diagram of VCO: 66 (VCO2) of LL: 71, and FIG. 11 is a diagram of VCO: 67 (VCO) of PLL for voltage source: 72.
FIG. 12 is a block diagram of the PLL for the voltage source:
FIG. 13 is a block diagram of the VCO 73 (VCO4) 73, and FIG.
FIG. Reference numeral 43 denotes the same selector as that of the second embodiment, and includes 49, 50, 51, 52, 53,
Reference numeral 54 denotes a frequency dividing circuit. Each frequency dividing circuit 49, 50, 5
1, 52, 53 and 54 are controlled by independent external signals similarly to the selector 43, so that the frequency division value can be varied.

Here, the fourth embodiment has the same general configuration as that of the first embodiment except for the specific configuration described in the fourth embodiment. That is, the voltage sources 38, 39, 40, 41, and 4 composed of the amplifier circuits according to the first embodiment shown in FIG.
PLL for voltage source: 70, 71, 72, 7 instead of 2
3, 74 and a frequency dividing circuit 49 are provided.

In this description, there are five stages of VCOs and five PLLs. The number of stages of VCOs of each PLL is VCO: 44, five stages, VC
O: 45 for 7 stages, VCO: 46 for 9 stages, VCO 47 for 1 stage
One stage, VCO: 48 has 13 stages, and the selector (switch) is controlled by a 3-bit signal.
The division values of 50, 51, 52, 53, and 54 are 1 / N, 1
/ M1, 1 / M2, 1 / M3, 1 / M4, 1 / M5. The PLLs 70, 71, 72, 73 and 74 operate on the same external reference clock. Dividing circuit 4
9, 50, 51, 52, 53, and 54 have frequency division values set by external signals, and PLL: 70, 71, 72,
73, 74, that is, the output frequency (PL
In the case of L: 44, fout1 = fin / N × M1) is determined. Similarly, the selector 43 also receives signals S0, S0 by a 3-bit control signal from the outside of the chip (microcomputer or the like).
1, five voltage sources are arbitrarily selected. Each selected voltage is applied to the VCO buffers 11, 12, 1
3, 14, and 15 to generate an independent delay time.

By using this method, different voltage sources can be generated depending on both the setting of the frequency division ratio of the PLL and the number of VCO stages in the PLL. By independently controlling, the buffers 11, 12, 1 of each stage of the VCO are controlled.
The present invention is characterized in that the current supplied to 3, 14, 15 can be freely varied, and the delay time of each stage can be arbitrarily adjusted. According to this method, each stage buffer 11, 12, 13, 1 of the VCO
The delay times of 4, 15 are td1, td2, td3, td
4, td5, the delay time Td of the entire VCO
Is Td = td1 + td2 + t, as in the first embodiment.
It can be expressed as d3 + td4 + td5. The same applies to the basic effects.

According to the fourth embodiment of the present invention, in order to selectively generate different delay values in the buffers 11, 12, 13, 14, and 15, a plurality of voltages generating different voltage values are used. Source PLL circuits 70, 71, 7
2, 73, 74 and the plurality of PLL circuits 70, 71,
Selecting means comprising a selector 43 for selecting any one of 72, 73 and 74 and connecting to any of the buffers 11, 12, 13, 14 and 15; and providing a plurality of voltage source PLL circuits 70. , 71,72,73,7
4, the voltage-controlled oscillation circuits VCO1: 65, VCO2: 66, VCO3: 67,
Since a plurality of PLL circuits 70, 71, 72, 73, and 74 having different numbers of buffer stages of VCO4: 68 and VCO5: 69 are used, they operate with the same reference clock and operate with the voltage controlled oscillation circuits VCO1: 65, VCO2: 66, and VCO3. : 67,
VCO4: 68, VCO5: 69 Select one of a plurality of voltage sources consisting of a plurality of PLL circuits 70, 71, 72, 73, 74 having different numbers of buffer stages, and select buffers 11, 12, 13, 14, 15 for each stage. By connecting to
A semiconductor integrated circuit having a PLL function that can realize a desired output frequency regardless of the phase comparison frequency can be obtained.

Embodiment 5 Embodiment 5 of the present invention will be described with reference to FIG. FIG. 14 is a configuration diagram of a voltage source circuit to be supplied to buffers at each stage of a VCO according to a fifth embodiment of the present invention. 70, 71, 72, 7
3, 74 are PLL (Phase Locked Loop)
p), and the buffers 11, 12, 1 of each stage of the VCO
3, 14 and 15. Also, a PD (Phase Detecto) constituting each PLL
r), CP (Charge Pump), LPF (Lo
w Pass Filter) is the same. VC
O has the same configuration, but has a different number of stages. Reference numeral 43 denotes the same selector as that of the first embodiment, and is 49, 50, 51, 52, 53, 54, 60, 6
1, 62, 63 and 64 indicate frequency dividing circuits. Each frequency dividing circuit 50, 51, 52, 53, 54, 60, 61, 62, 6
Like the selector 43, the selectors 3 and 64 are controlled by independent external signals, and can change the frequency division value.

Here, the fifth embodiment has the same general configuration as that of the fourth embodiment except for the specific configuration described in the fifth embodiment. That is, the frequency dividing circuits 60, 61, 62, 6
3, 64, and PLL: 70, 71, 72, 7
3, 74 are configured to be operated by different reference clocks.

In this description, there are five stages of VCOs and five PLLs, and the number of stages of the VCOs of each PLL is VCO: 44, five stages, VC
O: 45 for 7 stages, VCO: 46 for 9 stages, VCO 47 for 1 stage
One stage, VCO: 48 has 13 stages, and the selector (switch) is controlled by a 3-bit signal.
51, 52, 53, 54, 60, 61, 62, 63, 6
4 is 1 / N1, 1 / N2, 1 / N3, 1 / N
4,1 / N5,1 / M1,1 / M2,1 / M3,1 / M
4, 1 / M5. PLL: 70, 71, 72,
The reference numerals 73 and 74 operate by supplying an independent reference clock from the outside. Frequency dividing circuits 50, 51, 52, 53, 5
In 4,60,61,62,63,64, the frequency division value is set by an external signal, and PLL: 70, 71, 72,
73, 74, that is, the output frequency (PL
In the case of L: 44, fout1 = fin / N1 × M1) is determined. Similarly, the selector 43 also receives signals S0 and S0 by a 3-bit control signal from the outside of the chip (such as a microcomputer).
Received in S1 and S2, arbitrarily select five voltage sources.
Each selected voltage is applied to the VCO buffers 11, 12,
13, 14, and 15 to generate independent delay times.

By using this method, different voltage sources can be generated depending on both the setting of the frequency division ratio of the PLL and the number of VCO stages in the PLL. By independently controlling, the buffers 11, 12, 1 of each stage of the VCO are controlled.
The present invention is characterized in that the current supplied to 3, 14, 15 can be freely varied, and the delay time of each stage can be arbitrarily adjusted. According to this method, each stage 11, 12, 13, 14, 15 of the VCO
Td1, td2, td3, td4, td5
The delay time Td of the entire VCO is Td = td1 + td2 + td3 + td4, as in the first embodiment.
+ Td5. The same applies to the basic effects.

According to the fifth embodiment of the present invention, in order to selectively generate different delay values in the buffers 11, 12, 13, 14, and 15, a plurality of voltages generating different voltage values are selected. Source PLL circuits 70, 71, 7
2, 73, 74 and the plurality of PLL circuits 70, 71,
Selecting means comprising a selector 43 for selecting any one of 72, 73 and 74 and connecting to any of the buffers 11, 12, 13, 14 and 15; and providing a plurality of voltage source PLL circuits 70. , 71,72,73,7
4, a reference clock and a voltage controlled oscillator circuit VCO
1:65, VCO2: 66, VCO3: 67, VCO
4:68, VCO 5:69 Since a plurality of PLL circuits 70, 71, 72, 73, 74 having different numbers of buffer stages are used, the reference clocks are different, and the voltage controlled oscillation circuit V
CO1: 65, VCO2: 66, VCO3: 67, VC
O4: 68, VCO 5: 69 A plurality of voltage sources including a plurality of PLL circuits 70, 71, 72, 73, and 74 having different numbers of buffer stages are selected, and each stage buffer 1 is selected.
1, 12, 13, 14, and 15, it is possible to obtain a semiconductor integrated circuit having a PLL function capable of realizing a desired output frequency regardless of the phase comparison frequency.

Embodiment 6 FIG. The voltage source circuit to be supplied to the buffer of each stage according to the sixth embodiment of the present invention has the same configuration as that of the fourth embodiment shown in FIG. PD (Phase Detector), CP (Ch) constituting each PLL
arg Pump), LPF (Low Pass F)
ilter) are the same. VCO 65, 66, 6
7.68 and 69 have the same configuration,
It is assumed that the transistor sizes are different.

PLL: 70, 71, 72, 73, 74
Operate on the same external reference clock. In the frequency dividing circuits 49, 50, 51, 52, 53, and 54, the frequency dividing value is set by an external signal, and PLL: 70, 71, 7
2, 73, 74 oscillation frequency, that is, the output frequency (for PLL: 44, fout1 = fin / N × M
1) is determined. Since the PLLs 70, 71, 72, 73, and 74 have different transistor sizes, different oscillation frequencies can be obtained for the same division value setting. Each selected voltage is supplied to buffers 11, 12, 13, 14, and 15 of the VCO, so that an independent delay time can be generated. By this method, the buffers 11, 1 of each stage of the VCO
It is characterized in that the current supplied to 2, 13, 14, 15 can be freely varied, and the delay time of each stage can be adjusted arbitrarily.

According to this method, each stage buffer 1 of the VCO
The delay times of 1, 12, 13, 14, 15 are td1, td
2, td3, td4, td5, the delay time Td of the entire VCO is Td = td, as in the first embodiment.
1 + td2 + td3 + td4 + td5. The same applies to the basic effects.

According to the sixth embodiment of the present invention, in order to selectively generate different delay values in the buffers 11, 12, 13, 14 and 15, a plurality of voltages generating different voltage values are used. Source PLL circuits 70, 71, 7
2, 73, 74 and the plurality of PLL circuits 70, 71,
Selection means for selecting any one of 72, 73, 74 and connecting to any of the buffers at each stage, and providing a plurality of voltage source PLL circuits 70, 71, 72, 73,
At 74, the voltage-controlled oscillation circuits VCO1: 65, VCO2: 66, VCO3: 6 operate with the same reference clock.
7, a plurality of PLL circuits 70, 71, 72, 7 having different transistor sizes of VCO 4: 68 and VCO 5: 69
Since it uses 3,74, it operates with the same reference clock,
Voltage controlled oscillator circuits VCO1: 65, VCO2: 66, V
A plurality of PLL circuits 70, 71 with different transistor sizes of CO3: 67, VCO4: 68, VCO5: 69,
By selecting one of a plurality of voltage sources 72, 73 and 74 and connecting them to the buffers 11, 12, 13, 14, and 15, the desired output frequency can be realized regardless of the phase comparison frequency. A semiconductor integrated circuit having a function can be obtained.

Embodiment 7 FIG. A seventh embodiment according to the present invention will be described. A voltage source circuit to be supplied to each buffer in the seventh embodiment according to the present invention has the same configuration as that of the fifth embodiment shown in FIG. 70,7
1, 72, 73, and 74 are PLL (Phase Lock).
ed Loop), which is a voltage source to be supplied to the buffer of each stage of the VCO. Also, the Ps constituting each PLL
D (Phase Detector), CP (Char
gePump), LPF (Low Pass Filt)
er) are the same. The VCOs have the same configuration, but have different transistor sizes.

PLL: 70, 71, 72, 73, 74
Operates by supplying an independent reference clock from outside. Frequency dividing circuits 50, 51, 52, 53, 54, 60,
61, 62, 63, and 64 have frequency division values set by external signals, and PLLs: 70, 71, 72, 73, and 74.
, Ie, the output frequency (for PLL: 44, fout1 = fin / N1 × M1). Similarly, the selector 43 is also provided outside the chip (such as a microcomputer).
, S1, S1, S1
2 and select five voltage sources arbitrarily. Also, P
Since LL: 70, 71, 72, 73, and 74 have different transistor sizes, different oscillation frequencies can be obtained for the same setting of the frequency dividing chip. Each selected voltage is supplied to buffers 11, 12, 13, 14, and 15 of the VCO, so that an independent delay time can be generated.

According to this method, the current supplied to the buffers 11, 12, 13, 14, 15 of each stage of the VCO is freely varied, and the delay time of each stage is arbitrarily adjusted. By this method, each stage 11, 12, 1 of the VCO
The delay times of 3, 14, and 15 are td1, td2, td3,
When expressed as td4 and td5, the delay time T of the entire VCO
d is Td = td1 + td2 + as in the first embodiment.
It can be expressed as td3 + td4 + td5. The same applies to the basic effects.

According to the seventh embodiment of the present invention, a plurality of voltage source PLs each generating a different voltage value for selectively generating a different delay value in each buffer.
L circuits 70, 71, 72, 73, 74 and the plurality of Ps
Selection means for selecting any one of the LL circuits 70, 71, 72, 73, 74 and connecting to any of the buffers 11, 12, 13, 14, 15, 15; Circuits 70, 71, 72, 73, 7
4, a reference clock and a voltage controlled oscillator circuit VCO
1:65, VCO2: 66, VCO3: 67, VCO
Since the plurality of PLL circuits 70, 71, 72, 73 and 74 having different transistor sizes of 4:68 and VCO 5:69 are used, the reference clock and the voltage controlled oscillator VCO are used.
1:65, VCO2: 66, VCO3: 67, VCO
4:68, VCO 5:69 A plurality of PLL circuits 70, 71, 72, 73, 74 having different transistor sizes are selected from among a plurality of voltage sources, and the buffers 11, 12, 13, 14, 15 of the respective stages are selected. By connecting to
A semiconductor integrated circuit having a PLL function that can realize a desired output frequency regardless of the phase comparison frequency can be obtained.

Embodiment 8 FIG. An eighth embodiment according to the present invention will be described with reference to FIG. FIG. 15 is a configuration diagram of a voltage source circuit to be supplied to buffers at each stage in the VCO according to the eighth embodiment of the present invention. 44, 45, 46,
47 and 48 are DA converters (Digital Ana)
log converter), which is a voltage source to be supplied to the buffer of each stage of the VCO. D with the same gradient
These are A converters, each of which is controlled by an independent external signal and determines the generated voltage.

Here, in the eighth embodiment, the configuration other than the specific configuration described in the eighth embodiment has the same overall configuration as that of the first embodiment.

The VCO of this description has five stages, the number of DA converters is five, and the selector (switch) is controlled by a 3-bit control signal. Similarly, the selector 43 also receives signals S0 and S0 by a 3-bit control signal from the outside of the chip (such as a microcomputer).
Received in S1 and S2, arbitrarily select five voltage sources.
Each selected voltage is applied to the VCO buffers 11, 12,
13, 14, and 15 to generate independent delay times. With this method, the delay time of each buffer 11, 12, 13, 14, 15 of the VCO is set to td.
1, td2, td3, td4, td5, V
The delay time Td of the entire CO is equal to T as in the first embodiment.
d = td1 + td2 + td3 + td4 + td5, and a similar basic effect can be obtained.

According to the eighth embodiment of the present invention, in order to selectively generate different delay values in the buffers 11, 12, 13, 14, and 15, a plurality of Ds generating different voltage values are selected. / A converters 44, 45, 46,
47, 48 and the plurality of D / A converters 44, 4
5, 46, 47, and 48, and a selection unit including a selector 43 connected to one of the buffers 11, 12, 13, 14, and 15. A plurality of D / A converters 4 for generating different delay values for 12, 13, 14, and 15, respectively
4, 45, 46, 47, and 48, and selects one of the plurality of voltage sources,
By connecting the semiconductor integrated circuits 4 and 15, a semiconductor integrated circuit having a PLL function capable of realizing a desired output frequency regardless of the phase comparison frequency can be obtained.

Embodiment 9 Embodiment 9 of the present invention will be described with reference to FIG. FIG. 16 is a configuration diagram of a voltage source circuit to be supplied to the buffer of each stage according to the ninth embodiment of the present invention. 44, 45, 46, 47 and 48 are DA
Converter (Digital Analog conv)
er), which is a voltage source to be supplied to the buffer of each stage of the VCO. The D / A converters have different gradations, and are controlled by independent external signals to determine the gradations. A voltage is generated depending on the gradation.

Here, the ninth embodiment has the same overall configuration as that of the first embodiment described above except for the specific configuration described in the ninth embodiment.

The VCO of this description has five stages, the number of DA converters is five, and the selector (switch) is controlled by a 3-bit control signal. Similarly, the selector 43 also receives signals S0 and S0 by a 3-bit control signal from the outside of the chip (such as a microcomputer).
Received in S1 and S2, arbitrarily select five voltage sources.
Each selected voltage is applied to the VCO buffers 11, 12,
13, 14, and 15 to generate independent delay times.

This method is characterized in that the current supplied to the buffers 11, 12, 13, 14, 15 of each stage of the VCO can be freely varied and the delay time of each stage can be adjusted arbitrarily. By this method, the delay time of each stage of the VCO is set to t
Expressed as d1, td2, td3, td4, td5,
The delay time Td of the entire VCO is the same as in the first embodiment.
Td = td1 + td2 + td3 + td4 + td5. The same applies to the basic effects.

According to the ninth embodiment of the present invention, in order to selectively generate different delay values in the buffers 11, 12, 13, 14, and 15, a plurality of Ds that generate different voltage values are selected. / A converters 44, 45, 46,
47, 48 and the plurality of D / A converters 44, 4
A selector 43 comprising a selector 43 for selecting any one of 5, 46, 47, 48 and connecting to any of the buffers 11, 12, 13, 14, 15;
The plurality of D / A converters 44, 45, 46, 47,
48, a plurality of D / A converters 4 having different gradations
4, 45, 46, 47, and 48, the plurality of D / A converters 44, 45, 46, and 4 having different gradations are used.
By selecting any one of the plurality of voltage sources 7 and 48 and connecting them to the buffers 11, 12, 13, 14, and 15, a PLL function that can realize a desired output frequency regardless of the phase comparison frequency is provided. And a semiconductor integrated circuit having the same.

In the first to ninth embodiments, P
Although an LL, DA converter, and amplifier circuit were used, a control circuit having a plurality of voltage sources was provided.
The present invention can be applied even when connected to a circuit.

The embodiment according to the present invention has the following specific configuration. [1] PLL (Phase Locked Loop)
The oscillation frequency of the phase-locked loop (p: phase-locked loop) generates various output frequencies from the reference frequency by changing the ratio of the frequency dividing circuit. VCO (Vol) in the PLL circuit
stage Controlled Osilato
r: a plurality of voltage source circuits that can be supplied to the buffers at each stage of the voltage controlled oscillator circuit, to generate different delay values for the buffers at each stage, and to provide a delay time having a buffer at each stage. Is a semiconductor integrated circuit that can freely obtain a variable width of the output frequency irrespective of the phase comparison frequency. In addition, since the current source circuits that supply the buffers at each stage of the VCO also have a constant current, the semiconductor integrated circuit can reduce the amount of jitter. [2] As a voltage source circuit used in the above item [1], a plurality of amplifier circuits are used to supply a drive current for buffers in each stage of the VCO. An arbitrary amplifier is selected from a plurality of amplifiers, the delay time of each buffer is determined by the potential, and a variable width of the output frequency can be freely obtained by combining the delay times of all buffers. [3] As the voltage source circuit used in the above item [1], a plurality of PLs operating at the same reference clock and having different output frequencies are used.
L is used to supply the drive current of the buffer in each stage of the VCO. An arbitrary amplifier is selected from a plurality of PLLs, the delay time of each buffer is determined by the potential, and the variable width of the output frequency can be freely obtained by combining the delay times of all buffers. [4] As the voltage source circuit used in the above item [1], a drive current for the buffer of each stage of the VCO is supplied by using a plurality of PLLs having different reference clocks and output frequencies. An arbitrary amplifier is selected from a plurality of PLLs, the delay time of each buffer is determined by the potential, and the variable width of the output frequency can be freely obtained by combining the delay times of all buffers. [5] As the voltage source circuit used in the above item [1], it operates with the same reference clock, and supplies a drive current for the buffer of each stage of the VCO using a plurality of different PLLs of each stage of the VCO. An arbitrary amplifier is selected from a plurality of PLLs, the delay time of each buffer is determined by the potential, and the variable width of the output frequency can be freely obtained by combining the delay times of all buffers. [6] As the voltage source circuit used in the above item [1], a reference clock and a plurality of PLLs in each stage of the VCO are used to supply a drive current of a buffer in each stage of the VCO.
An arbitrary amplifier is selected from a plurality of PLLs, the delay time of each buffer is determined by the potential, and the variable width of the output frequency can be freely obtained by combining the delay times of all buffers. [7] As the voltage source circuit used in the above item [1], a plurality of PLLs that operate with the same reference clock and have different transistor sizes of the VCO are used to supply the drive current of the buffers of each stage of the VCO. An arbitrary amplifier is selected from a plurality of PLLs, the delay time of each buffer is determined by the potential, and the variable width of the output frequency can be freely obtained by combining the delay times of all buffers. [8] As the voltage source circuit used in the above item [1], a reference clock and a plurality of PLLs having different transistor sizes of the VCO are used to supply the drive current of the buffers at each stage of the VCO. An arbitrary amplifier is selected from a plurality of PLLs, the delay time of each buffer is determined by the potential, and the variable width of the output frequency can be freely obtained by combining the delay times of all buffers.

[9] As the voltage source circuit used in the above item [1], a plurality of D / A converters are used to supply the drive current of the buffers of each stage of the VCO. The plurality of D / A converters generate an arbitrary potential according to an external command such as a microcomputer. Arbitrarily select the output of multiple D / A converters,
The delay time of each buffer is determined by the potential, and a variable width of the output frequency can be freely obtained by a combination of the delay times of all the buffers. [10] As the voltage source circuit used in the above item [1], D / A converters having different gradations are used to supply the drive current of the buffers at each stage of the VCO. A plurality of D / A converters having different gradations generate an arbitrary potential according to an external command such as a microcomputer. A semiconductor integrated circuit in which the outputs of a plurality of D / A converters are arbitrarily selected, the delay time of each buffer is determined by the potential, and the variable width of the output frequency can be freely obtained by combining the delay times of all buffers. is there.

[0074]

According to the first aspect of the present invention, a plurality of buffers capable of selectively generating different delay values are provided as buffer means provided in the voltage-controlled oscillation circuit constituting the PLL. Since a desired output frequency is obtained by combining the delay values, a semiconductor integrated circuit having a PLL function capable of realizing a desired output frequency regardless of the phase comparison frequency can be obtained.

According to the second aspect of the present invention, since a plurality of voltage sources for selectively generating different delay values are provided in the respective buffer stages, the plurality of voltage sources can be used regardless of the phase comparison frequency. And a semiconductor integrated circuit that can realize a desired output frequency can be obtained.

According to the third aspect of the present invention, there are provided a plurality of voltage sources each generating a different voltage value, and a selection means for selecting any one of the plurality of voltage sources and connecting to any one of the buffers in each of the stages. Therefore, by selecting the plurality of voltage sources and connecting them to the buffers at each stage, a semiconductor integrated circuit that can realize a desired output frequency regardless of the phase comparison frequency can be obtained.

According to the fourth aspect, since the plurality of voltage sources are each constituted by a constant current source circuit, a desired output frequency can be realized irrespective of the phase comparison frequency, and the amount of jitter can be reduced. An integrated circuit can be obtained.

According to the fifth aspect, a plurality of amplifier circuits for selectively generating different delay values are provided in the respective stage buffers.
A semiconductor integrated circuit capable of realizing a desired output frequency regardless of the phase comparison frequency can be obtained.

According to the sixth aspect, there are provided a plurality of amplifier circuits each generating a different voltage value, and a selection means for selecting any one of the plurality of amplifier circuits and connecting the selected one of the plurality of amplifier circuits to one of the buffers in each of the stages. Therefore, by selecting the plurality of amplifier circuits and connecting them to the buffers at each stage, it is possible to obtain a semiconductor integrated circuit that can realize a desired output frequency regardless of the phase comparison frequency.

According to the seventh aspect of the present invention, a plurality of Ps for selectively generating different delay values in the respective buffers are provided.
Since the LL circuit is provided, by the plurality of PLL circuits,
A semiconductor integrated circuit capable of realizing a desired output frequency regardless of the phase comparison frequency can be obtained.

According to the eighth aspect, there are provided a plurality of PLL circuits each generating a different voltage value, and a selection means for selecting one of the plurality of PLL circuits and connecting to any of the buffers in each of the stages. Therefore, by selecting the plurality of PLL circuits and connecting them to the buffers at each stage, it is possible to obtain a semiconductor integrated circuit that can realize a desired output frequency regardless of the phase comparison frequency.

According to the ninth aspect, since the plurality of PLL circuits which operate with the same reference clock and have different output frequencies are used as the plurality of PLL circuits, the plurality of PLL circuits which operate with the same reference clock and have different output frequencies are used. By using the PLL circuit described above, a semiconductor integrated circuit that can realize a desired output frequency regardless of the phase comparison frequency can be obtained.

According to the tenth aspect, the plurality of PLLs
Since a plurality of PLL circuits having different reference clocks and output frequencies are used as the circuit, a semiconductor integrated circuit capable of realizing a desired output frequency irrespective of the phase comparison frequency is obtained by using a plurality of PLL circuits having different reference clocks and output frequencies. be able to.

According to the eleventh aspect, the plurality of PLLs
Since a plurality of PLL circuits operating with the same reference clock and having different numbers of buffer stages of the voltage controlled oscillator circuit are used, a plurality of PLL circuits operating with the same reference clock and having different numbers of buffer stages of the voltage controlled oscillator circuit are used. By
A semiconductor integrated circuit capable of realizing a desired output frequency regardless of the phase comparison frequency can be obtained.

According to the twelfth aspect, the plurality of PLLs
As a circuit, a plurality of PLL circuits having different numbers of buffer stages of the reference clock and the voltage controlled oscillation circuit are used.

According to the thirteenth aspect, the plurality of PLLs
As a circuit, a plurality of PLL circuits which operate with the same reference clock and have different transistor sizes of the voltage controlled oscillation circuit are used. Therefore, a plurality of PLL circuits which operate with the same reference clock and have different transistor sizes of the voltage controlled oscillation circuit are used. Accordingly, it is possible to obtain a semiconductor integrated circuit that can realize a desired output frequency regardless of the phase comparison frequency.

According to the fourteenth aspect, the plurality of PLLs
Since a plurality of PLL circuits having different transistor sizes of the reference clock and the voltage controlled oscillation circuit are used as the circuit, a desired number of PLL circuits having different transistor sizes of the reference clock and the voltage controlled oscillation circuit can be used regardless of the phase comparison frequency. A semiconductor integrated circuit that can realize an output frequency can be obtained.

According to the fifteenth aspect, since a plurality of D / A converters for generating different delay values are provided in the respective stage buffers, the plurality of D / A converters can be used regardless of the phase comparison frequency. And a semiconductor integrated circuit that can realize a desired output frequency can be obtained.

According to the sixteenth aspect, the plurality of D / A converters each generating a different voltage value, and the plurality of D / A
A selection means for selecting any one of the A / A converters and connecting to any of the respective stage buffers is provided. By selecting any one of the plurality of D / A converters and connecting to the respective stage buffers, A semiconductor integrated circuit that can achieve a desired output frequency regardless of the comparison frequency can be obtained.

According to the seventeenth aspect, the plurality of D / A
Since a plurality of D / A converters having different gradations are used as converters, a semiconductor integrated circuit capable of realizing a desired output frequency regardless of the phase comparison frequency can be obtained by using a plurality of D / A converters having different gradations. it can.

[Brief description of the drawings]

FIG. 1 is a conceptual configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a truth table of a selector (switch) according to a second embodiment of the present invention.

FIG. 4 is a connection diagram showing a circuit configuration of a selector (switch) according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 shows a VCO according to a third embodiment of the present invention.
3 is a connection diagram showing a circuit configuration of FIG.

FIG. 7 is a configuration diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 8 is a configuration diagram of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 9 shows a VCO according to a fifth embodiment of the present invention.
1 is a connection diagram illustrating a circuit configuration of FIG.

FIG. 10 shows a VC according to a fifth embodiment of the present invention.
FIG. 4 is a connection diagram illustrating a circuit configuration of O2.

FIG. 11 shows a VC according to a fifth embodiment of the present invention.
It is a connection diagram which shows the circuit structure of O3.

FIG. 12 is a diagram showing a VC according to a fifth embodiment of the present invention;
It is a connection diagram which shows the circuit structure of O4.

FIG. 13 shows a VC according to a fifth embodiment of the present invention.
It is a connection diagram which shows the circuit structure of O5.

FIG. 14 is a configuration diagram of a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 15 is a configuration diagram of a semiconductor integrated circuit according to a ninth embodiment of the present invention.

FIG. 16 is a configuration diagram of a semiconductor integrated circuit according to a tenth embodiment of the present invention.

FIG. 17 is a configuration diagram of a semiconductor integrated circuit according to the related art.

[Explanation of symbols]

1. Reference frequency (fin) input terminal, PC phase comparator, CP charge pump, LPF low-pass filter, 2 VCO, 3, 4, 5, 6, 7 buffer, 8
Output frequency (fout) output terminal, 9, 10 divider circuit, 11 to 15 buffer, 38 to 42 amplifier circuit,
43 selector, 44 to 48 PLL circuit for voltage source, 4
9 divider circuit, 70-74 PLL circuit for voltage source, 75
~ 91 D / A converter.

Claims (17)

[Claims] 1. A plurality of stages of buffers, each of which can selectively generate a different delay value, are provided as buffer means provided in a voltage-controlled oscillation circuit constituting a PLL, and a desired output is provided by a combination of the delay values of the respective stage buffers. A semiconductor integrated circuit having a PLL function, wherein a frequency is obtained. 2. The semiconductor integrated circuit according to claim 1, wherein a plurality of voltage sources for selectively generating different delay values are provided in the respective stage buffers. 3. A power supply system comprising: a plurality of voltage sources each generating a different voltage value; and selecting means for selecting any one of the plurality of voltage sources and connecting the selected voltage source to one of the buffers in each of the stages. The semiconductor integrated circuit according to claim 2. 4. The semiconductor integrated circuit according to claim 2, wherein each of said plurality of voltage sources is constituted by a constant current source circuit. 5. The semiconductor integrated circuit according to claim 1, wherein a plurality of amplifier circuits for selectively generating different delay values are provided in each of said buffer stages. 6. A plurality of amplifier circuits each generating a different voltage value, and a selection means for selecting one of the plurality of amplifier circuits and connecting the selected one of the plurality of amplifier circuits to one of the buffers in each of the stages. A semiconductor integrated circuit according to claim 5. 7. The semiconductor integrated circuit according to claim 1, wherein a plurality of PLL circuits for selectively generating different delay values are provided in each of said buffer stages. 8. A plurality of PLs each generating a different voltage value
8. The semiconductor integrated circuit according to claim 7, further comprising: an L circuit, and a selection unit that selects any one of the plurality of PLL circuits and connects to one of the buffers in each of the stages. 9. The semiconductor integrated circuit according to claim 7, wherein a plurality of PLL circuits operating at the same reference clock and having different output frequencies are used as the plurality of PLL circuits. 10. The semiconductor integrated circuit according to claim 7, wherein a plurality of PLL circuits having different reference clocks and output frequencies are used as the plurality of PLL circuits. 11. The PLL circuit according to claim 7, wherein a plurality of PLL circuits that operate on the same reference clock and have different numbers of buffer stages of the voltage controlled oscillation circuit are used as the plurality of PLL circuits. Semiconductor integrated circuit. 12. The semiconductor integrated circuit according to claim 7, wherein a plurality of PLL circuits having different numbers of buffer stages of a reference clock and a voltage controlled oscillator are used as the plurality of PLL circuits. 13. The PLL circuit according to claim 7, wherein a plurality of PLL circuits which operate on the same reference clock and have different transistor sizes of the voltage controlled oscillator circuit are used as the plurality of PLL circuits. Semiconductor integrated circuit. 14. The semiconductor integrated circuit according to claim 7, wherein a plurality of PLL circuits having different transistor sizes of a reference clock and a voltage-controlled oscillation circuit are used as the plurality of PLL circuits. 15. The semiconductor integrated circuit according to claim 1, wherein a plurality of D / A converters for generating different delay values are provided in each of said stage buffers. 16. A plurality of Ds each generating a different voltage value.
16. The semiconductor integrated circuit according to claim 15, further comprising: a / A converter; and selecting means for selecting one of the plurality of D / A converters and connecting to one of the buffers at each stage. 17. The method according to claim 17, wherein the plurality of D / A converters are:
17. The semiconductor integrated circuit according to claim 15, wherein a plurality of D / A converters having different gradations are used.