JP2002217308A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate manufacture and to stabilize a characteristic in LSI where DRAM and a logic circuit are mixed/loaded. SOLUTION: In a semiconductor device, a DRAM cell and a logic circuit are formed on a common semiconductor substrate 21. The gate electrode of the DRAM cell, the gate electrode of the logic circuit, the source of the logic circuit and a drain region have similar high melting point metallic silicide 23 structures. Thus, structure is simplified and a manufacture process can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a large semiconductor integrated circuit device in which a DRAM and a logic circuit are embedded (hereinafter referred to as a DRAM / logic embedded LSI).

[0002]

2. Description of the Related Art In recent years, there has been an increasing need for devices capable of performing graphics processing at high speed.
DRAM / logic embedded L that can increase the bus width of memory and logic circuits, that is, the number of signal lines, for speeding up
The speeding up of SI is also being promoted by downsizing. D
In order to increase the speed of the DRAM and the logic circuit in a RAM / logic mixed LSI, DRA
M and an insulated gate field effect transistor (MIS (Mtal-Insulator-Semiconducto
r) It is necessary to reduce the resistance of the gate electrode of the transistor) and the resistance of the source and drain regions of the logic circuit.

Therefore, in the DRAM and the logic circuit portion, both the gate electrode of the MIS transistor and a metal silicide made of a refractory metal with respect to a polycrystalline or amorphous silicon semiconductor layer into which impurities are introduced are formed in a self-aligned manner. What is called a salicide structure is desired.

In a logic circuit, each n-channel MIS transistor and p-channel MIS forming a CMIS (complementary insulated gate field effect transistor) are formed in order to reduce power consumption during standby.
It is desired that the above-described silicon semiconductor layer forming each gate electrode of the transistor have a so-called dual gate structure in which impurities of different conductivity types of n-type and p-type are respectively introduced.

As described above, in the logic circuit, since the resistance of the source and drain regions must be reduced, a salicide structure is used for the contact portions of the electrodes or wirings to these source and drain regions. However, in a DRAM, such a salicide structure is avoided in order to reduce the leakage current in the source and drain regions in order to secure a memory retention time.

As described above, both the gate electrodes of the transistors of the DRAM and the logic circuit and the source and drain regions of the logic circuit have a salicide structure made of metal silicide, and the CMIS of the logic circuit has a dual gate structure. As a method of manufacturing the embedded LSI, there is the following method. This manufacturing method will be described with reference to FIGS. 11 to 13 are schematic cross-sectional views of main parts of respective components of a DRAM cell and a logic circuit in each manufacturing process.

As shown in FIG. 11A, a semiconductor substrate 1 comprising, for example, at least one principal surface made of a silicon semiconductor, which constitutes a DRAM / logic embedded LSI, is prepared.
Formed portions of circuit elements to be electrically separated from each other are separated by a separation insulating layer 2. This isolation insulating layer 2 can be made of, for example, LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation).
lation).

Then, a gate insulating film 3 of SiO ₂ is formed on the surface of the semiconductor substrate 1 by thermal oxidation, and a silicon semiconductor layer 4 made of polycrystalline or amorphous silicon is entirely formed thereon. Finally, the silicon semiconductor layer 4 is covered with an ion implantation mask (not shown) made of, for example, a photoresist layer, on one side of a DRAM and a logic circuit, for example, a gate forming portion of an n-channel MIS transistor of one conductivity type. A p-type impurity is selectively ion-implanted into a gate formation portion of another conductivity type, for example, a p-channel MIS transistor of the logic circuit to form, for example, a p-type first region 4p having a reduced resistance. Next, the ion implantation mask is removed, and an ion implantation mask (not shown) made of, for example, a photoresist layer is formed so as to cover the first region 4p. An n-type impurity is ion-implanted into a gate formation portion of the MIS transistor to form a second region 4n having reduced resistance.

[0009] Thereafter, as shown in FIG. 11B, the refractory metal silicide layer 5 is entirely formed on the silicon semiconductor layer 4.
Is formed by a CVD (Chemical Vapor Deposition) method or the like.

As shown in FIG. 12A, a logic circuit is formed by the p-type first region 4p by performing pattern etching to a depth across the metal silicide layer 5 and the silicon semiconductor layer 4 over the entire thickness. The gate electrode 7p of the p-channel MIS transistor is formed, and the n-type second region 4n is formed.
To form a gate electrode 7n of each n-channel MIS transistor forming a logic circuit and a DRAM.

Next, although not shown, an opening is formed to entirely cover one conductive type, for example, an n-type MIS transistor, and expose the other conductive type, for example, a p-type MIS transistor. A resist pattern serving as an ion implantation mask is formed. Using this resist pattern and the gate electrode 7p in the opening as a mask,
P-type impurities of the same conductivity type as the gate electrode 7 serving as the mask are ion-implanted to form p-type low impurity concentration source and drain extension regions (hereinafter referred to as S / D regions) 8p.

Next, contrary to the above, although not shown, an opening for covering the above-mentioned p-type MIS transistor forming portion and exposing the other n-type MIS transistor forming portion to the outside is provided. A resist pattern serving as an ion implantation mask is formed. Using this resist pattern and the gate electrode 7 in the opening as a mask, an n-type impurity of the same conductivity type as that of the gate electrode 7n serving as the mask is ion-implanted to form an n-type low impurity concentration S / D region 8n. To form

Thereafter, an insulating layer 9 made of, for example, SiO ₂ shown in FIG. 12B is once formed entirely, not shown, and an etching resist (not shown) is formed on the insulating layer 9.
To form This etching resist is formed by photolithography using a photoresist so as to cover the formation portion of the DRAM and to expose the formation portion of the logic circuit to the outside. Then, a portion exposed to the outside without being covered by the etching resist is etched to a required thickness by anisotropic etching such as RIE (reactive ion etching), as shown in FIG. 12B.
In the formation portion of the logic circuit, the S / D region is exposed to the outside, and at the same time, the sidewall 1 is formed on the side surface of the gate electrode 7.
0 is formed. Thus, the formation part of the DRAM is
S / D region 8 of the logic circuit covered by insulating layer 9
n is exposed to the outside.

In this state, although not shown, an ion implantation mask made of, for example, a photoresist is formed to cover one conductive type transistor of the CMIS transistor, for example, a p-channel transistor in the logic circuit forming portion, and the mask is used. Using the n-type gate electrode 7 and the sidewall 10 as a mask, an n-type impurity is ion-implanted into the uncovered portion of the n-channel MIS transistor where the S / D region 11 has a high impurity concentration.
forming n. Thus, S / D region 12n is formed by both S / D regions 8n and 11n.

Next, although not shown, the above-mentioned C
An ion implantation mask of photoresist is formed to cover the other n-channel transistor forming part of the MIS transistor, and the p-type gate electrode 7 and the p-type gate electrode 7 are formed in the p-channel MIS transistor forming part not covered by this mask. Using the side wall 10 as a mask,
A p-type impurity is ion-implanted to form a high impurity concentration S / D region 11p, and the S / D regions 11p and 11p
The D region 12p is formed.

Thereafter, the ion implantation mask is removed and FIG.
As shown in FIG. 3A, a high-melting-point metal layer 13 capable of forming a metal silicide is formed on the entire surface, and a heat treatment for silicidation is performed. In this manner, a metal silicide layer 14 which is silicided only in a region directly in contact with silicon, that is, only in the S / D regions 12n and 12p of the logic circuit is formed. After that, the high melting point metal layer 13 left without being silicided is removed by etching.

In this way, as described above, DR
Metal silicide is formed on both gate electrodes 7n and 7p of the transistors of the AM and logic circuits and the source and drain regions 12p and 12n of the logic circuit to form a salicide structure.
A DRAM / logic mixed LSI in which S has a dual gate structure can be obtained.

[0018]

However, according to this method, the silicide layer 5 in the gate electrode is not used.
And the metal silicide layer 14 for the S / D regions 12p and 12n of the logic circuit are formed in separate steps, so that the manufacturing process is extremely complicated, requires a long time for manufacturing, and increases the cost. There is a problem. You.

As described with reference to FIG. 11B, since impurities are introduced into the semiconductor layer 3 constituting the gate electrode by ion implantation at an early stage, particularly, for example, the gate electrode of a p-channel MIS transistor is When the impurity to be implanted into the p-type first region 4p is, for example, boron or the like having a large diffusion coefficient, many heat treatments such as activation of the implanted impurity to form each S / D region after the boron implantation are performed. , The impurities such as boron are redistributed, for example, diffused into the active region through the thin gate insulating film 3 to change the characteristics. Also, although not shown in the above-described dual gate structure, an extension of the gate electrode (wiring When the two gates are connected to each other at the connection portion, mutual diffusion of impurities occurs at the connection portion, and the effect on the work function of the electrode is caused. Is a problem that caused the impact of the Njisuta characteristics.

According to the present invention, a semiconductor device capable of simplifying a manufacturing method and further stabilizing characteristics, in particular,
An object of the present invention is to provide an integrated LSI of a DRAM and a logic circuit and a method of manufacturing the same.

[0021]

That is, the present invention relates to a semiconductor device having a DRAM cell and a logic circuit formed on a common semiconductor substrate, wherein the gate electrode of the DRAM cell and the gate of the logic circuit are provided. Both the electrode and the source and drain regions of the logic circuit have the same refractory metal silicide structure.

Further, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a DRAM cell and a logic circuit are formed on a common semiconductor substrate, wherein a silicon semiconductor layer is formed on the semiconductor substrate. Forming a gate electrode of a DRAM by using the silicon semiconductor layer;
A patterning step of simultaneously forming a gate electrode of a logic circuit, a step of forming a first insulating layer entirely on a DRAM forming portion and a logic circuit forming portion, and forming the first insulating layer on the DRAM. A patterning step of excluding on the gate electrode of the DRAM, on the gate electrode of the logic circuit, and on the source and drain regions of the logic circuit, and over the formation portions of the DRAM and the logic circuit. Forming a metal layer constituting silicide by reaction with silicon, and forming a metal salicide on each gate electrode of the DRAM and the logic circuit and on the source and drain regions of the logic circuit by the reaction with the metal layer. The target semiconductor device is obtained by performing the steps of forming simultaneously.

As mentioned above, the DRAM according to the present invention
In the logic-mixed LSI semiconductor device, the metal silicide in the gate and the metal silicide in the S / D region in the logic circuit have the same configuration,
This simplifies the configuration.

Further, in the manufacturing method of the present invention, by employing the above-described structure of the present invention, metal silicide in the gate electrode and metal salicide for the S / D region in the logic circuit are simultaneously performed.
By doing so, the number of manufacturing steps is reduced.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic configuration of the present invention is shown in FIG.
A description will be given with reference to a schematic cross-sectional view of a main part of a surface portion of a semiconductor substrate 21 in which at least a surface portion on which an AM / logic embedded LSI semiconductor device is formed has a Si semiconductor layer. In the device of the present invention, as shown in FIG. 1B, a gate electrode 2 in a region I of a DRAM cell forming portion and a region II of a logic circuit forming portion is formed on a common semiconductor substrate 21.
2, that is, the word line, the logic gate, and the source and drain regions (S / D regions) (not shown) of the logic circuit both have the same refractory metal silicide layer 23.

In the method of manufacturing a semiconductor device according to the present invention, a silicon semiconductor layer constituting a gate electrode 22 is formed on a common semiconductor substrate 21 with a gate insulating film 24 interposed therebetween. Then, with this silicon semiconductor layer, the gate electrode 22 of the DRAM and the gate electrode 22 of the logic circuit are simultaneously formed by the same patterning process. Thereafter, the formation portion of the DRAM, that is, the region I
And a logic circuit forming portion, that is, region II, a first insulating layer 31 is formed on the entire surface, and this first insulating layer 31 is formed on the DRAM in region I as shown in FIG. 1A.
On the source and drain region formation areas,
Exclusions are made on the gate electrode 22 of the DRAM, on the gate electrode 22 of the logic circuit in the region II, and on the portion where the source and drain regions of the logic circuit are formed.

Then, a step of forming a metal layer constituting silicide by reaction with silicon, and a step of forming a metal layer constituting silicide entirely over the portion where the DRAM and the logic circuit are to be formed and the gate electrode 22 are covered, The metal silicide layer 2 is formed on the gate electrode and the surface of the source and drain regions of the logic circuit by reacting the layer with silicon.
3 are simultaneously formed.

Next, first to third embodiments of the present invention will be described.
Each example of the embodiment will be described. In this example, D
Although the case where the MIS transistor of the RAM is an n-channel MIS transistor and a CMIS transistor is formed in the logic circuit portion is illustrated, the present invention is not limited to these embodiments and examples.

[First Embodiment] A description will be given with reference to FIGS. As shown in FIG. 2A, for example, a semiconductor substrate 21 having, for example, at least one main surface made of a silicon semiconductor which constitutes a DRAM / logic mixed LSI is prepared, and a portion between circuit elements to be electrically separated from each other is formed. It is separated by the separation insulating layer 25. This isolation insulating layer 25 is made of, for example, LOCO as described with reference to FIG.
It is formed by S or STI.

A gate insulating film 24 made of SiO ₂ is formed on the surface of the semiconductor substrate 21 by thermal oxidation, and is entirely doped with impurities, that is, an intrinsic (i-type) polycrystal. Alternatively, the silicon semiconductor layer 27 made of amorphous silicon is formed by, for example, a CVD method. Thereafter, in the present invention, in the portion of the semiconductor layer 27 where the p-channel MIS transistor of the CMIS is formed, doping of impurities is not performed.
An n-type impurity, for example, phosphorus (P) is added to the formation portion of each n-channel MIS transistor of the DRAM and the logic circuit.
Is ion-implanted at a dose of, for example, 10 ¹⁵ cm ⁻² to be n-type.

As described above, pattern etching by photolithography using a photoresist is performed on the silicon semiconductor layer 27 having portions where impurities are doped and portions where impurities are not doped, as shown in FIG. 2B. The gate electrode 22n of each n-channel MIS transistor of the DRAM and the logic circuit and the intrinsic gate electrode 22 finally forming the gate electrode of the p-channel MIS transistor are simultaneously formed. These gate electrodes 22n
And 22 are oxidized to form a thin oxide film if necessary.

Then, one conductivity type, for example, p-channel M
The formation portion of the IS transistor is covered with a photoresist (not shown) formed by photolithography, and this is used as an ion implantation mask, and the gate electrode 22 is formed in the other formation portion of the n-channel MIS transistor, for example.
Using the n and the isolation insulating layer 25 as a mask, an n-type impurity, for example, arsenic (As) is ion-implanted at a dose of about 10 ¹⁴ cm ^-2 to form an n-type low-concentration source region and a drain region (S / D (Region) 26n is formed.

Next, the above-described ion implantation mask is removed, and the other conductive type, for example, the formation portion of the n-channel MIS transistor is covered with a photoresist (not shown) formed by photolithography.
Using the gate electrode 22 and the isolation insulating layer 25 as a mask, a p-type impurity such as boron (B) is ion-implanted at a dose of about 10 ¹³ cm ⁻² into a portion where the S-transistor is to be formed, so that the p-type Source and drain regions (S /
D region) 26p is formed.

A heat treatment for activating these ion-implanted impurities and for eliminating or reducing crystal defects is performed, for example, by one step.
Heat treatment is performed at 000 ° C. for 1 second.

As shown in FIG. 3A, a first insulating layer 31 made of, for example, SiN is entirely formed on the semiconductor substrate 21 on which the gate electrodes 22 are formed by LP-CVD (low-pressure chemical vapor deposition). It is formed by a method. In addition, this first
A second insulating layer 32 made of, for example, SiO ₂ is formed on the entire surface of the insulating layer 31 by HDP-CVD (high-density plasma chemical vapor deposition).

As shown in FIG. 3B, the second insulating layer 3
2 is etched back from its surface. For example, CMP
(Chemical mechanical polishing) is performed to planarize the second insulating layer 32 and expose the first insulating layer 31 on the gate electrode 22.

As shown in FIG. 4A, the formation portion of the DRAM is covered with an etching resist 35 made of a photoresist formed by photolithography, for example.
The second insulating layer 32 in the part where the logic circuit is formed is removed by etching.

As shown in FIG. 4B, the etching resist 35 is removed, and anisotropic etching is performed to remove the first insulating layer 31 on each of the gate electrodes 22n and 22 not covered by the second insulating layer 32. At the same time as removing
An opening 29 from which the first insulating layer has been removed is formed on the S / D region 26n and the S / D region 26p. At this time, since the first insulating layer 31 formed along the side surface of the gate electrode 22 of the logic circuit has a large thickness in the direction perpendicular to the substrate surface of the substrate 21, The first insulating layer 31 is left on the side surfaces of the gate electrodes 22n and 22 in the logic circuit forming portion by appropriately selecting the amount of etching by etching having etching anisotropy in the vertical direction. Side wall 2
8 is formed.

Thereafter, as shown in FIG. 5A, the formation portion of the p-channel MIS transistor in the formation portion of the logic circuit is covered with an ion implantation mask 30 made of a photoresist by photolithography, for example, and the n-type S An n-type impurity such as arsenic (As) is ion-implanted into the / D region 26n at a high concentration of, for example, about 10 ¹⁵ cm ^-2, and a high-concentration S / A so-called LDD type n-type S / D region 36n in which a D region is formed is formed.

Next, as shown in FIG. 5B, the ion implantation mask 30 in FIG. 5A is removed, and the formation portion of the n-channel MIS transistor is similarly covered with an ion implantation mask 40 made of a photoresist by photolithography, for example. Through a gate electrode 22 in a portion where a p-channel MIS transistor is formed and openings 29 on both sides of the gate electrode 22, a p-type impurity such as boron (B) is doped at 10 ¹⁵ cm ^−2.
The gate electrode 22 is turned into a p-type gate electrode 22p by ion implantation at a high concentration to the extent that a high concentration S / D region is formed outside the gate side on both sides while leaving a low concentration region on the gate side, that is, a so-called LDD. P-type S / D region 36
Form p.

As shown in FIG. 6A, the ion implantation mask 40 shown in FIG. 5B is removed, and if necessary, a thin oxide film on the surface of the gate electrode is etched to form the gate electrodes 22n and 22n.
At the same time as exposing 2p to the outside, the S / D regions 36n and 36p in the logic circuit are exposed to the outside through the opening 29, and in this state, a metal layer 33 made of, for example, Co, which can form a high melting point metal silicide, is formed by, for example, sputtering. The entire surface is formed.

Thereafter, a heat treatment for silicidation is performed. In this way, for example, Co at the contact portions between the metal layer 33 and silicon, that is, the gate electrodes 22n and 22p, and the S / D regions 36n and 36p of the logic circuit.
A silicide layer 34 (that is, a salicide layer) whose resistance is reduced by silicide is formed. Thereafter, the unreacted portion of the metal layer 33 that has not been silicided is removed by etching.

Thus, in the region I of the common semiconductor substrate 1, the salicide layer 3
4 is formed, but in the S / D region 26n, an n-channel MIS transistor of a circuit element constituting the DRAM in which the salicide layer 34 is not formed is formed.
, N-channel and p-channel MIS transistors each having a dual gate structure as circuit elements of a logic circuit in which the salicide layer 34 is formed on the gate electrodes 22n and 22p and the respective S / D regions 36n and 36p are formed. Thus, the semiconductor device according to the present invention is configured.

[Second Embodiment] In this embodiment, a photoresist is used to form a sidewall for an MIS transistor of a logic circuit, and the S / D
The salicide structure is formed in a limited area. An example of this embodiment will be described with reference to FIGS. Also in this example, as shown in FIG. 7A, a DRAM is formed by the same method as that described in FIGS. 2A and 2B and FIGS. 3A and 3B of the example in the first embodiment.
And n-type S / D regions 2 of low impurity concentration in portions where n-channel MIS transistors of the logic circuit are formed.
6n is formed, and a gate electrode 22n in which a silicon semiconductor layer is doped with a high concentration of n-type impurity is formed at a gate portion of the silicon semiconductor layer via a gate insulating film 24. Similarly, a formation portion of a p-channel MIS transistor of a logic circuit is formed. A p-type S / D region 26p having a low impurity concentration is formed, and a gate electrode 22 made of a non-doped silicon semiconductor layer is formed at a gate portion thereof with a gate insulating film 24 interposed therebetween.

In FIG. 7A, portions corresponding to those in FIG. 3A are denoted by the same reference numerals, and repeated description is omitted. In this embodiment, however, the first insulating layer 31 made of SiN formed entirely by CVD, for example, is used. A resist pattern 50 serving as an etching mask using a photoresist is formed by a well-known technique in the upper portion of the DRAM forming portion except on the gate electrode 22n, that is, in the concave portion where the gate electrode 22n does not exist.

Then, as shown in FIG. 7B, using the resist pattern 50 as an etching mask, the first insulating layer 31 on each of the gate electrodes 22n and 22 not covered by the resist pattern 50 is anisotropically etched.
And at the same time, the S / D regions 26n and S
Opening 29 from which the first insulating layer is removed on / D region 26p
To form At this time, the first insulating layer 31 formed along the side surface of the gate electrode 22 of the logic circuit
Since the thickness of the substrate 21 in the direction perpendicular to the substrate surface is large, the etching amount is appropriately selected by etching having etching anisotropy in the direction perpendicular to the substrate surface. The first insulating layer 31 is provided on the side surfaces of the gate electrodes 22n and 22 in the logic circuit forming portion.
Remain to form sidewalls 28.

Thereafter, as shown in FIG. 8A, the formation portion of the p-channel MIS transistor of the logic circuit is covered with an ion implantation mask 30 made of a photoresist by photolithography, for example, and n
N-type impurities, for example, arsenic As
Is implanted at a high concentration of, for example, about 10 ¹⁵ cm ^-2, and a high concentration S / D region is formed outside the low concentration region on the gate side, that is, a so-called LDD type n.
Form a type S / D region 36n.

Next, as shown in FIG. 8B, the ion implantation mask 30 in FIG. 8A is removed, and the portion where the n-channel MIS transistor is formed is similarly covered with an ion implantation mask 40 made of a photoresist by photolithography. Through a gate electrode 22 in a portion where a p-channel MIS transistor is formed and openings 29 on both sides of the gate electrode 22, a p-type impurity such as boron (B) is doped at 10 ¹⁵ cm ^−2.
The gate electrode 22 is turned into a p-type gate electrode 22p by ion implantation at a high concentration to the extent that a high concentration S / D region is formed outside the gate side on both sides while leaving a low concentration region on the gate side, that is, a so-called LDD. P-type S / D region 36
Form p.

As shown in FIG. 9A, the ion implantation mask 4
0 is removed, and if necessary, the thin oxide film on the gate electrode surface is etched to expose the gate electrodes 22n and 22p to the outside, and at the same time to expose the S / D regions 36n and 36p in the logic circuit to the outside through the opening 29. ,
In this state, a metal layer 33 of, for example, Co, which can constitute a high-melting metal silicide, is entirely formed by, for example, sputtering.

Thereafter, a heat treatment for silicidation is performed. In this way, for example, Co at the contact portions between the metal layer 33 and silicon, that is, the gate electrodes 22n and 22p, and the S / D regions 36n and 36p of the logic circuit.
A silicide layer 34 (that is, a salicide layer) whose resistance is reduced by silicide is formed. Thereafter, the unreacted portion of the metal layer 33 that has not been silicided is removed by etching.

Thus, in the region I of the common semiconductor substrate 1, the salicide layer 3 is formed in the gate electrode 22n.
4 is formed, but in the S / D region 26n, an n-channel MIS transistor of a circuit element constituting the DRAM in which the salicide layer 34 is not formed is formed.
, N-channel and p-channel MIS transistors each having a dual gate structure as circuit elements of a logic circuit in which the salicide layer 34 is formed on the gate electrodes 22n and 22p and the respective S / D regions 36n and 36p are formed. Thus, the semiconductor device according to the present invention is configured.

According to the second embodiment, the manufacturing process is further simplified as compared with the first embodiment.

[Third Embodiment] In this embodiment, the second insulating layer 32 of the first and second embodiments is used.
Alternatively, the formation of the resist pattern 50 is avoided and only the first insulating layer 31 is formed to further simplify the manufacturing. FIG. 10 shows a schematic process drawing of an example of this embodiment. In FIG. 10, the semiconductor substrate 2
1 is a cross-sectional view of a main portion of only the surface portion 1 and is not shown, but in this case also, by the same method as described in FIGS. 2A and 2B and FIGS. 3A and 3B of the first embodiment. , N-type MIS transistors of the DRAM and the logic circuit shown in FIGS. 2A and 2B and FIGS. 3A and 3B, respectively.
/ D region 26n is formed, a gate electrode 22n in which a silicon semiconductor layer is doped with a high-concentration n-type impurity is formed via a gate insulating film 24 in a gate portion thereof, and a p-channel MIS transistor forming portion of a logic circuit is formed. Similarly, a p-type S / D region 26p having a low impurity concentration is formed, and a gate electrode 22 made of a non-doped silicon semiconductor layer is formed at a gate portion thereof with a gate insulating film 24 interposed therebetween.

Then, as shown in FIG. 10A, a first insulating layer 31 made of, for example, SiN is formed on the entire surface by CVD, and the first insulating layer 31 As schematically shown by arrows from oblique directions, ions such as argon (Ar) or phosphorus (P) are implanted, and the damaged region 31d is implanted or irradiated by the ion implantation or irradiation. Is selectively formed over the entire surface of the formation portion. The angle of incidence θ of the ion implantation with respect to the normal direction to the substrate surface of the substrate 21 is ± 30 ° or more, for example, 45 °. For example, at the gate electrode 22n in the DRAM forming portion, that is, at the word line, these are relatively close to each other. And the logic gates of the logic circuit can be formed at relatively wide intervals. Therefore, in the DRAM forming portion, the shadowed portion on both sides of the gate electrode 22n, that is, the S / D region (FIG. Above (not shown), the region 31a which is hardly damaged is left by the fact that the ion implantation is not performed or hardly performed.

The first insulating layer 31 is subjected to anisotropic etching. This etching is performed in the damaged region 31d.
Is performed by anisotropic etching which shows a high etching rate and a low etching rate for the region 31a which is not damaged or not much damaged. In this way, as shown in FIG. 10B, a sidewall 28 is formed on each of the gate electrodes 22n and 22, and an opening 29 from which the insulating layer 31 has been removed is formed on the S / D region in the logic circuit formation portion.

Thereafter, although not shown, FIGS.
By performing the same steps as those described in the above, high-concentration ion implantation of n-type impurities is performed on each of the source region and the drain region of the n-channel MIS transistor of the logic circuit.
A p-type impurity is formed in the gate electrode 2
2 and both sides thereof are ion-implanted at a high concentration to form a p-type gate electrode 22p and a p-type high-concentration S / D region. Thereafter, a metal layer for forming a metal silicide is entirely formed, a silicidation treatment by heat treatment is performed, and an unreacted portion of the metal layer is removed by etching. As shown in FIG. 10C, the metal silicide (salicide) is formed. The layer 23 is formed. In this manner, similarly to each of the above-described embodiments, a semiconductor device in which a MIS transistor (not shown) of a DRAM and a CMIS transistor (not shown) formed by a dual gate electrode of a logic circuit are formed. it can.

In the above-described example, the case where the metal layer 33 constituting the metal silicide (salicide) layer 23 is Co has been described.
It can also be constituted by any one or more metals of o, W and Pt.

In each of the above examples, the DRAM
First insulating layer 3 on S / D region of MIS transistor
In the above-described examples, various modifications may be made. For example, a mask for high-concentration ion implantation may be left as a mask for high-concentration ion implantation while 1 is left in the entire thickness. Changes can be made.

As described above, in the device of the present invention and the method of the present invention, since the silicide layer is simultaneously formed on the gate electrode in the DRAM, the gate electrode in the logic circuit, and the S / D region, the manufacturing can be simplified. It is something that can be done. Further, in spite of the dual gate structure of the CMIS in the logic circuit, with respect to one conductivity type, for example, a p-type gate electrode, doping of the gate electrode is performed simultaneously with formation of the high concentration S / D region of the p-channel MIS transistor. Therefore, the manufacturing process is simplified.

[0060]

As described above, according to the present invention, the manufacturing process can be simplified. However, in the case of a dual gate structure, for example, the semiconductor constituting the p-type gate electrode is formed. Even when the p-type dopant in the layer is, for example, phosphorus P having a large diffusion coefficient, this impurity doping is performed, for example, after the heat treatment for activating the impurity forming the S / D region of the n-channel MIS transistor. Since the process is performed in the final stage, fluctuation of threshold voltage, non-uniformity, and reliability due to diffusion of impurities into the active region of the gate portion as in the conventional method described at the beginning accompanying the heat treatment are performed. The drop can be avoided.

Further, in the dual gate structure, the diffusion of, for example, boron (B) can be reduced in the connection (junction) between the gate electrode of the n-type and p-type semiconductor layers or the extension thereof, and Variations in characteristics can be improved. At the same time, it is possible to further reduce the design rule reduction limit.

As described above, since the mutual influence of each gate can be avoided, the impurity concentration of the gate in the DRAM, that is, the word line and the logic gate in the logic circuit can be set sufficiently high, so that the gate depletion can be sufficiently performed. Can be suppressed. Further, since the influence of the heating temperature can be reduced, the degree of freedom in selecting a heat treatment for further improving characteristics can be increased.

As described above, according to the present invention, the number of manufacturing steps can be simplified, the characteristics can be stabilized, and the reliability can be improved. Therefore, the yield, the mass productivity, and the cost can be reduced. The cost can be reduced, and the industrial profit is enormous.

[Brief description of the drawings]

1A and 1B are explanatory diagrams of a basic configuration of a manufacturing method according to the present invention for obtaining a semiconductor device according to the present invention.

FIGS. 2A and 2B are process diagrams (part 1) of an example of the production method of the present invention.

FIGS. 3A and 3B are process diagrams (part 2) of an example of the production method of the present invention.

FIGS. 4A and B are process diagrams (part 3) of an example of the production method of the present invention.

FIGS. 5A and 5B are process diagrams (part 4) of an example of the production method of the present invention.

6A and 6B are process diagrams (part 5) of an example of the production method of the present invention.

FIGS. 7A and 7B are process diagrams (part 1) of another example of the production method of the present invention.

FIGS. 8A and 8B are process diagrams (part 2) of another example of the production method of the present invention.

FIGS. 9A and 9B are process diagrams (part 3) of another example of the production method of the present invention.

FIGS. 10A to 10C are process diagrams of still another example of the production method of the present invention.

11A and 11B are process diagrams (part 1) of another example of the conventional manufacturing method.

12A and 12B are process diagrams (part 2) of another example of the conventional manufacturing method.

13A and 13B are process diagrams (part 3) of another example of the conventional manufacturing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Separation insulating layer, 3 ... Gate insulating film, 4 ... Silicon semiconductor layer, 4p ...
1st region, 4n ... 2nd region, 5 ... metal silicide layer, 7 ... gate electrode, 8p, 8n ... S /
D region, 9: insulating layer, 10: sidewall,
11n, 11p: High impurity introduction region, 12n, 12
p: S / D region of a logic circuit, 13: refractory metal layer, 14: metal silicide layer, 21: semiconductor substrate, 22, 22n, 22p: gate electrode, 2
3 ... metal silicide layer, 24 ... gate insulating film,
25 ... isolation insulating layer, 26n, 26p ... S / D region, 27 ... silicon semiconductor layer, 28 ... sidewall, 29 ... opening, 30, 40 ... ion implantation mask, 31: first insulating layer, 31d: damaged area, 32: second insulating layer, 33: metal layer,
34: silicide layer, 35: etching resist

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/10 461 H01L 27/10 681F 27/108 21/8242 (72) Inventor Tateshita Hachishu Shinagawa-ku, Tokyo 6-7-7 Shinagawa F-term in Sony Corporation (Reference) 4M104 AA01 BB01 BB20 BB22 BB25 BB26 BB28 BB40 CC01 CC05 DD04 DD08 DD16 DD17 DD23 DD28 DD37 DD43 DD55 DD78 DD81 DD84 DD88 DD89 DD94 EE09 EE14 EE17 FF14GG GG16 HH14 HH16 HH20 5F048 AA09 AB01 AB03 AC01 AC03 BA01 BB06 BB07 BB08 BB12 BC06 BC18 BD04 BF06 BG01 BG12 BG14 DA27 5F083 GA02 JA35 JA53 NA01 NA08 PR37 PR39 PR40 PR43 PR44 PR53 PR54

Claims (8)

[Claims] 1. A semiconductor device in which a DRAM (Dynamic Random Access Memory) cell and a logic circuit are formed on a common semiconductor substrate.
The gate electrode of the AM cell, the gate electrode of the logic circuit, and the source and drain regions of the logic circuit are
A semiconductor device having the same high melting point metal silicide structure. 2. The semiconductor device according to claim 1, wherein the source and drain regions of the logic circuit have a high melting point silicide structure, and the source and drain regions of the DRAM do not have a high melting point silicide structure. 3. The semiconductor device according to claim 1, wherein the refractory metal silicide is made of Co silicide. 4. The method according to claim 1, wherein the refractory metal silicide is Ti, M
The semiconductor device according to claim 1, wherein the semiconductor device is made of a metal silicide of at least one of o, W, and Pt. 5. A method of manufacturing a semiconductor device in which a DRAM (Dynamic Random Access Memory) cell and a logic circuit are formed on a common semiconductor substrate, wherein a silicon semiconductor layer is formed on the semiconductor substrate. Forming a gate electrode of the DRAM and a gate electrode of the logic circuit at the same time using the silicon semiconductor layer; and forming the DRAM circuit and the logic circuit. Forming a first insulating layer on the source and drain regions of the DRAM, leaving the first insulating layer on the gate electrode of the DRAM, the gate electrode of the logic circuit, and the logic circuit. A patterning step for eliminating the source and drain regions of the circuit; Entirely to the generating unit,
Forming a metal layer constituting silicide by reaction with the silicon; and simultaneously forming a metal salicide in the gate electrode and the source and drain regions of the logic circuit by the metal layer. Manufacturing method of a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 5, wherein said first insulating layer is formed entirely on said DRAM forming part and said logic circuit forming part. A step of entirely forming a second insulating layer on the first insulating layer; a step of flattening the surface by etching back from a surface of the second insulating layer; Removing the second insulating layer of the logic circuit forming portion by covering with a resist; removing the etching resist; removing the first insulating layer on each of the gate electrodes; An anisotropic etching step of forming a sidewall with the first insulating layer on the gate electrode; and forming the sidewalls on the gate electrode of the DRAM and the logic circuit and the source and drain regions of the logic circuit. Forming a metal salicide simultaneously in a region forming region. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the first insulating layer entirely on the DRAM forming part and the logic circuit forming part; Forming a resist pattern on the source and drain region formation portion of the DRAM in a limited manner;
Removing the first insulating layer on the gate electrodes of the AM and the logic circuit and on the source and drain regions of the logic circuit; on the gate electrodes of the DRAM and the logic circuit; and on the source and drain of the logic circuit Forming a metal salicide simultaneously in a region forming portion. 8. The method for manufacturing a semiconductor device according to claim 5, wherein said first insulating layer is formed entirely on said DRAM forming part and said logic circuit forming part. An ion implantation step of performing ion implantation in a limited region of the first insulating layer by ion implantation in an oblique direction to the first insulating layer; and an ion implantation process in the first insulating layer. Due to the difference in the etching rate between the region where the ion implantation is performed and the region where the ion implantation is not performed or almost not performed, the first insulation on the gate electrodes of the DRAM and the logic circuit and the source and drain regions of the logic circuit are performed. Anisotropic etching step of removing a layer; forming the source and drain regions on the DRAM and the logic circuit; The method of manufacturing a semiconductor device characterized by a step of forming a metal salicide.