JP2002208978A - Quadrature modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that the bit error rate deteriorates due to delay time difference between an in-phase side data conversion signal Ich and a quadrature side data conversion signal Qch. SOLUTION: The quadrature modulator comprises a circuit 6 for demodulating an in-phase side data conversion signal Ich and a quadrature side data conversion signal Qch, respectively, from a part of a QPSK modulation signal, a circuit 7 for detecting the delay time difference between the in-phase side data conversion signal Ich and the quadrature side data conversion signal Qch from the demodulation circuit 6, and a variable delay circuit 8 for imparting the quadrature side data conversion signal Qch being inputted to a multiplier circuit 4 with a delay time such that the delay time difference is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature modulator for synthesizing an in-phase carrier modulated by an in-phase data converted signal and an orthogonal carrier modulated by an orthogonal data converted signal and outputting a modulated signal. It is related to.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a configuration of a conventional quadrature modulator. Here, a QPSK (four-phase phase shift keying) system is shown as an example. In FIG. 3, reference numeral 101 denotes a carrier oscillation circuit that outputs a carrier, 102 denotes an orthogonal distribution circuit that orthogonally divides a carrier and outputs an in-phase carrier and an orthogonal carrier having a phase difference of 90 degrees from the in-phase carrier, and 103 denotes a digital signal. A multiplication circuit for multiplying the in-phase data conversion signal Ich converted from the transmission data by the in-phase carrier from the quadrature distribution circuit 102; 104, a quadrature data conversion signal Qch converted from digital transmission data and a quadrature distribution circuit 10;
A multiplying circuit for multiplying the multiplied signal by the orthogonal carrier from 2 and a synthesizing circuit 105 for synthesizing the multiplied output of the multiplying circuit 103 and the multiplied output of the multiplying circuit 104 to output a QPSK modulated signal.

Next, the operation will be described. The carrier output from the carrier oscillation circuit 101 is transmitted to the orthogonal distribution circuit 102.
Thus, the signals are orthogonally distributed to the in-phase carrier and the orthogonal carrier. The in-phase carrier is multiplied by an in-phase data conversion signal Ich taking a value of 1 or -1 and a multiplication circuit 103, and the quadrature carrier is multiplied by a quadrature data conversion signal Qch and a multiplication circuit 104 taking a value of 1 or -1. Is done. The multiplication outputs of the multiplication circuits 103 and 104 are synthesized by the synthesis circuit 105, and correspond to 2-bit digital transmission data (00, 01, 11, 10), for example, (π / 4, 3π / 4, −−). (3π / 4, −π / 4) is output from the quadrature modulator as a QPSK modulation signal. The QPSK modulated signal is transmitted to a receiver (not shown) to mediate communication.

[0004]

Since the conventional quadrature modulator is configured as described above, the bit error rate deteriorates due to the delay time difference between the in-phase data conversion signal and the quadrature data conversion signal. There was a problem of getting it.

[0005] The occurrence of the delay time difference has a great effect on the bit error rate, and the influence becomes larger as the modulation speed becomes higher, and cannot be ignored.

As a technique for suppressing the delay time difference between the in-phase data conversion signal and the quadrature data conversion signal, for example, a quadrature modulator disclosed in JP-A-8-8985 can be mentioned. This is because the in-phase data conversion signal and the quadrature data conversion signal immediately before being input to the quadrature modulator are taken out by the A / D converter, and the delay time difference is detected by detecting the reference signal, and the in-phase data conversion signal is detected. Alternatively, the delay time difference between the orthogonal data conversion signals is changed by a variable delay circuit.

However, the above method reduces the delay time difference between the in-phase data conversion signal and the quadrature data conversion signal immediately before being input to the quadrature modulator, and reduces the delay time difference generated inside the quadrature modulator. Cannot be reduced, the effect of the delay time difference of the quadrature modulator appears directly on the modulation output. In view of the current technical trends, it is considered that the modulation speed will be further increased in the future, and a method for solving this problem is desired.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and includes a delay time difference between an in-phase data conversion signal and a quadrature data conversion signal, including a signal generated inside a quadrature modulator. And a quadrature modulator configured to minimize the bit error rate due to the delay time difference.

[0009]

SUMMARY OF THE INVENTION A quadrature modulator according to the present invention detects a delay time difference between an in-phase data conversion signal and a quadrature data conversion signal demodulated from a part of a modulation signal, and outputs an in-phase data conversion signal. Alternatively, a delay time is given to at least one of the orthogonal data conversion signals so as to minimize the delay time difference.

A quadrature modulator according to the present invention includes a demodulation circuit for demodulating an in-phase data conversion signal and a quadrature data conversion signal from a part of a modulation signal, and an in-phase data conversion signal from the demodulation circuit and a quadrature signal. A delay time difference detection circuit for detecting a delay time difference from the data conversion signal, and a delay time for at least one of the in-phase data conversion signal input to the in-phase multiplication circuit or the quadrature data conversion signal input to the quadrature multiplication circuit. And a variable delay circuit that changes the delay time so that the delay time difference is minimized.

The quadrature modulator according to the present invention is provided with a quadrature multiplex mapping circuit for generating an in-phase data conversion signal and a quadrature data conversion signal from digital transmission data.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a diagram showing a configuration of a quadrature modulator according to Embodiment 1 of the present invention. In this case, QPSK (4
Phase shift keying) is shown as an example. In FIG.
1 is a carrier oscillation circuit for outputting a carrier wave, 2 is a quadrature distribution circuit for orthogonally distributing a carrier wave and outputting an in-phase side carrier and an orthogonal side carrier having a phase difference of 90 degrees from the in-phase side carrier, and 3 is a conversion from digital transmission data. A multiplication circuit (in-phase multiplication circuit) for multiplying the obtained in-phase data conversion signal Ich by the in-phase carrier from the quadrature distribution circuit 2, and a quadrature data conversion signal Qc converted from digital transmission data
h is multiplied by the orthogonal carrier from the orthogonal distribution circuit 2 (orthogonal multiplication circuit), and the multiplication output of the multiplication circuit 3 and the multiplication output of the multiplication circuit 4 are combined to form a QPSK modulation signal (modulation signal). ) Is output.

Reference numeral 6 denotes a demodulation circuit for demodulating a part of the QPSK modulated signal output from the synthesizing circuit 5, and 7 denotes a delay time difference for detecting a delay time difference between the in-phase data conversion signal Ich and the quadrature data conversion signal Qch. The detection circuit 8 is a variable delay circuit that applies a delay time to the orthogonal-side data conversion signal Qch before being input to the multiplication circuit 4 in accordance with the delay time difference detected by the delay time difference detection circuit 7.

Next, the operation will be described. The carrier output from the carrier oscillation circuit 1 is orthogonally distributed by the orthogonal distribution circuit 2 into the in-phase carrier and the orthogonal carrier. The in-phase side carrier is changed to 1 or -1 by the in-phase side data conversion signal Ich and the multiplying circuit 3 so that the quadrature side carrier is 1
Or, the multiplication circuit 4 multiplies the orthogonal data conversion signal Qch having a value of −1 by the multiplication circuit 4. Then, the multiplication outputs of the multiplication circuits 3 and 4 are synthesized by the synthesis circuit 5 to obtain 2
Bit digital transmission data (00, 01, 11, 1)
0), for example, (π / 4, 3π / 4, −
(3π / 4, −π / 4) is output from the quadrature modulator as a QPSK modulation signal. The QPSK modulation signal is
It is transmitted to a receiver (not shown) and mediates communication.

In the first embodiment, the delay time difference between the in-phase data conversion signal Ich and the quadrature data conversion signal Qch, including the delay time difference generated inside the quadrature modulator, can be minimized. The demodulation circuit 6, the delay time difference detection circuit 7, and the variable delay circuit 8 are provided in the quadrature modulator.

A part of the QPSK modulated signal output from the quadrature modulator is input to a demodulation circuit 6 provided in the quadrature modulator. The demodulation circuit 6 demodulates the in-phase data conversion signal Ich and the quadrature data conversion signal Qch from the QPSK modulation signal and outputs the same by, for example, a synchronous detection method. The delay time difference detection circuit 7 outputs the in-phase side data conversion signal Ic.
h, The timing of the quadrature data conversion signal Qch is compared to detect a delay time difference between the in-phase data conversion signal Ich and the quadrature data conversion signal Qch. The variable delay circuit 8 gives a delay time to the quadrature data conversion signal Qch before being multiplied by the multiplier 4, and minimizes the delay time difference obtained by the delay time difference detection circuit 7. The delay time given to the orthogonal data conversion signal Qch is adjusted.

The demodulation circuit 6 once demodulates the QPSK modulated signal output from the quadrature modulator, the delay time difference detection circuit 7 detects the delay time difference, and the variable delay circuit 8 sets the quadrature data to minimize this delay time difference. Since the delay time is adjusted and given to the converted signal Qch, the delay time difference including the inside of the quadrature modulator, which cannot be compensated by the conventional quadrature modulator, can be minimized, and the QPSK modulation signal is optimized. can do. This can prevent the bit error rate from deteriorating even in a high-speed modulator that is easily affected by the delay time difference. Since the delay time difference can be automatically minimized, it is particularly suitable for a quadrature modulator installed in an artificial satellite.

Although the first embodiment has been described with the variable delay circuit 8 provided on the quadrature data conversion signal Qch side, the variable delay circuit 8 is provided with the in-phase data conversion signal Ich.
It may be provided on the channel side.
It may be provided on both sides of the channel.

As described above, according to the first embodiment, the demodulation circuit 6 for demodulating the in-phase data conversion signal Ich and the quadrature data conversion signal Qch from a part of the QPSK modulation signal, and the demodulation circuit 6 And a delay time difference detection circuit 7 for detecting a delay time difference between the in-phase data conversion signal Ich and the quadrature data conversion signal Qch from the first and second quadrature data conversion signals Qch input to the multiplication circuit 4. Since the variable delay circuit 8 for providing the delay time is provided so that the delay time difference can be minimized including that generated inside the quadrature modulator, the QPS
The effect of optimizing the K modulation signal and preventing the bit error rate from deteriorating can be obtained.

Embodiment 2 In the first embodiment, the QPS
Although the quadrature modulator taking the K system as an example has been described, the present invention is not limited to the QPSK system, but can be applied to all modulated signals obtained by in-phase quadrature multiplexing. Examples include an M-phase PSK in which the reception phase is divided into 2π / M, a QAM (quadrature amplitude modulation) system in which phase modulation and amplitude modulation are combined, and in these systems, modulation is performed in the same manner as in the first embodiment. The signal is once demodulated to detect a delay time difference, and control is performed so as to minimize the delay time difference.

FIG. 2 is a diagram showing a configuration of a quadrature modulator according to a second embodiment of the present invention. The same or corresponding components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 2, reference numeral 9 denotes a digital transmission data which is converted into an in-phase data conversion signal I.
ch, an orthogonal multiplexing mapping circuit for converting an orthogonal data conversion signal Qch. Of course, the demodulation circuit 6 corresponds to the modulation method of the orthogonal multiplex mapping circuit 9.

The digital transmission data is converted by the orthogonal multiplex mapping circuit 9 into an in-phase data conversion signal Ich and an orthogonal data conversion signal Qch, and the in-phase data conversion signal Ich and the orthogonal data conversion signal Qch are multiplied by a multiplication circuit 3,
4 respectively. Hereinafter, as in the first embodiment, the demodulation circuit 6 once demodulates a part of the modulation signal output from the synthesis circuit 5, and the delay time difference detection circuit 7
, A delay time difference is detected from the demodulation result, and the delay time of the variable delay circuit 8 is controlled so as to minimize the delay time difference.

As described above, the delay time difference between the in-phase data conversion signal Ich and the quadrature data conversion signal Qch output from the orthogonal multiplex mapping circuit 9 is obtained from the modulation signal and is minimized. As in the case of 1, the effect that the deterioration of the BER characteristic can be reduced by optimizing the modulation signal can be obtained.

As described above, the present invention is not limited to the QPSK system, but is applicable to all quadrature modulators that generate a modulation signal from an in-phase carrier and a quadrature carrier such as an M-phase PSK or QAM system. Is possible.

[0025]

As described above, according to the present invention, the delay time difference between the in-phase data conversion signal and the quadrature data conversion signal demodulated from a part of the modulation signal is detected, and the in-phase data conversion signal or the quadrature data conversion signal is detected. The delay time is given to at least one of the side data conversion signals to minimize the delay time difference, so that the delay time difference including the amount generated inside the quadrature modulator can be minimized, and the modulation signal can be optimized. Thus, the effect of preventing deterioration of the bit error rate can be obtained.

According to the present invention, a demodulation circuit for demodulating an in-phase data conversion signal and a quadrature data conversion signal from a part of a modulation signal, and an in-phase data conversion signal and a quadrature data conversion signal from the demodulation circuit. A delay time difference detection circuit for detecting a delay time difference between the input signal and a delay time given to at least one of an in-phase data conversion signal input to the in-phase multiplication circuit or a quadrature data conversion signal input to the quadrature multiplication circuit; A variable delay circuit that changes the delay time so that the time difference is minimized is provided, so that the delay time difference including that generated inside the quadrature modulator can be minimized. The effect that the deterioration of the error rate can be prevented can be obtained.

According to the present invention, since the quadrature multiplex mapping circuit for generating the in-phase data conversion signal and the quadrature data conversion signal from the digital transmission data is provided, the modulation signal is generated from the in-phase carrier and the quadrature carrier. Therefore, it is possible to minimize the delay time difference including the amount generated inside all the quadrature modulators, and to obtain the effect of optimizing the modulation signal and preventing the bit error rate from deteriorating.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a quadrature modulator according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a quadrature modulator according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a conventional quadrature modulator.

[Explanation of symbols]

Reference Signs List 1 carrier oscillation circuit, 2 orthogonal distribution circuit, 3 multiplier circuit (in-phase multiplier circuit), 4 multiplier circuit (quadrature multiplier circuit), 5 combining circuit, 6 demodulation circuit, 7 delay time difference detection circuit, 8 variable delay circuit, 9 Orthogonal multiplex mapping circuit.

Claims (3)

[Claims] 1. An in-phase carrier modulated by an in-phase data conversion signal and an orthogonal carrier having a phase difference of 90 degrees with respect to the in-phase carrier and modulated by an orthogonal data conversion signal. A quadrature modulator that outputs a modulation signal, and detects a delay time difference between the in-phase data conversion signal demodulated from a part of the modulation signal and the quadrature data conversion signal, and detects the in-phase data conversion signal or the A quadrature modulator, wherein a delay time is given to at least one of the orthogonal data conversion signals to minimize the delay time difference. 2. A carrier oscillation circuit for outputting a carrier wave, an orthogonal distribution circuit for orthogonally distributing the carrier wave, and outputting an in-phase carrier wave and an orthogonal carrier wave having a phase difference of 90 degrees with respect to the in-phase carrier wave, respectively. An in-phase multiplication circuit for multiplying the in-phase data conversion signal by the in-phase data conversion signal; an orthogonal multiplication circuit for multiplying the quadrature data conversion signal by the quadrature data carrier; an output of the in-phase multiplication circuit and the quadrature side. A quadrature modulator that combines the output of the multiplication circuit and outputs a modulation signal; a demodulation circuit that demodulates the in-phase data conversion signal and the quadrature data conversion signal from a part of the modulation signal; A delay time difference detection circuit for detecting a delay time difference between the in-phase side data conversion signal and the quadrature side data conversion signal from the circuit; and an in-phase side input to the in-phase side multiplication circuit. A variable delay circuit for providing a delay time to at least one of the data conversion signal and the orthogonal data conversion signal input to the orthogonal multiplication circuit, and changing the delay time so that the delay time difference is minimized. And a quadrature modulator. 3. The quadrature modulator according to claim 2, further comprising an orthogonal multiplex mapping circuit for generating an in-phase data conversion signal and an orthogonal data conversion signal from digital transmission data.