JP2002207465A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize low power consumption in a driving circuit of a display device corresponding to an input signal of a low voltage amplitude by using a level shifter utilizing a differential amplifier. SOLUTION: A driving circuit is divided into a plurality of units, and each unit is provided with a constant current source. In addition to a conventional scanning circuit, the unit has a sub-scanning circuit for controlling on-off the constant current source arranged for each unit, and the current is efficiently supplied by controlling to turn on only the constant current source of the unit scanning at present.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a drive circuit for the display device, and more particularly to an active matrix display device having a thin film transistor (TFT) formed on an insulator and a drive circuit for the active matrix display device. About.

[0002]

2. Description of the Related Art In recent years, the miniaturization of semiconductor manufacturing technology has advanced,
With the accompanying miniaturization of LSIs, applications to small devices such as portable terminals have been progressing, and low power consumption has been required. Currently, low power supply voltage driving such as 3.3 [V] driving is required. Is the mainstream. On the other hand, LCDs (Liquid Crystal Displays), whose demand has been remarkably increasing in recent years as applications for mobile terminals and computer monitors, are often driven by signals having a voltage amplitude of 10 [V] to 20 [V]. The drive circuit has at least a circuit section driven by a corresponding high power supply voltage. Therefore, it is indispensable to connect the controller LSI driven by the low power supply voltage and the liquid crystal drive circuit driven by the high power supply voltage with a level shifter that changes the amplitude voltage width of the signal.

In recent years, displays using not only LCDs but also electroluminescent devices (hereinafter, referred to as EL devices; both singlet emission and triplet emission are defined as EL) have been developed in recent years. However, here too, there is a strong demand for lower drive voltages.

[0004]

FIG. 6 shows an example of a circuit diagram of a source signal line driving circuit of a display device. This source signal line driver circuit includes level shifters 601 to 604, an input signal buffer 605, a shift register 606, a NAND circuit 607, a buffer 608, a first latch circuit 609, and a second latch circuit 610. Connect.
The buffer 608 does not need to be particularly provided, and may be appropriately arranged according to the logic of the signal. Here, the start pulse, the clock signal, the digital video signal, and the like are signals input from outside the display device. Since these signals are supplied from the above-described controller LSI (not shown), their voltage amplitudes are generally It is supplied by a low voltage amplitude such as 3.3 [V]. Therefore, in the driving circuit shown in FIG.
Clock signal, start pulse, digital video signal, etc.
Signals input from the external controller LSI are subjected to voltage amplitude conversion (level conversion) by the level shifters 601 to 604 immediately after input. An input signal buffer 605 arranged near the input part of the clock signal
Is to prevent the waveform of the clock signal from being rounded due to a large load on the clock signal line. As means for preventing clock signal rounding, FIG.
As shown in FIG. 01, there is a method in which the level conversion of the clock signal is performed immediately before the shift register of each stage.

The operation of the circuit will be described. 6 and 7
Has the same circuit configuration except for the clock signal level conversion means, and will be described here with reference only to FIG. According to the clock signal and start pulse,
A pulse is output from the shift register 606, and two adjacent pulses are input to the NAND circuit 607. NA
The ND circuit 607 outputs a pulse that is the logical sum of the two input signals, and this is the first latch pulse. After that, the data is input to the first latch circuit 609 through the buffer 608. In accordance with the input timing of the first latch pulse, the level shifter 603 performs a latch operation on the digital video signal whose level has been converted. After the completion of this latch operation from the first stage to the last stage, a second latch pulse is input to the input terminal 7 during the retrace period, and the signal is supplied for one horizontal period held in the first latch circuit 609. The digital video signals are simultaneously transferred to the second latch circuit 610. After that, the gate signal line (Gat
A signal is written to the pixels 611 in the row where (e Line) is selected, and an image is displayed.

The level shifters 601 to 60 in FIG.
4, and the level shifters 701 to 704 in FIG.
FIG. 3 shows an example in which a conventional level shifter is used.
It is shown in (A). Here, In is an input signal, and Out is an output signal. Inb is an inverted signal of the input signal, and may be generated from the In signal using an inverter or the like. In the level shifter having such a configuration, the input signals (In,
When the voltage amplitude of Inb) is as small as about 3.3 [V], normal level conversion may not be performed due to the influence of the threshold value of the TFT constituting the level shifter.

Therefore, a level shifter having a configuration as shown in FIG. 3B is used. The level shifter shown in FIG. 3B performs level conversion by a differential amplifier.
Even when the voltage amplitude of the input signal is small, a reliable level conversion function can be realized, so that the circuit is very effective for reducing the driving voltage of the circuit.

[0008]

However, as shown in FIG. 3 (B), a level shifter using a differential amplifier requires a constant current source 301 (Sup.), And is always in operation during operation of the circuit. Since a constant current is supplied, its power consumption is larger than that of the conventional level shifter.
It is disadvantageous for mounting on a mobile device or the like. Further, there is a demerit that the size of the buffer arranged downstream of the level shifter is large. Recently, various types of mobile devices, which have become very popular, are expected to become even smaller and lighter, and that changes in devices used to achieve low-voltage driving will increase power consumption and circuit area. It can be said that this is a fall.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and provides a driving circuit of a display device which can cope with a low driving voltage of a peripheral circuit and can realize low power consumption. The purpose is to do.

[0010]

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention takes the following measures.

In the source signal line driving circuits shown in FIGS. 6 and 7, a constant current is always supplied to the level shifter irrespective of whether a pulse is output from the shift register or whether a video signal is input. Was. Therefore, in the present invention, the drive circuit is divided for every appropriate number of stages, and the first
In addition to a first scanning circuit having a shift register for outputting a latch pulse, a second scanning circuit (hereinafter referred to as a sub-scanning circuit) using a shift register or the like that operates at a lower speed than that of the first scanning circuit. The ON / OFF operation of a current source that supplies a current to a level shifter disposed in each block is controlled by the output pulse. With such a configuration, the constant current source, which causes an increase in power consumption, can supply a current only at a necessary place, thereby achieving a significant reduction in power consumption.
Further, in the sub-scanning circuit used for controlling the constant current source, the operation speed is low, so that it hardly affects the increase in power consumption.

Hereinafter, the configuration of the display device of the present invention will be described.

According to a display device of the present invention, in a display device in which a drive circuit and a pixel portion are formed on a substrate, the drive circuit has a first scanning circuit and a second scanning circuit; The first scanning circuit includes a shift register that sequentially outputs pulses according to a first clock signal, a level shifter that converts a voltage amplitude of an input signal, and a constant current source that supplies a current to the level shifter. The second scanning circuit includes a shift register that sequentially outputs pulses in accordance with a second clock signal, and the constant current source includes
The first feature is that current is supplied only during a period in which pulses sequentially output from the scanning circuit are input to the constant current source.

According to a display device of the present invention, in a display device in which a driving circuit and a pixel portion are formed on a substrate, the driving circuit has a first scanning circuit and a second scanning circuit, The first scanning circuit includes first to x-th x stages (x is a natural number,
x ≧ 2), and the x-stage units each include a shift register that sequentially outputs pulses in accordance with a first clock signal, a level shifter that converts a voltage amplitude of an input signal, and a level shifter that converts a voltage amplitude of an input signal. A constant current source for supplying a current, and the second scanning circuit has a shift register for sequentially outputting pulses in accordance with a second clock signal, and an a-th stage (a is a natural number, 1 ≦ a ≦ The constant current source in the unit x) supplies current only during a period in which pulses sequentially output from the second scanning circuit are input to the constant current source in the a-th unit. Performing is a second feature.

In the display device according to the present invention, in addition to the first or second feature, in the display device according to claim 1 or 2, the frequency of the second clock signal is equal to the first clock. It is characterized by being lower than the frequency of the signal.

In the display device according to the present invention, in addition to the first or second feature, the second clock signal is generated from the first clock signal by a frequency dividing circuit on a substrate. Is also good.

According to a display device of the present invention, in a display device in which a drive circuit and a pixel portion are formed on a substrate, the drive circuit has a scanning circuit and a selection circuit, and the scanning circuit includes a clock. A shift register that sequentially outputs a pulse in accordance with a signal, a level shifter that converts a voltage amplitude of an input signal, and a constant current source that supplies a current to the level shifter. And a decoder that outputs a selection pulse to an arbitrary terminal out of a plurality of output terminals, wherein the constant current source outputs the current only during a period in which the selection pulse is input to the constant current source by the decoder. Supplying is a third feature.

According to a display device of the present invention, in a display device in which a driving circuit and a pixel portion are formed on a substrate, the driving circuit has a scanning circuit and a selection circuit, and the scanning circuit includes a scanning circuit. It has units of first to x-th x stages (x is a natural number, x ≧ 2). Each of the units of the x stage has a shift register for sequentially outputting pulses in accordance with a clock signal, and a shift register for sequentially inputting a voltage. A level shifter for performing conversion,
A constant current source for supplying a current to the level shifter,
The selection circuit includes a decoder that outputs a selection pulse to an arbitrary terminal among a plurality of output terminals in response to input of a selection signal, and the plurality of output terminals of the decoder are connected to the fixed units of different units. A connected to a current source
The constant current source in the unit at the stage (a is a natural number, 1 ≦ a ≦ x) is supplied by the decoder only when the selection pulse is being input to the constant current source at the stage a. The fourth feature is that the supply is performed.

According to a display device of the present invention, in a display device in which a driving circuit and a pixel portion are formed on a substrate, the driving circuit has a scanning circuit and a selection circuit, and the scanning circuit has a It has units of first to x-th x stages (x is a natural number, x ≧ 2). Each of the units of the x stage has a shift register for sequentially outputting pulses in accordance with a clock signal, and a shift register for sequentially inputting a voltage. A level shifter for performing conversion,
A constant current source that supplies a current to the level shifter; and a constant current source switch circuit that inputs a pulse to the constant current source to control a current supply period and a stop period, and the selection circuit includes a selection signal. , A decoder that outputs a selection pulse to an arbitrary terminal among a plurality of output terminals in response to
The constant current source switch circuit in the unit of the stage (a is a natural number, 1 ≦ a ≦ x) is configured to output one of the selection signals output from the decoder or the shift in the unit of the (a-1) th stage. Only during the period when the output pulse from the last stage of the register is being input, a pulse is output to the constant current source in the a-th stage unit, and the constant current source in the a-th stage unit is a
A fifth feature is that current is supplied only during a period in which a pulse is input from the constant current source switch circuit in the unit at the stage.

According to the display device of the present invention, in addition to the above-described features, the driving circuit and the pixel portion are provided on a glass substrate.
It may be formed on any of a plastic substrate, a stainless steel substrate, and a single crystal wafer.

In the display device of the present invention, in addition to the above features, the driving circuit and the pixel portion may be formed integrally on the same substrate.

In the display device of the present invention, in addition to the above features, the driving circuit and the pixel portion may be formed on different substrates.

[0023]

FIG. 1 is a diagram showing a configuration of a drive circuit of a display device according to the present invention. The source signal line drive circuit is divided for each appropriate number of stages, and a current source 103 for the level shifter is provided for each division unit. Each division unit (in FIG. 1, a portion surrounded by a dotted line frame; hereinafter, referred to as a unit) is a constant current source 103, 109, a level shifter 104, 105, 110, 111, a first shift register. 106, NAND circuit 107, buffer 10
8, first latch circuit 112, second latch circuit 113
Etc. By repeating this unit by the required number of stages, a source signal line driving circuit is formed. Each of the level shifters 105 and 111 is a single unit,
Since the effect on the increase in power consumption is negligible, the device has an independent current source and operates. As for the level shifters 104 and 110, the number of level shifters corresponding to the number of input signals required for level conversion in each unit is collected.
The constant current supplied to them is a constant current source 103,
109. Further, the driving circuit of the display device of the present invention has a sub-scanning circuit, in which ON / OFF operation of the constant current sources 103 and 109 arranged in each unit.
, And a second shift register 102 for controlling Since the number of stages of the second shift register 102 is smaller than that of the first shift register 106, the second shift register 102 may be operated at a low speed. For example, in FIG. 1, the first shift register 106 arranged per unit has four stages, so that the second shift register 102 has a frequency of about の of that of the first shift register 106. You only have to make it work.

However, the gist of the present invention is that the source signal line driving circuit is divided into a plurality of units, and a constant current source arranged for each unit is turned on / off by a sub-scanning circuit.
The point is to control. Therefore, the first shift register 1
There is no particular limitation on the relationship between the number of stages 06 and the number of stages of the second shift register 102 and the operating clock frequency.

Here, the operation of the drive circuit in the display device of the present invention shown in FIG. 1 will be described. FIG. 4 shows a simple timing chart. Also, the signal input is as shown in FIG.
Will be described using terminal numbers 11 to 18.

First, a first clock signal is input to the input terminals 12 and 13 (denoted as a clock signal A in FIG. 4). The clock signal A is input to the frequency dividing circuit 101 and the level shifter 104. A second clock signal having a lower frequency is generated from the clock signal A by the frequency dividing circuit 101 (referred to as a clock signal B in FIG. 4). The clock signal B is supplied to the second shift register 102
Is input to

Subsequently, a start pulse (indicated as a start pulse 2 in FIGS. 1 and 4) is input to the input terminal 14, and the second shift register 102 operates in response to the clock signal B, and the pulse is output. Output. This pulse is input to the constant current sources 103 and 109, and a constant current is supplied to the level shifters 104 and 1 for a period during which the pulse is input.
Supply 10

On the other hand, the clock signal A input to the level shifter 104 undergoes level conversion here and is input to the first shift register 106. A start pulse (denoted as start pulse 1 in FIGS. 1 and 4) is input from an input terminal 11, subjected to level conversion by a level shifter 105, and input to a first shift register 106.
The first shift register 106 operates by the start pulse 1 and the clock signal A, and sequentially outputs pulses.

The pulses sequentially output from the first shift register 106 are input to the NAND circuit 107. When two adjacent pulses are both at Hi potential, a pulse at Lo potential is output from the NAND circuit and input to the buffer 108. This is the first latch pulse,
Is input to the latch circuit 112.

Digital video signals corresponding to R, G, and B are input from input terminals 15 to 17, and the level shifter 11
It is input to 0. At this time, since the constant current source 109 is operating and a constant current is supplied to the level shifter 110, the level is immediately converted and input to the first latch circuit 112. The digital video signals are sequentially held according to the input timing of the first latch pulse described above.

When the holding operation in the first latch circuit in the last stage is completed in the first unit, the same operation is started in the second unit. At the same time, the second
The pulse of the next stage is output from the shift register, and a constant current is supplied to the level shifter of the second stage unit. This operation is repeated, and the digital video signal for one horizontal period is held in the first latch circuit 112.

After that, a second latch pulse is input from the input terminal 18, the level is converted by the level shifter 111, and then input to the second latch circuit 113. According to this timing, the digital video signals held in the first latch circuit 112 are simultaneously transferred to the second latch circuit 113. After that, the pixels 11 of the selected row of the gate signal line (Gate Line) are selected.
4 is written, and an image is displayed by repeating a series of these operations.

Although not shown in FIG. 1, when writing a digital video signal to a pixel, it is common practice to convert the signal into an analog signal by a D / A conversion circuit and write the converted signal.

In FIG. 4, the SR output # '(# is a natural number) is the output of the second shift register, and is the first, second, third,. It is. The constant current source arranged in each unit supplies a current to the level shifter only during a period during which the pulse is output. In the period indicated by 401, the operation of the first shift register starts first in the first stage unit, and then the last stage in the unit (in FIGS. 1 and 4, the first shift register in the unit). Since the number of register stages is set to four, the number of register stages conforms to this. Of course, the number of shift register stages per unit is not limited to this.) This is a period until the output of the first shift register ends. It can be seen that the current is supplied normally during the period. Similarly, in the periods indicated by 402 and 403, the constant current source of each unit can normally supply a constant current to the level shifter.

By the way, in the embodiment of the present invention, the sub-scanning circuit is constituted by using a shift register.
Due to the overlap of the output pulses of the shift register, the timing is such that the supply of current continues for a while after the operation of all the first shift registers is completed in a certain unit. It is preferable that the level shifter 110 is sufficiently within the operation period even when a certain amount of delay occurs between the end of the operation and the latch operation of the video signal. More preferably, the operation start timing of the second shift register is
It is preferable to ensure that the level conversion of the clock signal A input to the first-stage first shift register can be performed reliably by making the timing slightly earlier than the operation start timing of the first shift register. As described above, by taking a sufficient margin for each timing, the ON timing of the constant current source is delayed due to the rounding or delay of the pulse output, and the level conversion of each input signal cannot be performed normally. Can be avoided.

In this embodiment, the clock signal B is generated from the clock signal A using the frequency dividing circuit 101, and the start pulses 1 and 2 are input independently. There is no particular limitation. That is, the clock signal may be independently input as an external input, or a circuit that generates one start pulse from the other start pulse may be provided.

In order to explain the present invention, a source signal line driving circuit has been described as an example of a driving circuit in this specification, but the present invention can be easily applied to a gate signal line driving circuit.

[0038]

Embodiments of the present invention will be described below.

[Embodiment 1] In the drive circuit shown in the above embodiment, the input video signal is of a digital type, but the present invention is also applicable to a display device using an analog type video signal. Is possible. FIG. 2 shows an example of implementing the present invention using a source signal line driving circuit in a display device using an analog video signal. Analog video signals are input from input terminals 25 to 27 corresponding to R, G, and B, respectively.

The source signal line driving circuit shown in FIG. 2 is divided into units each having an appropriate number of stages, and a current source 203 to the level shifter is provided for each unit, as in the embodiment. Each unit has a constant current source 20
3, level shifters 204 and 205, a first shift register 206, a NAND circuit 207, a buffer 208, a sampling switch 210, and the like. Level shifter 20
Reference numeral 4 denotes a group of level shifters corresponding to the number of input signals required to be level-converted in each unit. Further, a second shift register 202 is provided for controlling ON / OFF of the operation of the constant current source 203 disposed in each unit. Since the number of stages of the second shift register 202 is smaller than that of the first shift register 206, the second shift register 202 may be operated at a low speed.

Since the operation of the circuit is the same as that of the digital type shown in the embodiment, the description is omitted here. The output pulse from the buffer 208 is input to the sampling switch 210 to make the sampling switch 210 conductive. At this timing, sampling of the analog video signal input from the input terminals 25 to 27 is performed, and writing is performed to the pixels 211 of the selected row of the gate signal line.

[Embodiment 2] In this embodiment, an example in which ON / OFF control of a constant current source is performed by a method different from that of the embodiment will be described.

In the drive circuit shown in FIG. 5, the operation of the circuit is the same as that of the digital type shown in the embodiment, but the ON / OFF control of the constant current sources 503 and 508 is performed in the embodiment. A decoder 501 is used instead of the shift register of the first embodiment. Input terminal 38 ~
A unit selection signal is input to 45 to determine which constant current source is to be operated. In FIG. 5, for example, 4
Although a bit decoder is used, it may be determined according to the number of stages of the source signal line driver circuit, the number of units, and the like.

Of course, the method described in this embodiment can be implemented in combination with an analog driving circuit.

[Embodiment 3] In this embodiment, the ON / OFF of the constant current source at the timing over the units.
The control will be described.

FIG. 14 is a diagram showing a constant current source O, similar to the second embodiment.
1 shows an example of a drive circuit in which N / OFF control is performed using a decoder. In the configuration shown in FIG. 5, the simultaneous output of two different pulses, that is, it is basically impossible to intentionally create a pulse overlap period due to the configuration of the decoder, so that the ON of the constant current sources of adjacent units is not possible. It is not possible to make a margin for the operation delay of the drive circuit by overlapping the periods. That is, the NAND circuit 1 that outputs a pulse for ON / OFF control of the constant current source of the first stage unit
401, ON / OF of the constant current source of the second stage unit
The timing with the NAND circuit 1402 that outputs the pulse for F control cannot be overlapped.

To solve this problem, as shown in FIG. 14, the decoder has two phases, and ON / OFF control of the constant current sources of the odd-numbered unit and the even-numbered unit is performed by pulses from different decoders.

First, a pulse is output from the NAND circuit 1401, and the current supply from the constant current source of the first stage unit to the level shifter is started (ON). After the latch operation is completed in the last stage of the first unit, NAN
The pulse from the D circuit 1401 is stopped, and the constant current source ends (OFF) the current supply. Here, just before the constant current source in the first stage unit is turned off, a pulse is output from the NAND circuit 1402 to turn on the constant current source in the second stage unit. This operation is performed by the NAND circuit 14
Since the input terminal of the unit selection signal to the NAND circuit 01 and the input terminal of the unit selection signal to the NAND circuit 1402 are independent from each other, this can be easily performed. Hereinafter, ON / OFF of the constant current sources of the odd-numbered unit and the even-numbered unit is alternately performed by the two-phase decoder. An advantage of such a method is that a constant current source is turned on between adjacent units.
A high degree of freedom in setting the period is given.

[Embodiment 4] In this embodiment, the ON / OFF of the constant current source at the timing of straddling between units
An example in which the control is performed by a method different from that in the third embodiment will be described.

In implementing the present invention, if the power consumption is to be reduced by focusing on the level shifter, the number of shift register stages in a unit unit should be reduced, that is, it is better to divide the unit into a larger number of units. The number of level shifters that are supplied can be reduced. In that case,
The number of bits of a signal input to the decoder in the sub-scanning circuit increases, and the number of unit selection signal lines increases, thereby increasing the area occupied by the sub-scanning circuit. further,
In the method of the fourth embodiment in which the decoder has two phases, there is a disadvantage that the occupied area is further increased.

Therefore, in the present embodiment, an example in which the ON / OFF control of the constant current source is performed using the output pulse from the shift register together to obtain the same effect as in the fourth embodiment will be described.

Referring to FIG. The selection circuit 1500 is the same as that of the second embodiment, and is configured by a one-phase decoder. ON / OFF of the constant current source in the first stage unit 1510 is performed by the output of the NAND circuit 1501 in the first stage of the decoder, as in the second embodiment. In the units from the second stage to the last stage, the output pulse of the NAND circuit is input to the newly added circuit. In the unit of the second stage, the NAN of the second stage of the decoder
An output pulse of the D circuit 1502 is input to one of a two-input NOR circuit (hereinafter simply referred to as a NOR circuit) 1503. The output pulse of the last-stage shift register 1505 in the preceding unit is input to the remaining one of the inputs of the NOR circuit. Thereafter, the same configuration is adopted up to the last unit.

Note that, in order to discriminate from the circuit shown in the second embodiment, a circuit including a NOR circuit 1503 and an inverter 1504 is defined as a constant current source switch circuit. This constant current source switch circuit is included in a unit, that is, each unit has a constant current source switch circuit. Note that this constant current source switch circuit
This embodiment is merely an example. Therefore,
The circuit configuration is not limited as long as the input / output logic is the same.

Further, in FIG. 15, the first stage unit does not have the constant current source switch circuit because only the first stage unit can freely determine the timing of starting the input of the selection signal to the decoder. This is because there is no need to cover the ON timing of the constant current source with a pulse from another circuit, but a constant current source switch circuit may be provided here.

The circuit operation will be described with reference to the timing chart shown in FIG. First, in order to perform level conversion of a clock signal input to a shift register, a unit selection signal is input to a decoder 1500, a pulse is output from a NAND circuit 1501 (denoted as a decoder output 1 in FIG. 16), and a constant current source is output. The current supply of 1511 and 1512 is started. In accordance with the clock signal and the start pulse, the shift register operates in the first stage unit and sequentially outputs pulses (in FIG. 16, SR output #.
Is the number of stages, 1 to final). The pulse indicated by decoder output 1 is
A pulse is output until the operation of the shift register in the last stage of the first unit is completed, whereby the operation of the shift register in the first unit is guaranteed.

Subsequently, the operation is started in the second stage unit. Here, the constant current sources 1513 and 1514 in the second stage unit output the NOR circuit 1503 from the decoder output 2 by inputting the output pulse from the shift register 1505 in the last stage of the first unit. It starts early. The operation timing of the constant current source of each unit shown in FIG.
Notated as S current source #. # Is the number of stages, 1 to final), 1
In a part of the period indicated by reference numeral 602, the ON control of the constant current source is performed not by the output from the decoder but by the output of the preceding shift register. After the output of the previous stage shift register is completed, the constant current source is turned on by the decoder output.
(1603). That is, the NOR circuit 1
During a period in which a pulse is input to one or both of the input terminals 503, the constant current sources 1513 and 151
4 turns ON.

Eventually, the pulse output from the shift register 1509 at the last stage of the second stage unit is input to the NOR circuit, so that the constant current source is turned on in the third stage unit. Then, shift register 1
With the end of the pulse output of step 509, the constant current source is turned off in the third stage unit.

Thereafter, by performing the same operation up to the last unit of the drive circuit, a period during which the constant current sources of both units are ON can be provided at the timing across the units. Also, the circuit area can be implemented by adding only a few elements to the circuit of the second embodiment, and the circuit area can be greatly reduced as compared with the case where the decoder has two phases.

[Embodiment 5] In this embodiment, the TFTs of the pixel portion of the display device of the present invention and the drive circuit portions (source signal line side drive circuit, gate signal line side drive circuit) provided around the pixel portion are provided.
Will be described at the same time. However, for the sake of simplicity, a CMOS circuit, which is a basic unit for the drive circuit unit, is illustrated.

Referring to FIG. First, in this embodiment, a substrate 50 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used.
01 is used. Note that the substrate 5001 is not limited as long as it has a light-transmitting property, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a base film 5002 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 5001. In this embodiment, the base film 5002
Is used, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. Base film 500
As the first layer of No. 2, a plasma CVD
₄ , a silicon oxynitride film 5001a formed using NH ₃ and N ₂ O as reaction gases is formed in a thickness of 10 to 200 [nm] (preferably 50 to 100 [nm]). In this embodiment, the film thickness 50
[nm] silicon oxynitride film 5002a (composition ratio Si = 32
[%], O = 27 [%], N = 24 [%], H = 17 [%]. Next, as the second layer of the base film 5002,
Using a plasma CVD method, a silicon oxynitride film 5002b formed by using SiH ₄ and N ₂ O as reaction gases is reduced to 50 to 50%.
The layer is formed to a thickness of 200 [nm] (preferably 100 to 150 [nm]). In this embodiment, a silicon oxynitride film 5002b having a thickness of 100 nm (composition ratio: Si = 32%, O = 59)
[%], N = 7 [%], H = 2 [%]).

Next, the semiconductor layers 5003 to 5005
006 is formed. As the semiconductor layers 5003 to 5006, a semiconductor film having an amorphous structure is formed by a known method (sputtering,
After forming a film by LPCVD or plasma CVD, a known crystallization treatment (laser crystallization, thermal crystallization, or thermal crystallization using a catalyst such as nickel) is performed. The formed crystalline semiconductor film is patterned and formed into a desired shape. The semiconductor layers 5003 to 50
06 is 25 to 80 [nm] (preferably 30 to 60 [nm])
Formed with a thickness of Without limitation on the material of the crystalline semiconductor film, preferably silicon (silicon) or silicon germanium _{(Si X Ge 1-X (} X = 0.0001~0.0
2)) It is good to form with an alloy etc. In this example, after a 55 [nm] amorphous silicon film was formed by a plasma CVD method, a solution containing nickel was held on the amorphous silicon film. After dehydrogenation (500 [° C.], 1 hour) of this amorphous silicon film, thermal crystallization (550 [° C.], 4 hours) is performed, and laser annealing for further improving crystallization is performed. Then, a crystalline silicon film was formed by performing a heat treatment. Then, semiconductor layers 5003 to 5006 were formed from the crystalline silicon film by a patterning process using a photolithography method.

After the formation of the semiconductor layers 5003 to 5006, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz], and the laser energy density is 100 to 40.
0 [mJ / cm ² ] (typically 200 to 300 [mJ / cm ² ]). When a YAG laser is used, its second harmonic is used to set the pulse oscillation frequency to 1 to 10 kHz and the laser energy density to 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ / cm ^2]. ]) Then, a laser beam condensed linearly with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is irradiated.
May be set as 50 to 90 [%].

Next, a gate insulating film 5007 covering the semiconductor layers 5003 to 5006 is formed. Gate insulating film 50
07 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, 110 [nm] is obtained by the plasma CVD method.
Silicon oxynitride film (composition ratio Si = 32 [%], O =
59 [%], N = 7 [%], H = 2 [%]). Needless to say, the gate insulating film 5007 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicat
e) and O ₂ were mixed, the reaction pressure was 40 [Pa], and the substrate temperature was 30.
It can be formed by discharging at a high-frequency (13.56 [MHz]) power density of 0.5 to 0.8 [W / cm ₂ ] at 0 to 400 [° C.]. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

Next, a film thickness of 2 is formed on the gate insulating film 5007.
A first conductive film 5008 of 0 to 100 [nm] and a film thickness of 100
A second conductive film 5009 of about 400 [nm] is stacked. In this embodiment, a first conductive film 5007 made of a TaN film having a thickness of 30 [nm] and a second conductive film 5008 made of a W film having a thickness of 370 [nm] are formed by lamination. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set it to 0 [μΩcm] or less. The resistivity of the W film can be reduced by enlarging the crystal grains.
When there are many impurity elements such as oxygen in the film, crystallization is hindered and the resistance is increased. Therefore, in this embodiment, high-purity W
(Purity: 99.9999 [%]) by forming a W film with sufficient care so as not to mix impurities from the gas phase at the time of film formation by a sputtering method using a target having a resistivity of 9 to 9%. 20 [μΩcm] was achieved.

In this embodiment, the first conductive film 500
8 was TaN, and the second conductive film 5009 was W. However, the present invention is not limited thereto, and any of Ta, W, Ti, Mo, Al, and C may be used.
It may be formed of an element selected from u, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, A
An alloy composed of g, Pd, and Cu may be used. Further, the first conductive film is formed of a Ta film, the second conductive film is formed of a W film, and the first conductive film is formed of a TiN film.
The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of an Al film, the first conductive film is formed of a TaN film,
The second conductive film may be a combination of a Cu film.

Next, as shown in FIG. 8B, a mask 5010 made of a resist is formed by photolithography, and a first etching process for forming electrodes and wirings is performed. In the first etching process, the first and second
The etching conditions are as follows. In the present embodiment, the first etching condition is ICP (Inductively Coupled Plasm
a: Inductively coupled plasma) Using an etching method, using CF ₄ , Cl _2, and O ₂ as etching gases, setting a gas flow ratio of each to 25/25/10 [sccm], and a pressure of 1 [Pa]. And 500 [W] RF (13.56 [M]
Hz]) Power was applied to generate plasma to perform etching. Here, a dry etching apparatus (Model E645-IC) using ICP manufactured by Matsushita Electric Industrial Co., Ltd.
P) was used. 150 [W] on substrate side (sample stage)
(13.56 [MHz]), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered. The etching rate for W under the first etching condition is 200.39 [nm / min.], And TaN
Is 80.32 [nm / min.], And the selectivity ratio of W to TaN is about 2.5. Further, the taper angle of W is about 26 ° under the first etching condition.

Thereafter, as shown in FIG. 8B, the second etching condition was changed without removing the resist mask 5010, and CF ₄ and Cl ₂ were used as etching gases, and the respective gas flow rates were changed. The ratio is 30/30 [sccm] and 1
At a pressure of [Pa], 500 [W] RF (1
3.56 [MHz]) power was supplied to generate plasma, and etching was performed for about 30 seconds. An RF (13.56 [MHz]) power of 20 [W] is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF
_Under the second etching condition in which ₄ and Cl ₂ are mixed, both the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 [n].
m / min.], and the etching rate for TaN is 66.43.
[nm / min.]. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased at a rate of about 10 to 20%.

In the first etching process, the shape of the mask made of resist is made appropriate so that
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees. Thus, the first-shaped conductive layers 5011 to 5015 including the first conductive layer and the second conductive layer by the first etching process.
(First conductive layers 5011a to 5015a and second conductive layers 5011b to 5015b) are formed. Gate insulating film 5
007, the first shape conductive layers 5011 to 50
The region not covered with 15 is etched to about 20 to 50 [nm] to form a thinned region.

Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type is added to the semiconductor layer (FIG. 8B). The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose is 1 × 10 ¹³
５5 × 10 ¹⁵ [atoms / cm ² ] and the acceleration voltage is 60-1
It is performed as 00 [keV]. In this embodiment, the dose is 1.5
The measurement was performed at × 10 ¹⁵ [atoms / cm ² ] and the acceleration voltage was 80 [keV]. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the first
The conductive layers 5011 to 5015 having the above-mentioned shape serve as masks for the impurity element imparting n-type, and the high-concentration impurity regions 5016 to 5019 are formed in a self-aligned manner. 1 × 10 ²⁰ to 1 × 10 ^{21 in the} high concentration impurity regions 5016 to 5019
An impurity element imparting n-type is added in a concentration range of [atoms / cm ³ ].

Next, as shown in FIG. 8C, a second etching process is performed without removing the resist mask. Here, CF ₄ , Cl ₂ and O ₂ are used as etching gases.
And the respective gas flow ratios are set to 20/20/20 [s
ccm] and 500 [W] to the coil type electrode at a pressure of 1 [Pa].
RF (13.56 [MHz]) power was supplied to generate plasma, and etching was performed. Substrate side (sample stage)
Also, an RF (13.56 [MHz]) power of 20 [W] is supplied, and a substantially negative self-bias voltage is applied. The etching rate for W in the second etching process is 12
At 4.62 [nm / min.], The etching rate for TaN is 20.67 [nm / min.], And the selectivity ratio of W to TaN is 6.05. Therefore, the W film is selectively etched. The taper angle of W became 70 ° by the second etching. By this second etching process, second conductive layers 5020b to 5024b are formed. on the other hand,
The first conductive layers 5011a to 5015a are hardly etched to form first conductive layers 5020a to 5024a.

Next, a second doping process is performed. The doping is performed using the second conductive layers 5020b to 5024b as a mask for the impurity element, so that the semiconductor layer below the tapered portion of the first conductive layer is doped with the impurity element. In this embodiment, P is used as the impurity element.
(Phosphorus) with a dose of 1.5 × 10 ¹⁴ [atoms / c
m ² ], a current density of 0.5 [μA], and an acceleration voltage of 90 [keV]. Thus, low-concentration impurity regions 5025 to 5028 overlapping with the first conductive layer are formed in a self-aligned manner. These low concentration impurity regions 5025 to 502
The concentration of phosphorus (P) added to 8 was 1 × 10 ^{17 to} 5 ×
10 ¹⁸ [atoms / cm ³ ], and has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer.
Note that in the semiconductor layer overlapping with the tapered portion of the first conductive layer, the impurity concentration is slightly reduced from the end of the tapered portion of the first conductive layer toward the inside, but is approximately the same. . Further, the high-concentration impurity regions 5016 to
An impurity element is also added to 5019 (FIG. 9A).

Next, as shown in FIG. 9B, after removing the resist mask, a third etching process is performed using photolithography. This third etching treatment is performed in order to partially etch the tapered portion of the first conductive layer so that the tapered portion overlaps with the second conductive layer. However, a mask made of the resist 5029 is formed in a region where the third etching is not performed.

Etching in Third Etching Process
The conditions are Cl as an etching gas. _TwoAnd SF₆Using
The first and second gas flow ratios were 10/50 [sccm].
And ICP etching method as in the second etching.
Do it. Note that TaN in the third etching process is
The etching rate is 111.2 nm / min.
The etching rate for the gate insulating film is 12.8 [nm / mi
n.].

In the present embodiment, etching was performed by applying a RF (13.56 [MHz]) power of 500 [W] to the coil-type electrode at a pressure of 1.3 [Pa] to generate plasma. . The RF (13.56) of 10 [W] is also provided on the substrate side (sample stage).
[MHz]) Power is applied and a substantially negative self-bias voltage is applied. As described above, the first conductive layers 5030a to 5030a-5
032a is formed.

By the third etching, impurity regions (LDD regions) 5033 to 5034 which do not overlap with the first conductive layers 5030a to 5032a are formed. Note that impurity regions (GOLD regions) 5025 and 5028
Remain over the first conductive layers 5020a and 5024a, respectively.

As described above, in the present embodiment, the impurity regions (LDD regions) 5033 to 533 which do not overlap with the first conductive layer
034 and an impurity region (GOLD) overlapping the first conductive layer.
Regions) 5025 and 5028 can be formed at the same time, and can be separately formed according to the TFT characteristics.

Next, after removing the resist mask, the gate insulating film 5007 is etched. The etching process here is performed using CHF ₃ as an etching gas and a reactive ion etching method (RIE method). In this embodiment, the chamber pressure is 6.7 [Pa], and the RF is
The third etching process was performed at a power of 800 [W] and a CHF ₃ gas flow rate of 35 [sccm]. As a result, a part of the high-concentration impurity regions 5016 to 5019 is exposed, and the gate insulating film 5
007a to 5007d are formed.

Next, a new mask 50 made of resist is used.
35 is formed and a third doping process is performed. This third
Is obtained by adding an impurity element imparting a second conductivity type (p-type) opposite to the first conductivity type (n-type) to a semiconductor layer serving as an active layer of a p-channel TFT by the doping process. A region 5036 is formed (FIG. 9C). Using the first conductive layer 5030a as a mask for an impurity element, an impurity element imparting p-type conductivity is added to form an impurity region in a self-aligned manner.

In this embodiment, the impurity region 5036 is formed by an ion doping method using diborane (B ₂ H ₆ ). At the time of the third doping process, the semiconductor layer forming the n-channel TFT is made of a resist mask 5.
035. First doping process and second doping
Is added to the impurity regions 5036 at different concentrations by the doping process, but the concentration of the impurity element imparting p-type is 2 × 10 ²⁰ to 2 × 10 ²¹ [atoms / By performing the doping treatment so as to obtain cm ³ ], there is no problem because it functions as the source region and the drain region of the p-channel TFT.

Through the above steps, an impurity region is formed in each semiconductor layer. In this embodiment, the method of doping the impurity (B) after etching the gate insulating film is described; however, the impurity may be doped without etching the gate insulating film.

Next, a mask 5035 made of resist is used.
Is removed to form a first interlayer insulating film 5037 as shown in FIG. The first interlayer insulating film 5037 is formed of an insulating film containing silicon with a thickness of 100 to 200 [nm] by a plasma CVD method or a sputtering method. In this embodiment, a film thickness of 15
A silicon oxynitride film of 0 [nm] was formed. Needless to say, the first interlayer insulating film 5037 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 1 [ppm] or less,
Preferably in a nitrogen atmosphere of 0.1 [ppm] or less,
The heat treatment may be performed at 700 ° C., typically 500 to 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA)
Law) can be applied.

In this embodiment, at the same time as the above activation treatment, Ni used as a catalyst during crystallization is gettered into an impurity region containing a high concentration of P, and the semiconductor layer mainly serving as a channel formation region is obtained. The nickel concentration in is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

The activation process may be performed before forming the first interlayer insulating film 5037. However, when the wiring material used is weak to heat, after forming an interlayer insulating film 5037 (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment. Preferably, an activation treatment is performed.

Alternatively, a doping process may be performed after the activation process to form the first interlayer insulating film 5037.

Further, a heat treatment is performed for 1 to 12 hours at 300 to 550 ° C. in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film 5037. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When a laser annealing method is used as the activation treatment, it is preferable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, as shown in FIG. 10B, a second interlayer insulating film 5038 made of an organic insulating material is formed on the first interlayer insulating film 5037. In this embodiment, the film thickness is 1.
An acrylic resin film of 6 [μm] was formed. Next, patterning for forming a contact hole reaching each of the impurity regions 5016, 5018, 5019, and 5036 is performed.

As the second interlayer insulating film 5038, a film made of an insulating material containing silicon or an organic resin is used. As the insulating material containing silicon, silicon oxide, silicon nitride, or silicon oxynitride can be used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used.

In this embodiment, a silicon oxynitride film formed by a plasma CVD method was formed. Note that the thickness of the silicon oxynitride film is preferably 1 to 5 μm (more preferably 2 to 4 μm). A silicon oxynitride film is effective in suppressing deterioration of an EL element because moisture contained in the film itself is small. In addition, dry etching or wet etching can be used for forming the contact hole. However, considering the problem of electrostatic breakdown at the time of etching, it is preferable to use a wet etching method.

Further, since the first interlayer insulating film 5037 and the second interlayer insulating film 5038 are simultaneously etched in the formation of the contact hole here, the material for forming the second interlayer insulating film 5038 in consideration of the shape of the contact hole. It is preferable to use a material having a higher etching rate than the material for forming the first interlayer insulating film 5037.

Then, each of the impurity regions 5016 and 501
Wirings 5039 to 5044 electrically connected to the wirings 8, 5019 and 5036 are formed. Here, the film thickness 50
[nm] Ti film and 500 [nm] thick alloy film (Al and Ti
An alloy film is formed by patterning, but another conductive film may be used.

As described above, the n-channel TFT,
a driving circuit having a p-channel TFT, a pixel TFT,
The pixel portion having a storage capacitor can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate.

As for the storage capacitor, a necessary portion may be selectively doped with impurities before forming the gate conductive film to form a capacitor. According to this method, the number of photoresist masks is increased by one, but a storage capacitor can be formed without applying a bias.

Subsequently, a third interlayer insulating film 5045 is formed. In this step, the surface on which the TFT is formed is flattened to form a subsequent pixel electrode. Therefore, it is desirable that the insulating film be formed of an insulating film made of a resin film such as acrylic, which has excellent flatness. Next, a pixel electrode (reflective electrode) 5046 is formed by forming and patterning an MgAg film thereon (FIG. 1).
0 (C)).

On the other hand, a counter substrate 5047 is prepared. FIG.
As shown in FIG. 1A, a color filter layer 5048 to 5050, an overcoat layer 505
Form one. The color filter layer is located above the TFT,
Color filters 5048 and 5049 of different colors are formed so as to overlap with each other, and also serve as a light shielding film. The color filter layer of each color is made of a mixture of a resin and a pigment.
It is formed to a thickness of about 3 [μm]. For this, a photosensitive material can be used to form a predetermined pattern using a mask. At the same time, a spacer is formed using this color filter layer (not shown). This may be formed by overlapping color filters. The height of the spacer is 1 to 4 times the thickness of the overcoat layer 5051.
By considering [μm], the thickness can be set to 2 to 7 [μm], preferably 4 to 6 [μm], and the height can reduce the gap when the active matrix substrate and the counter substrate are bonded to each other. Form. The overcoat layer 5051 is formed using a photocurable or thermosetting organic resin material, and for example, polyimide or an acrylic resin may be used.

After forming the overcoat layer 5051,
A counter electrode 5052 made of a transparent conductive film is formed by patterning. After that, an alignment film 5053 is formed on both the active matrix substrate and the counter substrate, and a rubbing process is performed.

Thereafter, the active matrix substrate and the counter substrate are bonded with a sealant 5055. A filler is mixed in the sealant 5055, and the two substrates are bonded at a uniform interval by the filler and the spacer. Subsequently, a liquid crystal material 50 is provided between the two substrates.
Inject 54 and completely seal with sealant (not shown). As the liquid crystal material 5054, a known liquid crystal material may be used. As described above, an active matrix liquid crystal display device as shown in FIG. 11A is completed.

Although the TFT in the active matrix type liquid crystal display device manufactured by the above-described process has a top gate structure, a TFT having a bottom gate structure.
This embodiment can be easily applied to TFTs having other structures. Further, by forming the pixel electrode with a transparent conductive film, a transmissive display device can be obtained.

In this embodiment, a glass substrate is used. However, the present invention is not limited to a glass substrate, and the present invention can be applied to a case where a substrate other than a glass substrate such as a plastic substrate, a stainless steel substrate, a single crystal wafer, etc. is used. It is.

[Embodiment 6] The display device of the present invention has various uses. In this embodiment, an application example of an electronic device in which the display device of the present invention is incorporated will be described.

Such electronic devices include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a digital camera, a personal computer, a television, a projector device, and the like. Examples of these are shown in FIGS.

FIG. 12A shows a liquid crystal display (LC).
D), the housing 3301, the support 3302, and the display unit 3
303 and the like. The display device of the present invention can be used for the display portion 3303.

FIG. 12B shows a video camera, which includes a main body 3311, a display section 3312, an audio input section 3313, operation switches 3314, a battery 3315, and an image receiving section 331.
6 and so on. The display device of the present invention can be used for the display portion 3312.

FIG. 12C shows a personal computer, which includes a main body 3321, a housing 3322, a display portion 3323,
A keyboard 3324 and the like are included. The display device of the present invention can be used for the display portion 3323.

FIG. 12D shows a portable information terminal, which includes a main body 3331, a stylus 3332, a display portion 3333, operation buttons 3334, an external interface 3335, and the like. The display device of the present invention can be used for the display portion 3333.

FIG. 13A shows a mobile phone, and the main body 34 is provided.
01, audio output unit 3402, audio input unit 3403, display unit 3404, operation switch 3405, antenna 3406
including. The display device of the present invention can be used for the display portion 3404.

FIG. 13B shows an audio reproducing apparatus, specifically, a car audio system.
2. Including operation switches 3413 and 3414. The display device of the present invention can be used for the display portion 3412. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus.

FIG. 13C shows a digital camera, which includes a main body 3501, a display section (A) 3502, an eyepiece section 3503,
An operation switch 3504, a display portion (B) 3505, and a battery 3506 are included. The display device of the present invention can be used for the display portion (A) 3502 and the display portion (B) 3505.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in various fields. In addition, any of the configurations shown in the first to fifth embodiments may be applied to the electronic apparatus of the present embodiment.

According to the present invention, an external controller LSI
It is possible to provide a driving circuit of a display device which can cope with a constant driving voltage and realize low power consumption.

[Brief description of the drawings]

FIG. 1 is a diagram showing a digital driving circuit configuration of a display device of the present invention.

FIG. 2 is a diagram showing a configuration of an analog driving circuit of a display device of the present invention.

FIG. 3 is a diagram showing a normal level shifter and a level shifter using a differential amplifier.

FIG. 4 is a diagram showing a timing chart of the operation of the circuit in the embodiment.

FIG. 5 is a diagram illustrating an example in which a selection circuit is configured using a decoder.

FIG. 6 is a diagram illustrating a configuration of a source signal line driving circuit in a conventional display device.

FIG. 7 illustrates a configuration of a source signal line driving circuit in a conventional display device.

FIG. 8 illustrates an example of a manufacturing process of a display device.

FIG. 9 illustrates an example of a manufacturing process of a display device.

FIG. 10 illustrates an example of a manufacturing process of a display device.

FIG. 11 illustrates an example of a manufacturing process of a display device.

FIG. 12 illustrates an example in which the display device of the present invention is applied to an electronic device.

FIG. 13 illustrates an example in which the display device of the present invention is applied to an electronic device.

FIG. 14 illustrates an example in which a selection circuit is configured using a decoder.

FIG. 15 illustrates an example in which a selection circuit is configured using a decoder.

16 is a diagram showing a timing chart of the operation of the circuit shown in FIG.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623B 680 680P 680T 680V F-term (Reference) 2H092 GA59 JA24 RA10 2H093 NC01 NC09 NC22 ND39 5C006 BB16 BC03 BC20 BF03 BF46 BF49 EB05 FA46 FA47 5C080 AA10 BB05 DD25 DD26 DD30 FF11 JJ02 JJ03 JJ04 JJ06 KK02 KK07 KK43

Claims (15)

[Claims] 1. A display device in which a driving circuit and a pixel portion are formed on a substrate, wherein the driving circuit has a first scanning circuit and a second scanning circuit, and the first scanning The circuit includes a shift register that sequentially outputs pulses according to a first clock signal, a level shifter that converts a voltage amplitude of an input signal, and a constant current source that supplies a current to the level shifter; Has a shift register that sequentially outputs pulses in accordance with a second clock signal. The constant current source is configured such that pulses sequentially output from the second scanning circuit are input to the constant current source. A display device, wherein current is supplied only during a certain period. 2. A display device having a driving circuit and a pixel portion formed on a substrate, wherein the driving circuit has a first scanning circuit and a second scanning circuit, and the first scanning circuit The circuit is
A shift register which has first to x-th x stages (x is a natural number, x ≧ 2), wherein each of the x-stage units sequentially outputs pulses according to a first clock signal;
A shift register that has a level shifter that converts a voltage amplitude of an input signal and a constant current source that supplies a current to the level shifter, wherein the second scanning circuit sequentially outputs pulses according to a second clock signal And the constant current source in the unit of the a-th stage (a is a natural number, 1 ≦ a ≦ x) is configured such that the pulse sequentially output from the second scanning circuit is in the unit of the a-th stage. A display device, wherein current is supplied only during a period in which the current is input to the constant current source. 3. The display device according to claim 1, wherein a frequency of the second clock signal is lower than a frequency of the first clock signal. 4. The display device according to claim 1, wherein said second clock signal is generated from said first clock signal by a frequency dividing circuit on a substrate. Display device. 5. A display device in which a driving circuit and a pixel portion are formed on a substrate, wherein the driving circuit has a scanning circuit and a selection circuit, wherein the scanning circuit sequentially generates pulses according to a clock signal. A shift register for outputting, a level shifter for converting a voltage amplitude of an input signal, and a constant current source for supplying a current to the level shifter, wherein the selection circuit has a plurality of output terminals according to a selection signal input. Has a decoder that outputs a selection pulse to an arbitrary terminal, wherein the constant current source supplies current only during a period in which the selection pulse is input to the constant current source by the decoder. Characteristic display device. 6. A display device in which a driving circuit and a pixel portion are formed on a substrate, wherein the driving circuit has a scanning circuit and a selection circuit, and the scanning circuit includes first to x-th scanning circuits. It has x-stage (x is a natural number, x ≧ 2) units, each of which has a shift register for sequentially outputting pulses in accordance with a clock signal, and a level shifter for converting the voltage amplitude of an input signal. A constant current source that supplies a current to the level shifter; the selection circuit includes a decoder that outputs a selection pulse to an arbitrary terminal among a plurality of output terminals in response to a selection signal input; Are connected to the constant current sources of the units of different stages, respectively. The constant current source in the unit of the a-th stage (a is a natural number, 1 ≦ a ≦ x) is In a period in which-option pulse is input to the constant current source of the first a stage only, display device which is characterized in that the supply of current. 7. A display device in which a driving circuit and a pixel portion are formed on a substrate, wherein the driving circuit has a scanning circuit and a selection circuit, wherein the scanning circuit has first to x-th x stages (x is a natural number, x ≧
2) wherein the x-stage units each include a shift register for sequentially outputting pulses in accordance with a clock signal, a level shifter for converting the voltage amplitude of an input signal, and a constant for supplying a current to the level shifter. A current source, and a constant current source switch circuit that inputs a pulse to the constant current source to control a current supply period and a stop period, and the selection circuit has a plurality of output terminals according to a selection signal input. And a decoder that outputs a selection pulse to an arbitrary terminal. The constant current source switch circuit in the unit of the a-th stage (a is a natural number, 1 ≦ a ≦ x) selects a signal output from the decoder. Only during one of the signals or during the period when the output pulse from the last stage of the shift register in the (a-1) -th unit is being input, the a-stage unit is used. A pulse is output to the constant current source in the unit, and the constant current source in the a-th unit is in a period in which a pulse is input from the constant current source switch circuit in the a-th unit. A display device characterized in that only a current is supplied. 8. The display device according to claim 1, wherein the driving circuit and the pixel portion are formed on a glass substrate, a plastic substrate, a stainless steel substrate, or a single crystal wafer. A display device formed on any of the above. 9. The display device according to claim 1, wherein the drive circuit and the pixel portion are formed integrally on a same substrate. apparatus. 10. The display device according to claim 1, wherein the drive circuit and the pixel portion are formed on different substrates. . 11. A liquid crystal display using the display device according to any one of claims 1 to 10. 12. A personal computer using the display device according to any one of claims 1 to 10. 13. A portable information terminal using the display device according to any one of claims 1 to 10. 14. A car audio using the display device according to any one of claims 1 to 10. 15. A digital camera using the display device according to any one of claims 1 to 10.