JP2002204056A - Circuit board for soldering - Google Patents
Circuit board for solderingInfo
- Publication number
- JP2002204056A JP2002204056A JP2000403322A JP2000403322A JP2002204056A JP 2002204056 A JP2002204056 A JP 2002204056A JP 2000403322 A JP2000403322 A JP 2000403322A JP 2000403322 A JP2000403322 A JP 2000403322A JP 2002204056 A JP2002204056 A JP 2002204056A
- Authority
- JP
- Japan
- Prior art keywords
- soldering
- circuit board
- alloy
- electroplated
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、鉛（Ｐｂ）を含有
しない錫（Ｓｎ）合金、特に、Ｓｎにビスマス（Ｂ
ｉ）、銀（Ａｇ）、亜鉛（Ｚｎ）又は銅（Ｃｕ）等を含
むＳｎ合金を回路パターン上に電気鍍金した安全で、環
境に良好なＴＡＢテープ、ＣＳＰ、ＢＧＡ、ＣＯＦ等の
半田付け用回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tin (Sn) alloy containing no lead (Pb), in particular, bismuth (B)
i) For safe and environmentally friendly soldering of TAB tape, CSP, BGA, COF etc. by electroplating a Sn alloy containing silver (Ag), zinc (Zn) or copper (Cu) on the circuit pattern Related to a circuit board.
【０００２】[0002]
【従来の技術】従来、半田付け用回路基板として、種々
のものが用いられている。例えば、基板にフレキシブル
なポリイミド等を用いたＴＡＢ（Tape Automated Bondi
ng）テープ、ＣＳＰ（Chip Size Package）、ＢＧＡ（B
all Grid Array）、ＦＰＣ（Flexible Printed Circui
t）等があり、又、ガラスエポキシ等のリジッドな基板
を用いたいわゆる多層基板がある。そして、これらの半
田付け用回路基板の回路パターン上にはＳｎ‐Ｐｂ合金
鍍金が行われていた。2. Description of the Related Art Conventionally, various types of circuit boards for soldering have been used. For example, TAB (Tape Automated Bondi) using flexible polyimide etc. for the substrate
ng) Tape, CSP (Chip Size Package), BGA (B
all Grid Array), FPC (Flexible Printed Circui)
t), and a so-called multilayer substrate using a rigid substrate such as glass epoxy. Then, Sn-Pb alloy plating was performed on the circuit patterns of these circuit boards for soldering.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、Ｐｂは
人体への毒性が問題となると共に、環境汚染の問題を引
き起こしている。そのため、近年人体への影響や環境保
護の点でＰｂの使用が規制されている。その結果、Ｐｂ
を含む合金鍍金と同等の機能を果たし、人体や環境に影
響を与えない他の安全性の高い金属を用いて半田付け用
回路基板の回路パターン上に鍍金を行なう必要がある。However, Pb poses problems of toxicity to the human body and causes environmental pollution. Therefore, in recent years, the use of Pb has been regulated in terms of impact on the human body and environmental protection. As a result, Pb
It is necessary to perform plating on the circuit pattern of the circuit board for soldering by using another highly safe metal which has the same function as alloy plating including, and does not affect the human body and the environment.
【０００４】本発明は、上記の事情を背景になされたも
のであり、ＴＡＢテープ、ＣＳＰ、ＢＧＡ、ＣＯＦ等の
半田付け用回路基板の回路パターンに半田鍍金を施す場
合に、Ｓｎ‐Ｐｂ合金のうちのＰｂを他の安全性の高い
金属、例えば、Ａｇ、Ｓｎ、Ｂｉ又はＣｕ等に変更した
Ｓｎ合金を用いて電気鍍金することで、Ｐｂを含有しな
い半田接合性の良いＳｎ合金を鍍金した半田付け用回路
基板を提供することを目的とする。[0004] The present invention has been made in view of the above circumstances, and when applying a solder plating to a circuit pattern of a circuit board for soldering such as TAB tape, CSP, BGA, COF, etc., the Sn-Pb alloy is used. Pb was electroplated with another highly safe metal, such as Ag, Sn, Bi, or a Cu alloy that was changed to Cu or the like, so that a Sn alloy with good Pb-free soldering properties was plated. An object of the present invention is to provide a circuit board for soldering.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
に、請求項１に記載の発明は、絶縁性基板上に回路パタ
ーンを形成してなる半田付け用回路基板において、前記
回路パターン上の全面又は一部面にＰｂを含有しないＳ
ｎ合金を電気鍍金したことを特徴とする。According to one aspect of the present invention, there is provided a circuit board for soldering comprising a circuit pattern formed on an insulating substrate. S that does not contain Pb on the entire or partial surface
It is characterized in that an n alloy is electroplated.
【０００６】請求項１に記載の発明によれば、Ｐｂを含
有しないＳｎ合金鍍金を行なうことで人体への毒性及び
環境汚染の問題を解消すると共に、従来のＰｂを含有し
たＳｎ合金鍍金と同等の半田付け性を有する回路基板を
得ることが可能になる。According to the first aspect of the present invention, the problem of toxicity to the human body and environmental pollution is eliminated by performing the Sn alloy plating containing no Pb, and is equivalent to the conventional Sn alloy plating containing Pb. Thus, it is possible to obtain a circuit board having solderability.
【０００７】又、請求項２に記載の発明は、前記回路パ
ターン上の全面又は一部面に純Ｓｎ、Ｓｎ‐Ｂｉ、Ｓｎ
‐Ａｇ、Ｓｎ‐Ｚｎ又はＳｎ‐Ｃｕの何れかを電気鍍金
したことを特徴とする。Further, according to a second aspect of the present invention, pure Sn, Sn-Bi, Sn
-Ag, Sn-Zn or Sn-Cu is electroplated.
【０００８】請求項２に記載の発明によれば、具体的な
Ｓｎ合金を特定し、これらのＳｎ合金を用いて電気鍍金
を行うことで、ＴＡＢテープ等の半田付け用回路基板の
Ｐｂフリー化が実現可能となる。According to the second aspect of the present invention, specific Sn alloys are specified, and electroplating is performed using these Sn alloys, so that a circuit board for soldering such as a TAB tape is made Pb-free. Can be realized.
【０００９】さらに、請求項３に記載の発明は、前記回
路パターン上の全面又は一部面にＢｉ、Ａｇ、Ｚｎ又は
Ｃｕの何れか二元素とＳｎとの三元素合金を電気鍍金し
たことを特徴とする。Further, the invention according to claim 3 is characterized in that a three-element alloy of Bi, Ag, Zn or Cu and Sn is electroplated on the entire or partial surface of the circuit pattern. Features.
【００１０】請求項３に記載の発明によっても、ＴＡＢ
テープ等の半田付け用回路基板のＰｂフリー化が実現可
能となる。According to the third aspect of the present invention, TAB
Pb-free circuit boards for soldering such as tapes can be realized.
【００１１】又、請求項４に記載の発明は、前記半田付
け用回路基板に、ＴＡＢテープ、ＣＳＰ、ＢＧＡ、ＣＯ
Ｆ、ＰＣＢ及びＦＰＣを含むことを特徴とする。Further, the invention according to claim 4 is that the circuit board for soldering includes a TAB tape, CSP, BGA, CO
It is characterized by including F, PCB and FPC.
【００１２】請求項４に記載の発明によれば、広範囲の
半田付け用回路基板においてＰｂフリー化が可能にな
る。According to the fourth aspect of the present invention, Pb-free can be achieved in a wide range of circuit boards for soldering.
【００１３】[0013]
【発明の実施の形態】以下、本発明の半田付け用回路基
板の実施形態について、図面に基づいて説明する。図１
には、回路パターンを形成した半田付け用回路基板であ
る所謂２メタルＴＡＢテープ１の平面図が示されてい
る。しかしながら、本発明は、フレキシブルなポリイミ
ド等を用いたＴＡＢテープ、ＣＳＰ、ＢＧＡ，ＦＰＣ、
又、ガラスエポキシ等のリジッドな基板を用いた所謂多
層基板等、広範囲にわたって適用可能である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the circuit board for soldering according to the present invention will be described with reference to the drawings. FIG.
1 shows a plan view of a so-called two-metal TAB tape 1 which is a circuit board for soldering on which a circuit pattern is formed. However, the present invention relates to TAB tape using flexible polyimide or the like, CSP, BGA, FPC,
Further, the present invention can be applied to a wide range such as a so-called multilayer substrate using a rigid substrate such as glass epoxy.
【００１４】上記２メタルＴＡＢテープ１は、４８ｍｍ
幅のベースフィルムに１８μｍ厚の銅箔をラミネートし
た基材（ユーピレックス‐Ｓ ５０μｍ厚 接着剤 東
レ７１００タイプ １２μｍ厚）を用いている。具体的
なＳｎ合金鍍金処理に関しては、回路パターン形成後、
ソルダーレジストを印刷し、無電解Ｓｎ鍍金を０．５μ
ｍ程度付着した２メタルＴＡＢテープ１に、Ｓｎ‐Ｂｉ
合金鍍金を電気鍍金により施すことになる。The 2-metal TAB tape 1 is 48 mm
A base material (upilex-S, 50 μm thick adhesive, Toray 7100 type, 12 μm thick) laminated with a 18 μm thick copper foil on a base film having a width is used. Regarding the specific Sn alloy plating process, after forming the circuit pattern,
Print solder resist, electroless Sn plating 0.5μ
m to the two-metal TAB tape 1 with Sn-Bi
Alloy plating is performed by electroplating.
【００１５】２メタルＴＡＢテープ１の幅方向両端部に
は、長手方向に沿って等間隔にスプロケットホール２が
形成されている。このスプロケットホール２は角穴であ
り、配線（リード）の形成時にＴＡＢテープの搬送に用
いられる。２メタルＴＡＢテープ１の中央部にはデバイ
スホール８が穿設されており、その周囲部にはインナー
リード部１１が形成されている。又、スプロケットホー
ル２の方向へ入力アウターリード部５及び出力アウター
リード部６が形成されており、入力アウターリード部５
の中間部にはアウターリードホール１０が穿設されてい
る。そして、２メタルＴＡＢテープ１の中央部にはソル
ダーレジスト３が形成されている。At both ends in the width direction of the two-metal TAB tape 1, sprocket holes 2 are formed at equal intervals along the longitudinal direction. The sprocket hole 2 is a square hole, and is used for transporting a TAB tape at the time of forming a wiring (lead). A device hole 8 is formed in the center of the two-metal TAB tape 1, and an inner lead 11 is formed around the device hole. Further, an input outer lead portion 5 and an output outer lead portion 6 are formed in the direction of the sprocket hole 2, and the input outer lead portion 5 is formed.
An outer lead hole 10 is formed at an intermediate portion of the outer lead hole 10. A solder resist 3 is formed at the center of the two-metal TAB tape 1.
【００１６】上記２メタルＴＡＢテープ１において、入
力アウターリード部５のみを鍍金液に浸して、アウター
リードホール１０内の入力アウターリード部５にＳｎ‐
Ｂｉ鍍金を形成する。出力アウターリード部６、インナ
ーリード部１１及びソルダーレジスト３塗布エリアには
Ｓｎ‐Ｂｉ鍍金は付着しない。In the two-metal TAB tape 1, only the input outer lead portions 5 are immersed in a plating solution, and Sn-
Bi plating is formed. Sn-Bi plating does not adhere to the output outer lead portion 6, the inner lead portion 11, and the solder resist 3 application area.
【００１７】鍍金液は石原薬品株式会社製ＰＦ‐０５Ｍ
プロセスを使用し、Ｂｉの含有率を１質量％、３質量％
又は５質量％とし、５μｍ又は７μｍの厚さのＳｎ‐Ｂ
ｉ合金鍍金を導体上に形成した。アノードとして９９．
９９％純Ｓｎを使用し、鍍金液温度を４０℃、電流密度
（ＤＫ）を１０Ａ／ｄｍ２とした条件で、鍍金液を撹拌
しながら電気鍍金を行なった。The plating solution is PF-05M manufactured by Ishihara Chemical Co., Ltd.
Using a process, the content of Bi is 1% by mass and 3% by mass.
Or 5 mass%, Sn-B having a thickness of 5 μm or 7 μm
An i-alloy plating was formed on the conductor. 99. as anode
Electroplating was carried out using 99% pure Sn under the conditions of a plating solution temperature of 40 ° C. and a current density (DK) of 10 A / dm 2 while stirring the plating solution.
【００１８】得られたＳｎ−Ｂｉ合金皮膜はほぼ狙い通
りのものであり、半田浴に浸して濡れ性を評価したとこ
ろ、Ｓｎ‐Ｐｂ合金皮膜と同等レベルの半田濡れ性が得
られた。回路パターン上の密着性も良好で、変色、斑等
もなく外観も良好な半光沢鍍金皮膜が得られた。Ｎｏ．
１〜６のサンプル（１．５５ｍｍ×１５ｍｍ長さ）の測
定結果を表１に示す。ここで、Ｂｉ組成と鍍金厚さは蛍
光Ｘ線により測定した。The obtained Sn—Bi alloy film was almost as intended. When the film was immersed in a solder bath and the wettability was evaluated, the same level of solder wettability as that of the Sn—Pb alloy film was obtained. A semi-glossy plating film having good adhesion on the circuit pattern and good appearance without discoloration or spots was obtained. No.
Table 1 shows the measurement results of the samples 1 to 6 (1.55 mm × 15 mm length). Here, the Bi composition and the plating thickness were measured by X-ray fluorescence.
【００１９】[0019]
【表１】 [Table 1]
【００２０】又、１５０℃×３ｈｒ加熱後、Ｓｎ６３質
量％、Ｐｂ３７質量％のＳｎ−Ｐｂ合金からなる２３０
℃の半田浴中に、Ｎｏ．１〜６のサンプルを５秒間フラ
ックスなしで浸したが、１００％のエリアで半田が濡れ
ており、良好な結果が得られた。After heating at 150 ° C. for 3 hours, 230% of a Sn—Pb alloy of 63% by mass of Sn and 37% by mass of Pb is used.
No. in a solder bath at Samples 1 to 6 were dipped for 5 seconds without flux, but the solder was wet in 100% of the area, and good results were obtained.
【００２１】Ｓｎ‐Ｂｉ合金の他にＳｎ‐Ｃｕ合金、Ｓ
ｎ‐Ａｇ合金、Ｓｎ‐Ｚｎ合金或いは純Ｓｎによる電気
鍍金、又はＳｎベースのＣｕ、Ａｇ、Ｚｎ何れか２元素
を含む３元素合金による電気鍍金でも、同様の結果を得
ることが可能である。In addition to Sn—Bi alloy, Sn—Cu alloy, S
Similar results can be obtained by electroplating using an n-Ag alloy, Sn-Zn alloy or pure Sn, or electroplating using a Sn-based three-element alloy containing any two elements of Cu, Ag, and Zn.
【００２２】[0022]
【発明の効果】本発明によれば、ＰｂフリーＳｎ合金鍍
金を施すことでＰｂを含有しない半田接合の良好な半田
付け用回路基板を得ることができ、人体に有害なＰｂの
環境への流出を防止できる。又、二次的な効果として、
Ｓｎ合金鍍金でＰｂを含有していないため、ＩＣに影響
を及ぼすＰｂから放出されるα線を排除することが可能
となった。According to the present invention, by applying Pb-free Sn alloy plating, a Pb-free soldering circuit board having good solder joints can be obtained, and Pb harmful to the human body leaks into the environment. Can be prevented. Also, as a secondary effect,
Since Pb was not contained in the Sn alloy plating, it was possible to eliminate α-rays emitted from Pb affecting IC.
【図１】ＰｂフリーＳｎ合金鍍金を施すＴＡＢテープの
一部切欠平面図である。FIG. 1 is a partially cutaway plan view of a TAB tape subjected to Pb-free Sn alloy plating.
１ ＴＡＢテープ ５ 入力アウターリード部 ６ 出力アウターリード部 １１ インナーリード部 DESCRIPTION OF SYMBOLS 1 TAB tape 5 Input outer lead part 6 Output outer lead part 11 Inner lead part
───────────────────────────────────────────────────── フロントページの続き (72)発明者 牧田 秀明 埼玉県上尾市原市1333−２ 三井金属鉱業 株式会社総合研究所内 (72)発明者 松村 保範 埼玉県上尾市原市1333−２ 三井金属鉱業 株式会社総合研究所内 Ｆターム(参考） 4K024 AA07 AA21 BB11 CA04 CA06 CB06 5E319 AA03 AC01 BB02 CC33 GG03 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hideaki Makita 1333-2, Hara-shi, Ageo-shi, Saitama Mitsui Metal Mining Co., Ltd. (72) Inventor Yasunori Matsumura 1333-2, Hara-shi, Ageo-shi, Saitama Mitsui Metal Mining 4K024 AA07 AA21 BB11 CA04 CA06 CB06 5E319 AA03 AC01 BB02 CC33 GG03
Claims (4)
なる半田付け用回路基板において、前記回路パターン上
の全面又は一部面にＰｂを含有しないＳｎ合金を電気鍍
金したことを特徴とする半田付け用回路基板。1. A circuit board for soldering comprising a circuit pattern formed on an insulating substrate, wherein an Sn alloy containing no Pb is electroplated on the entire or partial surface of the circuit pattern. Circuit board for soldering.
純Ｓｎ、Ｓｎ‐Ｂｉ、Ｓｎ‐Ａｇ、Ｓｎ‐Ｚｎ又はＳｎ
‐Ｃｕの何れかを電気鍍金したことを特徴とする請求項
１に記載の半田付け用回路基板。2. Pure Sn, Sn—Bi, Sn—Ag, Sn—Zn or Sn on the entire or partial surface of the circuit pattern.
The circuit board for soldering according to claim 1, wherein any one of -Cu is electroplated.
Ｂｉ、Ａｇ、Ｚｎ又はＣｕの何れか二元素とＳｎとの三
元素合金を電気鍍金したことを特徴とする請求項１に記
載の半田付け用回路基板。3. The circuit pattern according to claim 1, wherein a three-element alloy of Bi, Ag, Zn, or Cu and Sn is electroplated on the entire or partial surface of the circuit pattern. Circuit board for soldering.
ープ、ＣＳＰ、ＢＧＡ、ＣＯＦ、ＰＣＢ及びＦＰＣを含
むことを特徴とする請求項１乃至３の何れかに記載の半
田付け用回路基板。4. The soldering circuit board according to claim 1, wherein the soldering circuit board includes a TAB tape, CSP, BGA, COF, PCB, and FPC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000403322A JP2002204056A (en) | 2000-12-28 | 2000-12-28 | Circuit board for soldering |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000403322A JP2002204056A (en) | 2000-12-28 | 2000-12-28 | Circuit board for soldering |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002204056A true JP2002204056A (en) | 2002-07-19 |
Family
ID=18867471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000403322A Pending JP2002204056A (en) | 2000-12-28 | 2000-12-28 | Circuit board for soldering |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002204056A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100495184B1 (en) * | 2002-12-02 | 2005-06-14 | 엘지마이크론 주식회사 | A tape substrate and tin plating method of the tape substrate |
| KR100511965B1 (en) * | 2002-12-13 | 2005-09-02 | 엘지전자 주식회사 | A tin plating method of the tape substrate |
| CN102014586A (en) * | 2010-11-24 | 2011-04-13 | 深南电路有限公司 | Method for gold-plating long and short gold fingers |
-
2000
- 2000-12-28 JP JP2000403322A patent/JP2002204056A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100495184B1 (en) * | 2002-12-02 | 2005-06-14 | 엘지마이크론 주식회사 | A tape substrate and tin plating method of the tape substrate |
| KR100511965B1 (en) * | 2002-12-13 | 2005-09-02 | 엘지전자 주식회사 | A tin plating method of the tape substrate |
| CN102014586A (en) * | 2010-11-24 | 2011-04-13 | 深南电路有限公司 | Method for gold-plating long and short gold fingers |
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