JP2002203373A - Boost regulation method and information reproducing device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a boost regulation method which is capable of making rapid boost regulation with high accuracy regardless of patterns recorded on a recording medium and an information reproducing device using the same. SOLUTION: A signal forming section 30 forms a regenerative signal boosted at the boost level set by a CPU 60 across CPUI/F62 by amplifying the signal by an AGC to a specified level. The regenerative signal is binarized by a data slicer 40. The data slicer 40 counts the binarized data according to the lengths of the respective logic levels of the binarized data in a variable Up count unit and a Down count unit. Since comparative levels vary, the ratios different from each other are set in order to maintain the specified ratio of the first and second periods of the logic levels of the binarized data according to the boost levels of the regenerative signal and the optimum boost level is determined from the difference between the respective comparative levels and is set in the signal forming section 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boost adjusting method and an information reproducing apparatus using the same, and more particularly, to a boost adjusting method for adjusting a boost level of a reproduced signal using a data slicer for performing a binarization process of the reproduced signal. The present invention relates to a method and an information reproducing apparatus in which a boost level is adjusted using the method.

[0002]

BACKGROUND ART Problems to be Solved by the Invention CD (Co
mpact Disc) and DVD (Digital Versatile Disc / Digit)
Discs (information recording media and recording media in a broad sense) such as an optical disc such as an al Video Disc are indispensable for multimedia informationization. An information reproducing apparatus that generates a reproduction signal obtained by reproducing information recorded on such a disc is required to reproduce recorded information without error.

Therefore, in an information reproducing apparatus, a reproduced signal generated by reading information recorded on a recording medium is amplified, passed through a high-frequency emphasis filter (equalizer), and then binarized (processed) by a data slicer. The quality of the reproduced signal is improved by performing error correction through an error correction circuit.

FIG. 12 shows an outline of the main components of such a conventional information reproducing apparatus.

In this information reproducing apparatus, a reproduced signal (RF signal) detected by a pickup (not shown) is amplified by a preamplifier 10 and absorbs a decrease in output, via an automatic gain control (AGC) for maintaining a constant gain. The signal is input to a high-frequency emphasizing filter (equalizer) 12 that boosts the vicinity of a high-frequency component of the RF signal whose amplitude is extremely reduced due to removal of high-frequency noise of the RF signal and intersymbol interference.

[0006] The equalizer 12 performs the waveform equalization by boosting in this manner, whereby the fluctuation (jitter) in the time direction is obtained.
Improves the accuracy of detecting digital information caused by dull components and waveforms.

When the waveform is equalized by the equalizer 12, the data is binarized by the data slicer 14 and input to the PLL 18 as binarized data 16. The PLL 18 extracts a clock signal 20 from the binary data 16 and generates binary synchronization data 22 from the clock signal 20 and the binary data 16. After that, the clock signal 20 and the binary synchronization data 22 are sent to the error correction circuit 24. The error correction circuit 24 detects an error in the binary synchronization data 22, and corrects the error within the range using a given error correction method.

The equalizer 12 is composed of a filter circuit composed of a combination of several low-pass filters capable of varying the cutoff frequency (fc) while suppressing the group delay fluctuation, and a boost circuit capable of varying the amount of boost. In order to suppress the group delay characteristics at the time of boosting, the cutoff frequencies of the boost circuit and the low-pass filter are almost the same.

For example, in the case of an optical disk, the RF signal input to the data reproducing apparatus having such a configuration is used to reduce laser power due to laser noise in a pickup, photodetection system noise, circuit noise such as a preamplifier, or mechanical factors. Along with the increase of such noises, furthermore, disk noise mainly due to disk characteristics, noise due to waveform interference, asymmetry, crosstalk, etc., cause fluctuations in the time direction (hereinafter referred to as jitter).

As described above, the equalizer 12 has a role of removing high-frequency noise and boosting the high-frequency component of the RF signal that has been reduced by intersymbol interference. At this time, if the boost amount is small, the waveform interference of the high frequency component of the RF signal increases and the jitter increases. On the contrary, if the boost amount is large, the jitter due to the phase distortion of the low frequency component of the RF signal increases.

Therefore, the boost amount is optimally adjusted so as to minimize the jitter amount, and various technologies relating to a data reproducing apparatus for performing such an optimal adjustment of the boost amount have been proposed.

For example, in Japanese Patent Application Laid-Open No. H10-55503, "Information Storage Device", a close-packed recording pattern recorded at a predetermined position on a disk for locking a PLL and a random pattern recorded in a user data area are used. There is disclosed a technique of comparing the detected amplitudes to determine a boost level.

However, in a recording medium such as a CD or a DVD, the position of the repetition of the closest pattern is unknown. Therefore, in a recording medium such as a CD or a DVD, the amplitude in both patterns cannot be sampled.
There is a problem that the boost level cannot be adjusted based on this.

For example, Japanese Patent Application Laid-Open No. 11-328858 discloses a technique for adjusting a boost level based on a phase error voltage or an error rate.

However, the level of the phase error voltage greatly varies depending on the reproduction position of the recording medium. In particular, if a flaw or the like is present on the recording medium, the variation in the adjustment result using the flaw becomes large, and high-precision adjustment cannot be performed. Therefore, it is necessary to accurately grasp the phase error voltage by comparing the same location (address) of the recording medium.

Similarly, the level of the error rate greatly varies depending on the reproduction position of the recording medium, and the error rate can be compared at the same location (address) of the recording medium or by performing long-time sampling. It was necessary to accurately grasp and reflect it on the adjustment of the boost level.

Therefore, the present invention has been made in view of the above technical problems, and an object of the present invention is to provide a high-precision boost in a short time regardless of a pattern recorded on a recording medium. An object of the present invention is to provide a boost adjustment method capable of performing adjustment and an information reproducing apparatus using the same.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method in which the ratio of the lengths of the first and second periods of the first and second levels of the binary data is a given ratio. A boost level adjusting method for adjusting a boost level for boosting a reproduction signal supplied to a data slicer for performing a binarization process on the basis of a comparator level adjusted to be equal to The comparison level difference between the first state in which the ratio of the lengths of the second periods is equal and the second state in which the ratio of the lengths of the first and second periods is different is obtained. The boost level of the reproduced signal is set so that the compared level difference becomes a target comparator level difference corresponding to the target boost level of the reproduced signal.

Here, the reproduction signal is, for example, a signal read from an information recording medium, is AC-coupled, and changes with reference to a bias potential level.

Further, in the present invention, a data slicer capable of changing the ratio of the length of the first and second periods of the first and second levels of the binarized data by changing the compare level is used. The data slicer is not limited to the realizing means as long as the ratio of the lengths of the first and second periods can be changed.

The target boost level is optimal for reproduction which is uniquely determined from, for example, the shape of the pits of the recording medium on which the information to be reproduced is recorded, the light intensity distribution of the light spot, and the recorded modulation code. Boost level.

In the present invention, the first data slicer is used.
Is a state where the ratio of the lengths of the first and second periods of the binarized data is adjusted to be equal by the data slicer, and a second state is where the first and second periods of the binarized data are adjusted. The state in which the length ratio of the second period is adjusted to be different is set. Then, the boost level of the reproduction signal is set such that the difference between the comparator levels serving as the reference values of the binarized data in each state becomes the comparator level difference corresponding to the target boost level.
Thus, since the above-described comparison level difference and the amplitude of the reproduction signal have a monotonically increasing relationship, it is possible to set a boost level that determines the amplitude of the reproduction signal based on the comparison level difference. In particular, when the optimum boost level for reproduction determined uniquely from the pit shape of the recording medium on which the information to be reproduced is recorded, the light amount distribution of the light spot, the recorded modulation code, etc. is known, the boost is determined. The optimum boost level can be adjusted as a result by controlling the level to be the optimum boost level and a control level difference corresponding to the optimum boost level.

Therefore, the optimum boost adjustment can be performed without referring to the phase error voltage or error rate which greatly varies depending on the reproduction position of the recording medium when the position of the repetition of the densest pattern is unknown on the recording medium. it can. This means that it is possible to adjust the boost of an information reproducing apparatus such as a CD or DVD having no close-packed pattern repetition position, such as a recording medium. It means you can do it.

Further, in the present invention, the data slicer may compare the reproduced signal with a first compare level to compare the reproduced signal with a first compare level.
A comparator for generating binarized data, and counting up to a given up-count unit when the binarized data is at a first level, and a given down-count unit when the binarized data is at a second level And a D / A converter that converts the count value into an analog signal and outputs the analog value as the first compare level.

According to the present invention, the comparator counts up to a given up-count unit when the binary data is at the first level, and the given down-count unit when the binary data is at the second level. By using a digital level slicer loop-controlled by a comparator level generator and a D / A converter that counts down to generate a count value, it is possible to perform high-precision boost adjustment with good controllability.

Further, the present invention uses the count value counted by the compare level generating means in a first up-count unit and a down-count unit as the compare level in the first state. The present invention is characterized in that the count value counted by the comparator level generating means in the second up-count unit and the down-count unit is used as the compare level.

Here, a first up-count unit and a down-count unit are set for the digital data slicer as the first state described above, and the count value counted by the comparator level generation means is set to the first state. Is used as the comparison level.

Further, a second up-count unit and a down-count unit are set for the digital data slicer as the above-mentioned second state, and the count value counted by the comparator level generating means is set to the second state. Used as compare level.

[0029] Thus, the comparator level difference can be easily obtained as the difference between the count values, so that a more accurate boost adjustment can be executed.

Further, the present invention is a boost adjusting method for adjusting a boost level for boosting a reproduction signal supplied to a data slicer for performing a binarization process based on a comparator level to which an offset value is added. Detecting the duty ratio of the binarized data generated by the data slicer, and determining that the duty ratio of the binarized data binarized by the data slicer corresponds to a target boost level of the reproduced signal. A boost level of the reproduction signal is set so as to obtain a duty ratio.

Here, the duty ratio refers to the ratio of the lengths of the periods of the first and second levels, which are the logical levels of the binary data.

Further, in the present invention, a data slicer for performing a binarization process of a reproduced signal at a comparator level having a certain offset is used.

According to the present invention, the data slicer detects the duty ratio of the binarized data binarized at the comparator level to which a certain offset value has been added, and detects the duty ratio corresponding to the target boost level. The boost level of the reproduction signal is set so that the ratio is obtained.

Thus, since the duty ratio of the binary data and the amplitude of the reproduction signal have a fixed relationship, the boost level for determining the amplitude of the reproduction signal can be set based on the duty ratio. In particular, if the optimum boost level for reproduction determined uniquely from the pit shape of the recording medium on which the information to be reproduced is recorded, the light spot distribution of the light spot, the recorded modulation code, etc. is known, the boost is determined. The optimum boost level can be adjusted by controlling the level to be the optimum boost level and the duty ratio corresponding to the optimum boost level.

Therefore, when the position of the repetition of the densest pattern on the recording medium is unknown, or without referring to a phase error voltage or an error rate which fluctuates greatly depending on the reproduction position of the recording medium, the optimum boost adjustment can be performed. it can. This means that it is possible to adjust the boost of an information reproducing apparatus such as a CD or DVD having no close-packed pattern repetition position, such as a recording medium. It means you can do it.

In the present invention, the duty ratio is detected as first and second count values corresponding to the lengths of the first and second periods of the first and second levels of the binary data. , As the boost level of the reproduction signal,
And a boost level corresponding to the difference between the second count value and the second count value.

According to the present invention, the duty ratio is detected as the first and second count values corresponding to the lengths of the first and second periods of the first and second levels of the binary data. Therefore, the duty ratio can be detected with a simple configuration, the boost level to be set simply by the CPU or the like can be determined, and the boost adjustment can be performed with high accuracy.

Also, in the present invention, the data slicer includes a first comparator for comparing the reproduced signal with a first comparator level to generate first binary data, A comparator level generating means for counting up when the digitized data is at the first level and counting down when the first binary data is at the second level to generate a comparator level corresponding to the count value; A first D / A converter that converts a comparator level into an analog signal and outputs the analog signal as the second comparator level, an adder that adds a given offset value and the count value, and an addition result of the adder And a second D / A converter for converting the reproduced signal and the second comparator level into an analog signal and outputting the analog signal as a second comparator level. And a second comparator for generating a second binary data compare, the duty ratio of the second binary data, characterized in that it is detected.

According to the present invention, a digital data slicer having a control loop including a first comparator, a comparator level generating means, and a first D / A converter is provided, and a given offset is provided outside the control loop. Since the binarization is performed at the compare level obtained by adding the values,
Binary data can be generated based on a target level without offsetting the added offset value as a disturbance.

Further, by using such a digital data slicer, it is possible to perform high-precision boost adjustment with good controllability.

Further, in the present invention, the comparator level generating means is characterized in that the count-up unit and the count-down unit have the same value.

According to the present invention, the configuration of the compare level generating means can be simplified.

Also, the present invention is characterized in that the reproduced signal is a signal amplified to a certain level by an automatic gain control means.

Here, the automatic gain control means is, for example, A
GC.

According to the present invention, since the reproduction signal amplified to a certain level by the automatic gain control means is used, for example, the shape of the pit of the recording medium on which the information to be reproduced is recorded, the light It is possible to enhance the accuracy of the optimum boost level for reproduction that can be uniquely determined from the light amount distribution of the spot, the recorded modulation code, and the like, and as a result, the boost level value adjusted can be further optimized. .

Further, the present invention is characterized in that the reproduced signal is modulated so that a DSV (Digital Sum Value) of a modulation code becomes zero.

Here, the modulation so that the DSV value of the modulation code becomes 0 means that the period of the logical level "H" and the period of the logical level "L" of the modulation code are per unit time. It means that they are modulated to be equal.

Therefore, according to the present invention, this DSV
CD on which information modulated so that the value of “0” becomes 0
The optimization of the boost level of the reproduction information of an optical disk such as a DVD or an optical disk can be achieved.

The present invention is also an information reproducing apparatus for reproducing information recorded on a recording medium, comprising: means for reading the information recorded on the recording medium to generate the reproduction signal; The automatic gain control means for amplifying to a certain level, the boost means for boosting the signal amplified by the automatic gain control means in accordance with the boost level adjusted by any one of the boost adjustment methods, and the boost means And a data slicer for binarizing the signal boosted by the data slicer.

Here, the information reproducing apparatus is preferably applied to a disk device, an optical disk device and the like, but may be applied to other various electronic devices. In that case, a function capable of recording information may be provided.

According to the present invention, when the position of the repetition of the densest pattern on the recording medium is unknown, or without referring to the phase error voltage or the error rate which greatly varies depending on the reproduction position of the recording medium, the optimum boost adjustment can be performed. And an information reproducing apparatus for performing the above. This means that it is possible to provide an information reproducing apparatus capable of boost adjustment of an information reproducing apparatus such as a CD or DVD having no close-packed pattern repetition position like a recording medium, and to shorten the adjustment time. This means that it is possible to provide an information reproducing apparatus capable of performing highly accurate boost adjustment.

[0052]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> 1. First Embodiment 1. Information Reproducing Apparatus According to First Embodiment FIG. 1 shows an outline of a main configuration of an information reproducing apparatus according to a first embodiment.

The part relating to the boost adjustment of the information reproducing apparatus according to the first embodiment includes a signal generator 30, a data slicer 40, a CPU 60, and a CPU interface (InterFace: hereinafter abbreviated as I / F) 62.

A pick-up detection signal detected by a not-shown pick-up is input to a signal generation unit 30. The signal generation unit 30 generates a reproduction signal obtained by equalizing the waveform of the pickup detection signal and supplies the reproduction signal to the data slicer 40.

Hereinafter, it is assumed that the reproduced signal is modulated so that the DSV (Digital Sum Value) of the modulation code becomes 0. That is, when binarized like an optical disk such as a CD or DVD, the modulation code is modulated so that the period of the logical level "H" and the period of the logical level "L" are equal per unit time. Shall be

The data slicer 40 binarizes the reproduction signal at the slice level (comparative level) controlled and adjusted to generate binarized data. A demodulation unit connected downstream of the data slicer 40 performs a demodulation process based on the binarized data.

The data slicer 40 measures the length of the period of each logic level of the binary data by using a counter for the binary data of the reproduced signal modulated so that the DSV value of the modulation code becomes 0, for example. Is a digital data slicer that generates a count value in accordance with. And controls the slice level (compare level) based on the count value.

Further, the CPU 60 includes a CPU I / F 6
2, the setting of the count unit to be set in the counter and the reading of the above-mentioned count value are performed, and based on this, the boost level can be set for the signal generator 30. .

The signal generator 30 includes an RF signal generator 32,
It has the function of an automatic gain controller (hereinafter abbreviated as AGC) that absorbs a decrease in output and keeps the gain constant. It removes high-frequency noise and removes signals whose amplitude is extremely reduced due to intersymbol interference. It includes a high-frequency emphasizing filter (equalizer) 34 for boosting the vicinity of high-frequency components, a digital-to-analog converter (hereinafter abbreviated as D / A converter, DAC) 36, and a boost level setting register 38.

A pick-up detection signal detected by a pick-up (not shown) is amplified by an RF signal generating section 32 to generate a reproduction signal RF. The reproduced signal RF is amplified to a certain level by the AGC / equalizer 34, and then boosted around the high-frequency component at the set boost level, and output to the data slicer 40.

The boost level setting register 38 stores the CP
The CPU 60 (more specifically, via the U I / F 62
The boost level is set by the firmware operating on the CPU 60). The boost level set in the boost level setting register 38 is converted into an analog signal by the DAC 36 and set to the AGC equalizer 34.

In the DAC 36, a PWM (Pulse Wi-Fi) is used.
It is also possible to obtain an analog signal by dth modulation) control.

The reproduction signal RF supplied near the high frequency component supplied from the signal generation unit 30 is AC-coupled via a capacitor C, and has a potential level biased by a bias voltage connected via a resistor R. It is converted to a signal that changes to the reference. This signal is input to the non-inverting input terminal (+ terminal) of the comparator 42. In a broad sense, a signal that changes based on a biased potential level may be referred to as a reproduction signal.

A comparator level voltage is supplied to an inverting input terminal (−terminal) of the comparator 42. The comparator 42 outputs binary data in which logic levels “H” and “L” are switched based on the potential difference between the non-inverting input terminal and the inverting input terminal. The binarized data is also input to the counter 44.

The counter 44 has a clock CL (not shown).
In synchronization with the K, the Up count register 46 according to the length of the first period in which the logical level of the binary data is “H”
The count value is incremented by the up-count unit set in. Further, the counter 44 detects the clock C
In synchronization with LK, the count value is counted down in units of down-counts set in the Down count register 48 according to the length of the second period in which the logic level of the binary data is “L”.

For example, the Up count register 46 and Dow
Assuming that the ratio between the count-up unit and the count-down unit set in the n-count register 48 is 1: 1, the ratio of the length of the period of the logical levels “H” and “L” of the binarized data is 1: 1. Can be generated. Also, the Up count register 46 and Do
Assuming that the ratio between the count-up unit and the count-down unit set in the wn count register 48 is 2: 3, the ratio between the lengths of the periods of the logical levels “H” and “L” of the binarized data is 3: 2. Can be generated.

The result of counting by the counter 44 is
0 is supplied.

The DAC 50 converts the count result of the counter 44 into an analog signal, converts it into a comparator level voltage, and supplies it to the inverting input terminal of the comparator 42.

The counter 44 is, in principle, the U
p count register 46, Down count register 4
8, the counter control logic 52, 16-bit Up
/ Down counter 54 is included.

The counter control logic 52 controls the 16-bit Up / Down counter 54 based on the binarized data, and supplies the 16-bit count value to the DAC 50. At that time, according to the logical level of the binarized data,
The count-up or count-down is performed in units of the count value set in the Up count register 46 or the Down count register 48.

FIG. 2 shows a specific example of the configuration of such a counter 44.

The counter 44 includes a combinational circuit 70 and first to sixteenth flip-flops (Flip-Flop: hereinafter F
Abbreviated as F. ) 72 _{1 to} 72 ₁₆ to implement the functions of the counter control logic 52 and the 16-bit Up / Down counter 54.

The combinational circuit 70 is composed of a logic element which is a component of the logic circuit, and includes a comparator output from the comparator 42, a 16-bit count value, an Up count unit from the Up count register 46, and a Down count from the Down count register 48. The unit is entered.

In addition to this, the combination circuit 70 sets a set band from a control unit (not shown) and inputs a defect detection signal indicating that a defect has been detected as a reference signal.

When the output of the comparator is at the logic level (first level) “H”, the combinational circuit 70 sets the value of U indicated by the register value set in the Up count register 46 to U.
A 16-bit addition result is generated by counting up a 16-bit count value in units of p counts, and the respective bit values of the 16-bit addition result are respectively referred to as first to sixteenth F
F72 supplied to the _{1-72 16.}

When the comparator output is at the logical level (second level) “L”, the combinational circuit 70
A 16-bit subtraction result obtained by counting down the 16-bit count value is generated in units of Down count indicated by the register value set in the own count register 48, and the respective bit values of the 16-bit subtraction result are respectively referred to as first to first bits. 16 is supplied to the FF72 ₁ ~72 ₁₆ of.

The first to sixteenth FFs 72 _{1 to} 72 ₁₆ are connected to the combinational circuit 7 at the rising edge of the clock CLK.
Each bit value of the 16-bit addition / subtraction result supplied from 0 is latched. The 16-bit latch data latched by the _first to sixteenth FFs 72 _{1 to} 72 ₁₆ is supplied to the DAC 50 connected to the subsequent stage and also supplied to the combination circuit 70.

The combination circuit 70 includes a CPU (not shown).
Based on the set band set by the above or the reference signal, regardless of the Up count unit indicated by the register value set in the Up count register 46 and the Down count unit indicated by the register value set in the Down count register 48 , The 16-bit value is updated in new count-up units and new count-down units.

For example, when the set band is set high or when the reference signal is in the active state, the combination circuit 70 sets the count-up unit and the count-down unit to a large value. The combination circuit 70
Sets the count-up unit and the count-down unit to small values when the set bandwidth is set low and the reference signal is in an inactive state.

As described above, by changing the unit of count-up and the unit of count-down in the combination circuit 70, the band can be changed.

When the setting band is set high or when the reference signal is in an active state, by setting a large value in units of count-up and count-down, the counter result is easily reflected, and the slice level of the reproduced signal is reduced. In addition, it is possible to quickly follow a change due to disturbance or the like, and to perform various controls at an optimal slice level immediately after the disturbance is added.

On the other hand, when the set band is set low and the reference signal is inactive, setting a small value for the count-up unit and the count-down unit makes it difficult to reflect the counter result, and the slice level of the reproduced signal is reduced. Can be generated at a stable slice level so as not to be affected by the noise of the modulation component of the reproduction signal RF.

The data slicer 40 having such a configuration is as follows.
Although the modulation code is originally modulated to have a DSV value of 0, even if the DSV value of the modulation code does not become 0 for some reason, the Up count register 46 and the Down count register By setting an appropriate count unit to 48, it is possible to set an optimum comparator level such that the DSV value of the modulation code becomes zero.

As described above, the Up count register 46,
By changing the comparator level determined by the count unit set in the Down count register 48, the lengths of the first and second periods, which are the periods of the logical levels “H” and “L” of the binarized data, are changed. Can be changed.

2. Features of the First Embodiment In the first embodiment, for example, the shape of a pit of a recording medium on which information to be reproduced is recorded, the light amount distribution of a light spot,
It is characterized by utilizing the fact that the optimum boost level for reproduction is uniquely determined from the recorded modulation code or the like.

Therefore, the first embodiment focuses on the fact that the comparator level to be set differs in the data slicer 40 depending on the amplitude of the input signal to the data slicer which changes according to the boost level. This makes it possible to associate the uniquely determined optimum boost level with the compare level to be set for the data slicer 40.

For example, the logic level “H” of the binarized data
And the comparison level in the first state when the first and second periods of “L” are 1: 1 and the first and second periods are 1: 2
In this case, the difference from the comparator level in the second state differs depending on the amplitude of the input signal to the data slicer. Since the amplitude of the input signal is determined by the boost level set in the previous stage, the optimum boost level can be easily set based on the difference from the comparator level.

FIGS. 3A to 3C show waveforms when different compare levels are set according to the boost level.

FIG. 3A shows a case where the reproduction signal RF boosted at the optimum boost level is inputted as the comparator input signal 80 of the data slicer, which is the period of the logic levels "H" and "L". 1, the second period is 1: 1
And the comparator level in the first state,
2 shows the comparison level in the second state.

In this case, the comparator level in the second state in which the first and second periods of the logical levels "H" and "L" are 1: 2 is the same as that in the first state in which the first and second periods are also 1: 1. It becomes lower than the compare level, and in this case, the difference between the two compare levels becomes Lva.

FIG. 3B shows a reproduced signal RF boosted at a boost level lower than the optimum boost level.
Is input as the comparator input signal 82 of the data slicer, the comparator level in the first state in which the first and second periods, which are the periods of the logical levels “H” and “L”, are 1: 1 , And the comparison level in the second state which is also 1: 2.

In this case, the comparator level in the second state in which the first and second periods of the logic levels “H” and “L” are 1: 2 is the same as that in the first state in which the first and second periods are also 1: 1. It is lower than the compare level, and in this case, the difference between the two compare levels is Lvb.

Since the boost level is lower than that at the time of the optimal boost shown in FIG. 3A, the amplitude of the comparator input signal 82 is smaller than that of the comparator input signal 80 shown in FIG. Therefore, the comparator level in the first state in which the first and second periods are 1: 1;
The difference L from the comparator level in the second state, which is 1: 2
vb has a relationship that it is smaller than Lva in FIG.

FIG. 3C shows a reproduced signal RF boosted at a boost level exceeding the optimum boost level.
Is input as the comparator input signal 84 of the data slicer, the comparator level in the first state in which the first and second periods, which are the periods of the logical levels “H” and “L”, are 1: 1. , And the comparison level in the second state which is also 1: 2.

In this case, the comparator level in the second state in which the first and second periods of the logic levels "H" and "L" are 1: 2 is the same as that in the first state in which the first and second periods are also 1: 1. It is lower than the compare level. In this case, the difference between the two compare levels is Lvc.

Since the boost level is higher than that at the time of the optimum boost shown in FIG. 3A, the amplitude of the comparator input signal 84 becomes larger than that of the comparator input signal 80 shown in FIG. Therefore, the comparator level in the first state in which the first and second periods are 1: 1;
The difference L from the comparator level in the second state, which is 1: 2
vc has a relationship of being larger than Lva in FIG.

As described above, there is a monotonically increasing relationship as shown in the following equation according to the boost level.

Lvc>Lva> Lvb (1) In the data slicer 40 according to the first embodiment, the comparator level is supplied to the DAC 50 as the count value of the counter 44.

The binary signal 2 binarized by the comparator 42
In order to change the ratio between the first and second periods, which are the periods of the logic levels “H” and “L” of the quantified data, the count units may be set in the Up count register 46 and the Down count register 48, respectively. . Therefore, counter 4
4, the count values counted in these count units can be read out as respective compare levels, whereby the difference between the compare levels can be recognized.

As a result, it is possible to associate the boost level with the difference between the compare levels.

FIG. 4 shows the relationship between the boost level and the difference between the input data to the DAC 50.

Here, the relationship between the boost level and the difference between data supplied to the DAC 50 (difference in count value) when the input signal to the comparator 42 is normalized is shown.

That is, as shown in FIGS. 3A to 3C, the difference between the boost level and the comparator level is monotonically increasing, and the boost level and the DA in FIG.
The difference between the data supplied to C50 also has a monotonically increasing relationship.

Therefore, as described above, for example, the optimum boost for reproduction determined uniquely from the pit shape of the recording medium on which the information to be reproduced is recorded, the light spot distribution of the light spot, the recorded modulation code, and the like. Since the level is determined, the difference between the input data to the DAC 50 of the data slicer 40 to be set correspondingly can be easily obtained.

As described above, in the first embodiment, in the data slicer having the configuration shown in FIG. 1, since the comparison level difference and the amplitude of the reproduction signal have a monotonically increasing relationship, the data slicer has the relationship based on the comparison level difference. Thus, a boost level that determines the amplitude of the reproduction signal can be set.

In particular, when the optimum boost level for reproduction, which is uniquely determined from the pit shape of the recording medium on which the information to be reproduced is recorded, the light quantity distribution of the light spot, and the recorded modulation code, is known. By setting the boost level as an optimum boost level and controlling the difference so as to have a corresponding comparator level difference, the optimum boost level can be adjusted as a result.

Therefore, when the position of the repetition of the densest pattern on the recording medium is unknown or when the phase error voltage or the error rate greatly fluctuating depending on the reproduction position of the recording medium is not referred to, the optimum boost adjustment can be performed. it can. This means that it is possible to adjust the boost of an information reproducing apparatus such as a CD or DVD having no close-packed pattern repetition position, such as a recording medium. It means you can do it.

3. Processing of the First Embodiment In the first embodiment, the boost adjustment as described above is performed by C
It can be executed by firmware operating on the PU 60. This firmware may be written in a ROM readable by the CPU 60, or may be stored in a given storage device and read as appropriate.

FIG. 5 shows the flow of the process of executing the boost adjustment in the first embodiment.

First, the CPU 60 has a CPU I / F 62.
Via the Up count register 46 so that the ratio of the lengths of the first and second periods of the logic levels “H” and “L” of the binary data is 1: 1. An up-count unit and a down-count unit are set in the Down count register 48 (step S10). That is, a value that sets the ratio to 1: 1 is set for the up-count unit and the down-count unit.

Subsequently, the CPU 60 controls the CPU I / F 6
Then, the count value input to the DAC 50 is read from the 16-bit Up / Down counter 54 via Step 2 (Step S12). 16-bit Up / Down counter 54
The number of bits of the count value output to DAC 50 from
Although it is variable depending on the setting band or the like, it is desirable that the 16-bit count value can be read as it is in order to perform the boost adjustment with high accuracy.

Subsequently, the read count value is stored in a variable A (step S14).

Next, the CPU 60 operates as a CPU I / F 62.
, The ratio of the lengths of the first and second periods of the logical levels “H” and “L” of the binarized data is not 1: 1 1−α:
1 + α (−1 <α <1) so that U becomes a second state.
p count register 46, Down count register 4
In step S16, an up-count unit and a down-count unit are set.

Subsequently, the CPU 60 controls the CPU I / F 6
Then, the count value input to the DAC 50 is read from the 16-bit Up / Down counter 54 via Step 2 (Step S18).

Then, the read count value is stored in the variable B (step S20).

Further, the absolute value of the difference between the variable A and the variable B is obtained, and as shown in FIG. 4, for example, the shape of the pit of the recording medium on which the information to be reproduced is recorded, the light quantity distribution of the light spot, and A comparison is made as to whether or not the value matches the target value C1 corresponding to the optimal boost level optimal for reproduction uniquely determined from the modulation code or the like (step S22).

When the absolute value of the difference between variable A and variable B does not match target value C1 (step S22: N), variable A
The absolute value of the difference between the parameter and the variable B is compared with the target value C1 (step S24).

When the absolute value of the difference between the variables A and B is smaller than the target value C1 (step S24: N), the boost level to be set in the boost level setting register 38 of the signal generator 30 is increased (step S26). ).

Thereafter, the flow returns to step S16.

On the other hand, in step S24, variable A and variable B
Is greater than or equal to the target value C1 (step S
24: Y), the boost level to be set in the boost level setting register 38 of the signal generator 30 is lowered (step S28), and the process returns to step S16.

At step S22, when the absolute value of the difference between variable A and variable B matches target value C1 (step S2
2: Y), a series of boost adjustment processing ends (END).

4. Optical Disk Device (Information Reproducing Device) in First Embodiment FIG. 6 shows a configuration example of an optical disk device (disc device, information reproducing device in a broad sense) capable of boost adjustment in the first embodiment described above.

This optical disk device is an optical disk (disc or information recording medium in a broad sense) such as a CD or DVD.
A disk motor (spindle motor) 102 for rotating a rotating shaft on which the motor 00 is mounted is provided. The information recorded on the optical disc 100 is modulated so that the DSV value of the modulation code becomes zero.

An optical pickup 104 (pickup in a broad sense) is disposed below the optical disc 100. The optical pickup 104 is mounted on a carriage 106 that moves in the radial direction of the optical disc 100.

The carriage 106 can be moved in the radial direction of the optical disk 100 by a feed mechanism (not shown), and the feed mechanism is driven by a feed motor 108.

The optical pickup 104 includes a semiconductor laser and a photodetector (not shown). Then, the laser beam from the semiconductor laser is applied to the optical disc 100 via the objective lens 110, and the reflected light is received by the light receiving portion of the photodetector divided into four or two.

The objective lens 110 of the optical pickup 104
Are held movably along the optical axis direction (vertical direction), and are also movably held in the radial direction of the optical disc 100. Then, the focus actuator 112 moves the objective lens 110 in the optical axis direction, and the tracking actuator 120 moves the objective lens 110 in the radial direction of the optical disc 100.

A detection signal from a photodetector (not shown) of the optical pickup 104 is supplied to a signal generation unit 122. The signal generation unit 122 includes the components of the signal generation unit 30 shown in FIG. The reproduction signal R based on the detection signal
F, an analog signal such as a focus error signal FE, a tracking error signal TE, a ripple signal RP indicating the amplitude of a reproduced waveform, a jitter signal JT indicating a jitter level, and a sum signal AD.

The reproduction signal RF from the signal generator 122 is
The data is supplied to the data slice unit 124. The data slice unit 124 includes the components of the data slicer 40 shown in FIG. 1, and the first and second periods of the logic levels “H” and “L” of the binarized data are set by a CPU (not shown). The binarized data is generated by binarizing the reproduction signal RF with reference to the slice level adjusted to the ratio. The binarized data is supplied to the demodulation unit 126.

The demodulation section 126 generates a synchronous clock SYCLK and a synchronous data SYDAT based on the binarized data.
Extract and output A.

The signals FE, TE,
RP, JT, AD are analog to digital (Analog to Digi
tal: hereinafter abbreviated as A / D. ) The data is converted into digital data by the conversion unit 128 and output to the focus servo control unit 130, the tracking servo control unit 132, the adjustment unit 134, and the defect detection unit 136.

The focus servo control section (focus equalizer) 130 receives digital data corresponding to the signal FE and controls the focus actuator drive section 138. Then, the focus actuator driving section 1
38 drives the focus actuator 112. This allows the objective lens 11 to always be in focus.
0 moves in the optical axis direction, and a minute spot of the laser beam is formed on the recording layer of the optical disc 100.

The tracking servo control section (tracking equalizer) 132 receives digital data corresponding to the signal TE,
Control. Then, the tracking actuator driving section 140 drives the tracking actuator 120. Accordingly, the objective lens 110 moves in the radial direction of the optical disc 100 so that the tracking state is always maintained, and the track on the recording layer of the optical disc 100 is tracked by the light beam.

The feed servo control section (feed equalizer) 142 receives the output (low-frequency component) of the tracking servo control section 132 and controls the feed motor drive section 144. Then, the feed motor driving unit 144
The feed motor 108 is driven so that the feed motor 108 rotates intermittently.

The disk servo control unit (disk equalizer) 146 receives SYDATA from the demodulation unit 126 and controls the disk motor drive unit 148. Specifically, the interval of the reference signal included in SYDATA is measured,
The CLV (Constant Lin
ear Velocity) control. Then, the disk motor drive section 148 drives the disk motor 102.

The adjusting section 134 receives the digital data corresponding to the signals RP and JT, and performs low-pass filter processing, averaging processing, and the like.

The defect detector 136 outputs the sum signal A
Receiving the digital data corresponding to D
The presence or absence of a defect is detected. That is, when no signal is returned from the optical pickup 104 due to dirt, scratches, black dots, or the like on the surface of the optical disc, the defect detection signal (skip signal) is activated.

When the defect detection signal (skip signal) becomes active, the low pass filter processing and the averaging processing of the adjusting section 134 are stopped, and the slice level of the data slice section 124 is followed at high speed, as shown in FIG. Thus, the increment of the count-up unit and the count-down unit in the counter 44 is increased, and the change of the upper bits of the 16-bit count value is accelerated.

As a result, even when the optical disc has a defect, an accurate digital average value can be obtained. Even when there is a defect, binarized data sliced at an optimum slice level can be generated.

The error detection and correction section 150 includes a demodulation section 126
An error is detected from the synchronous clock SYCLK and the synchronous data SYDATA output from the CPU and error correction is performed in accordance with a given error correction process. The error detection and correction unit 150 checks the status of the error detection and correction,
This is reflected on an error flag (not shown).

More specifically, error detection and correction section 150
Displays a flag in the error flag each time an error is detected, displays a flag in the error flag each time an error is corrected, and displays an error flag if error correction is not possible. This is indicated by a flag.

The control unit 152 controls the CPU I / O shown in FIG.
F62, and exchanges data with a CPU (not shown).
4, demodulation section 126, A / D conversion section 128, focus servo control section 130, tracking servo control section 132,
Feed servo controller 142, disk servo controller 1
Various control signals are supplied to the control unit 46, the adjustment unit 134, the defect detection unit 136, and the error detection and correction unit 150.

For example, the setting band described with reference to FIG. 2 is set by the CPU (firmware operating on the CPU) (not shown) in the data slice section 124 via the CPU I / F 152.

When a defect detection signal is used as the reference signal described with reference to FIG. 2, for example, the defect detection signal generated by the defect detection unit 136 is supplied to the data slice unit 124.

Further, the error flag updated by the error detection / correction unit 150 is, for example, the CPU I / F1
Reference is made to a CPU (firmware operating on the CPU) (not shown) via the CPU 52. Thereby, C
The PU can measure the error rate.

In the optical disk device having such a configuration, when performing the above-described boost adjustment, the CPU (firmware operating on the CPU) (not shown) transmits the data slice unit 1 via the CPU I / F 152.
For 24, an up-count unit and a down-count unit are set.

As shown in FIG. 5, the up-count unit and the down-count unit are such that the ratio between the first and second periods of the logic levels "H" and "L" of the binary data is 1: 1. The first state in the case where
Is set.

Then, the CPU is connected to the CPU I / F 152
, Read the respective count values from the data slice unit, and raise or lower the boost level so as to reach a given target value. CPU is CPU
Via the I / F 152, the boost level that has been raised or lowered is set for the signal generator 122.

By repeating the above operation, the boost level can be set to an optimum level.

<Second Embodiment> 7. Information Reproducing Apparatus According to Second Embodiment FIG. 7 shows an outline of a main configuration of the information reproducing apparatus according to the second embodiment.

However, the same portions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description will be omitted as appropriate.

In the part relating to the boost adjustment of the information reproducing apparatus in the second embodiment, the signal generator 30, the data slicer 160, the CPU 180, and the CPU I / F 18
2. Includes a duty detection unit 184.

A pickup detection signal detected by a pickup (not shown) is input to the signal generator 30. The signal generation unit 30 generates a reproduction signal obtained by equalizing the waveform of the pickup detection signal and supplies the reproduction signal to the data slicer 160.

In the following, it is assumed that the reproduced signal is modulated so that the DSV value of the modulation code becomes zero.

The data slicer 160 binarizes the reproduced signal at the adjusted and controlled comparator level to generate binarized data. A demodulation unit connected to the subsequent stage of the data slicer 160 performs a demodulation process based on the binarized data.

The data slicer 160 performs feedback control based on a count value corresponding to the length of the period of each logical bell of the binary data of the reproduced signal modulated so that the DSV value of the modulation code becomes 0, for example. Is a digital data slicer that adjusts the comparator level so that the ratio of the lengths of the periods of each logic level is 1: 1. Then, the data slicer 160 extracts the count value to be feedback-controlled, and performs a binarization process on the reproduction signal based on a comparator level obtained by adding an offset value to the count value.

The duty detecting section 184 detects the duty of the binarized data based on the comparator level obtained by adding the above-mentioned offset value. That is, the ratio between the first and second periods, which are the periods of the logical levels “H” and “L” of the second binary data, is detected.

The CPU 180 sets an offset value to the data slicer 160 and reads out the duty ratio detected by the duty detecting unit 184 via the CPU I / F 182, and based on the setting, sends the signal to the signal generating unit 30. To set the boost level.

The reproduced signal RF boosted in the vicinity of the high frequency component supplied from the signal generating section 30 is AC-coupled via a capacitor C, and has a potential level biased by a bias voltage connected via a resistor R. It is converted to a signal that changes to the reference. This signal is output to the first comparator 1
It is input to the non-inverting input terminal 62.

The negative terminal of the first comparator 162 has
A compare level voltage is provided. The first comparator 162 outputs first binary data in which the logic levels “H” and “L” (first and second levels) are switched based on the potential difference between the + terminal and the − terminal.

The reproduction signal RF is a signal generated by reading the recording information of the optical disk modulated so that the DSV value of the modulation code becomes 0. For this reason, the first binarized data obtained by binarizing the data has the logic level “H”,
The output is such that the lengths of the first and second periods, which are the periods of “L”, are approximately 1: 1 per unit time. Such first binary data is also input to the counter 164.

The counter 164 has a clock C (not shown).
In synchronization with LK, the count value is incremented by “+1” in accordance with the length of the first period in which the logic level of the first binary data is “H”. Also, the counter 164
Counts down the count value by “−1” in accordance with the length of the second period in which the logic level of the first binary data is “L” in synchronization with the clock CLK.

The counting result of the counter 164 is supplied to the first DAC 166 and the adder 168.

The first DAC 166 converts the count result of the counter 164 into an analog signal, converts it into a comparator level voltage, and supplies it to the minus terminal of the first comparator 162.

The reproduction signal RF is AC-coupled via a capacitor C, converted into a signal based on a potential level biased by a bias voltage connected via a resistor R, and then converted to a second comparator. 170 is also supplied to the + terminal.

The negative terminal of the second comparator 170 has
A compare level voltage is provided. The second comparator 170 outputs second binary data in which the logic levels “H” and “L” are alternately switched based on the potential difference between the + terminal and the − terminal.

Similarly to the first binarized data, when the DSV value of the modulation code of the reproduction signal RF is 0, the second binarized data has a logic level of “H” or “L”. A certain first
And the length of the second period is approximately 1: 1 per unit time.
Is output as

The other end of the adder 168 is supplied with the offset value stored in the offset addition register 172. The adder 168 adds the count value of the counter 164 and this offset value, and supplies the result to the second DAC 174.

The second DAC 174 converts the addition result of the adder 168 into an analog signal, converts it into a comparator level voltage, and supplies the same to the negative terminal of the second comparator 170.

The counter 164 includes a counter control logic 176 and a 16-bit Up / Down counter 178 in principle. That is, the counter control logic 176 determines the 16-bit U based on the first binarized data.
It controls the p / Down counter 178, and supplies the 16-bit count value to the first DAC 166 and the adder 168.

FIG. 8 shows a specific example of the configuration of such a counter 164.

In this case, the counter 164 includes a combinational circuit 190 and first to sixteenth FFs 72 _{1 to} 72 ₁₆ , which implement the functions of the counter control logic 176 and the 16-bit Up / Down counter 178.

The combination circuit 190 is made up of a logic element which is a component of the logic circuit, and the first comparator 16
2 and the 16-bit count value are input. In addition, the combination circuit 190 sets a set band from a control unit (not shown) and inputs a defect detection signal indicating that a defect has been detected as a reference signal.

When the output of the comparator is at the logical level (first level) “H”, the combination circuit 190 sets “+1”.
A 16-bit addition result is generated by counting up the 16-bit count value, and the respective bit values of the 16-bit addition result are respectively referred to as first to sixteenth FFs 72 _{1 to} 72
Supply ₁₆

When the comparator output is at the logical level (second level) "L", the combinational circuit 190 generates a 16-bit subtraction result obtained by counting down the 16-bit count value by "-1". The respective bit values of the subtraction result of
Supplied to the _{1-72 16.}

The first to sixteenth FFs 72 _{1 to} 72 ₁₆ are connected to the combinational circuit 1 at the rising edge of the clock CLK.
Each bit value of the 16-bit addition / subtraction result supplied from 90 is latched. The 16-bit latch data latched by the _first to sixteenth FFs 72 _{1 to} 72 ₁₆ is supplied to the DAC 50 connected to the subsequent stage and also supplied to the combination circuit 70.

The combination circuit 190 includes a CP (not shown).
The count-up unit and the count-down unit are changed based on the set band set by U or the reference signal.

For example, when the set band is set high or when the reference signal is in the active state, the combination circuit 190 sets a large value for the count-up unit and the count-down unit. The combination circuit 19
When the set bandwidth is set low and the reference signal is in an inactive state, 0 is set to a small value in units of count-up and count-down.

As described above, by changing the count-up unit and the count-down unit in the combination circuit 190, the band can be changed.

When the setting band is set high or when the reference signal is in the active state, by setting a large value for the count-up unit and the count-down unit, the counter result is easily reflected, and the slice level of the reproduction signal is reduced. In addition, it is possible to quickly follow a change due to disturbance or the like, and to perform various controls at an optimal slice level immediately after the disturbance is added.

On the other hand, when the set band is set low and the reference signal is inactive, setting a small value in the count-up unit and the count-down unit makes it difficult to reflect the counter result, and the slice level of the reproduced signal is reduced. Can be generated at a stable slice level so as not to be affected by the noise of the modulation component of the reproduction signal RF.

Data slicer 160 having such a configuration
Are the first comparator 162, the counter 164, the first
In a loop formed by the DAC 166, a disturbance level and the like are removed, and a comparator level obtained by adding only the offset value set in the offset addition register 172 is generated outside the control loop, and the second binarized based on this is generated. Can be generated. As a result,
Despite being modulated so that the value of the DSV of the modulation code becomes 0, the DSV of the modulation code for some reason
Can be sliced at an appropriate slice level even when the value of does not become 0.

As described above, the offset addition register 17
By changing the offset value set to 2,
The lengths of the first and second periods, which are the periods of the logical levels “H” and “L” of the binarized data, can be changed.

6. Features of the Second Embodiment In the second embodiment, for example, as in the first embodiment, for example, the pit shape of the recording medium on which the information to be reproduced is recorded, the light intensity distribution of the light spot, and the information are recorded. It is characterized by utilizing the fact that an optimum boost level for reproduction is uniquely determined from a modulation code or the like.

Therefore, in the second embodiment, the duty ratio of the comparator level set by adding a certain offset value in the data slicer 160 depends on the amplitude of the input signal to the data slicer which changes according to the boost level. We focus on the points that can be linked.

That is, with respect to the boost level set by adding a certain offset value, the amplitude of the comparator input signal that changes according to the boost level causes the logical levels “H” and “L” of the binarized data to be changed. 1. The ratio of the length of the second period, that is, the duty ratio is determined. Therefore, when the optimal boost level is uniquely determined, the duty ratio to be set can be known in accordance with the amplitude of the input signal of the comparator boosted at the optimal boost level. What is necessary is just to set the offset value corresponding to the offset addition register.

FIGS. 9A to 9C show a comparator input signal corresponding to a boost level and an offset value “−α”.
2 generated based on the compare level to which
4 shows a waveform of quantified data.

FIG. 9A shows a case where the reproduced signal RF boosted at the optimum boost level is input as the comparator input signal 192 of the data slicer. In this case, the difference between the Up count number and the Down count number of the binarized data generated based on the comparator level to which the offset value “−α” has been added is “+12”. .

At this time, the counter 164 counts two times per given unit time based on a clock CLK (not shown).
When the logic level of the digitized data is "H", the count value is counted up by "+1", and when the logic level of the binary data is "L", the count value is counted down by "-1".

FIG. 9B shows a reproduced signal RF boosted at a boost level lower than the optimum boost level.
Is input as the comparator input signal 194 of the data slicer. In this case, since the amplitude is smaller than that of the comparator input signal 192 at the time of the optimal boost, the period of the logic level “L” becomes shorter when the binarization is performed on the basis of the same comparator level as in FIG. As a result, the Up value of the binarized data generated based on the comparator level to which the offset value “−α” is added
The difference between the count number and the down count number is “+28”
Becomes

FIG. 9C shows a reproduction signal RF boosted at a boost level exceeding the optimum boost level.
Is input as the data slicer comparator input signal 196. In this case, the amplitude is larger than that of the comparator input signal 192 at the time of the optimal boost. Therefore, when the binarization is performed based on the same level of the comparator level as in FIG. 9A, the period of the logic level “L” becomes longer. As a result, the Up value of the binarized data generated based on the comparator level to which the offset value “−α” is added
The difference between the count number and the Down count number is “+2”.

Therefore, in the data slicer 160 according to the second embodiment, the offset addition register 172
Can be changed by changing the offset value that is set in the counter value. Thus, the count value can be arbitrarily changed by the counter 164, and the logical level “H” of the binarized data can be changed. "L"
Can be changed arbitrarily.

This means that the offset value set in the offset addition register 172 and the duty ratio detected by the duty detecting section 184 can be associated with each other.

FIG. 10 shows the relationship between the boost level and the Up / Down count difference per unit time.

Here, Up / Down per unit time
The count difference is detected by the duty detection unit 184. That is, the duty detection unit 184 can count the states of the logic levels “H” and “L” of the binarized data based on the given clock CLK, respectively, and determine the difference.

As described above, since the boost level and the Up / Down count difference per unit time are in a monotonic relationship, if the optimum boost level for reproduction that can be uniquely determined is known, it should be set correspondingly. The Up / Down count difference can be determined. Therefore, CPU1
Reference numeral 80 denotes an offset value corresponding to this,
What is necessary is just to set in the offset addition register 172 of the data slicer 160 via F182.

As described above, in the second embodiment, in the data slicer having the configuration shown in FIG. 7, since the duty ratio of the binarized data and the amplitude of the reproduced signal have a fixed relationship, the data slicer is based on the duty ratio. , A boost level for determining the amplitude of the reproduction signal can be set.

For example, when the optimum boost level for reproduction, which is uniquely determined from the pit shape of the recording medium on which the information to be reproduced is recorded, the light quantity distribution of the light spot, the recorded modulation code, and the like, is known. By setting the boost level as an optimum boost level and controlling the duty ratio to correspond to the optimum boost level, the optimum boost level can be adjusted as a result.

[0200] Therefore, when the position of the repetition of the densest pattern on the recording medium is unknown or when the phase error voltage and the error rate greatly fluctuate depending on the reproduction position of the recording medium, the optimum boost adjustment can be performed. it can. This means that it is possible to adjust the boost of an information reproducing apparatus such as a CD or DVD having no close-packed pattern repetition position, such as a recording medium. It means you can do it.

7. Processing of Second Embodiment In the second embodiment, the boost adjustment as described above is performed by C
It can be executed by firmware operating on the PU 180. This firmware may be written in a ROM readable by the CPU 180, or may be stored in a given storage device and read as appropriate.

FIG. 11 shows the flow of the process of executing the boost adjustment in the second embodiment.

First, the CPU 180 executes the CPU I / F1
A given offset value is set in the offset addition register 172 of the data slicer 160 via 82 (step S30). Since the optimal boost level that can be uniquely determined is known, the offset value is determined as shown in FIG.
Is a value obtained from the Up / Down count difference obtained in the relationship shown in FIG.

Subsequently, the CPU 180 executes the CPU I / F
The duty ratio detected by the duty detection unit 184 is read out via 182 (step S32), and is stored in a variable A (step S34).

Next, the CPU 180 compares the variable A with a target value obtained from the relationship shown in FIG. 10 (step S36).

If the value of variable A does not match the target value (step S36: N), it is determined whether variable A is greater than the target value (step S38).

When the value of the variable A is equal to or smaller than the target value (step S38: N) and when the offset value is a positive number (step S40: Y), the boost to be set in the boost level setting register 38 of the signal generator 30 is set. The level is raised (step S42).

Thereafter, the flow returns to step S32.

On the other hand, when the offset value is a negative number in step S40 (step S40: N), the signal generation unit 30
The boost level to be set in the boost level setting register 38 is lowered (step S44), and the process returns to step S32.

In step S38, when the value of the variable A is larger than the target value (step S38: Y) and when the offset value is a positive number (step S46: Y), the boost level setting register 38 of the signal generator 30 The boost level to be set is lowered (step S48).

Thereafter, the flow returns to step S32.

On the other hand, if the offset value is a negative number in step S46 (step S46: N), the signal generator 30
The boost level to be set in the boost level setting register 38 is increased (step S50), and the process returns to step S32.

Step S36 When the value of the variable A matches the target value (step S36: Y), a series of boost adjustment processing ends (END).

8. Application to Optical Disk Apparatus Such a boost adjustment in the second embodiment can be easily applied to the optical disk apparatus shown in FIG. 6 to which the components shown in FIG. 7 are applied. In this case, the duty detection unit 184 shown in FIG. 7 may be included in the data slice unit 124 or the demodulation unit 126 shown in FIG.

In this case, the data slice section outputs the first binarized data generated by the first comparator 162 to the demodulation section 126 when performing normal reproduction,
When it is determined that the phase error or the error rate is large based on the measurement result of the phase error signal or the error rate and an offset is added, the second binarized data generated by the second comparator 170 is demodulated by the demodulation unit 126. Output to This is because the first and second comparators 162,
This is because the first and second binarized data may not have the same value even if 0 is set to the offset value set in the offset addition register 172 due to the difference in the offset 170.

In such an optical disc device, when performing the above-described boost adjustment, the CP
U (firmware running on CPU) to CPU
An offset value is set for the data slice section via the I / F.

The data slice section generates binarized data based on the compare level corresponding to the offset value. This binarized data is output by the duty detection unit.
A duty ratio is detected.

Then, the CPU reads the duty ratio of the binary data output from the data slice unit via the CPU I / F, and based on the read duty ratio, increases the boost level so that the given duty ratio is obtained. Or let it go down. The CPU sets the raised or lowered boost level to the signal generation unit via the CPU I / F.

By repeating the above operation, the boost level can be set to an optimum level.

Note that the present invention is not limited to the first or second embodiment, and various modifications can be made within the scope of the present invention.

For example, in the second embodiment, the count-up and count-down are described in units of "1", but the present invention is not limited to the count-up and count-down values. In short, in the second embodiment, the value to be counted up and the value to be counted down only need to be the same value, and it is desirable that they be the same value.

Further, in the first and second embodiments, the counter is described as a 16-bit counter, but the present invention is not limited to this. The gist of the present invention is not limited by the number of higher-order bits supplied to a DAC or the like connected to the subsequent stage in the 16-bit counter value.

Although the first and second embodiments are preferably applied to an optical disk device (broadly, a disk device and an information reproducing device), they can be applied to other various electronic devices. When the first and second embodiments are applied to an information reproducing device such as an optical disk device, the information reproducing device may be provided with a function of writing recorded information.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a main configuration of an information reproducing apparatus according to a first embodiment.

FIG. 2 is a block diagram illustrating a specific example of a configuration of a counter according to the first embodiment.

FIGS. 3A to 3C are explanatory diagrams showing a comparator input signal waveform when different comparator levels are set according to a boost level. FIGS.

FIG. 4 is an explanatory diagram showing a relationship between a boost level and a difference between input data to a DAC.

FIG. 5 is a flowchart illustrating a flow of a boost adjustment execution process according to the first embodiment.

FIG. 6 is a block diagram illustrating a configuration example of an optical disc device capable of boost adjustment according to the first embodiment.

FIG. 7 is a block diagram illustrating an outline of a main configuration of an information reproducing apparatus according to a second embodiment.

FIG. 8 is a block diagram illustrating a specific example of a configuration of a counter according to the second embodiment.

FIGS. 9A to 9C are waveforms of binary data generated based on a comparator input signal corresponding to a boost level and a comparator level to which an offset value “−α” is added; FIG.

FIG. 10: Boost level and Up / D per unit time
It is explanatory drawing which shows the relationship with an own count difference.

FIG. 11 is a flowchart showing a flow of a boost adjustment execution process in the second embodiment.

FIG. 12 is a block diagram illustrating an outline of a main part of a configuration of a conventional information reproducing apparatus.

[Explanation of symbols]

Reference Signs List 10 preamplifier 12 equalizer 14 data slicer 16 binary data 20 clock signal 22 binary synchronization data 24 error correction circuit 30, 122 signal generator 32 RF signal generator 34 AGC / equalizer 36, 50 DAC 38 boost level setting register 40 , 160 Data slicer 42 Comparator 44, 164 counter 46 Up count register 48 Down count register 52, 176 Counter control logic 54, 178 16-bit Up / Down counter 60, 180 CPU 62, 182 CPU I / F 70, 190 Combination circuit 72 _{1-72 16} of the first to 16 FF 80, 82, 84 a comparator input signal 100 optical disc 102 the disc motor 104 optical pickup 106 carriage 108 Lead motor 110 Objective lens 112 Focus actuator 120 Tracking actuator 124 Data slice section 126 Demodulation section 128 A / D conversion section 130 Focus servo control section 132 Tracking servo control section 134 Adjustment section 136 Defect detection section 138 Focus actuator drive section 140 Tracking actuator drive section 142 feed servo control unit 144 feed motor drive unit 146 disk servo control unit 148 disk motor drive unit 150 error detection and correction unit 152 control unit 162 first comparator 168 adder 170 second comparator 172 offset addition register 184 duty detection unit 192 , 194, 196 Comparator input signal AD Total signal CLK Clock FE Okasuera signal JT jitter signal RF reproduced signal RP ripple signal SYCLK synchronous clock SYDATA synchronous data TE tracking error signal

Claims (10)

[Claims] 1. A binary level based on a comparator level adjusted such that a ratio of the lengths of the first and second periods of the first and second levels of the binary data is a given ratio. Level adjustment method for adjusting a boost level for boosting a reproduction signal supplied to a data slicer for performing a conversion process, wherein the first and second periods have the same length ratio. A comparison level difference between a state and a second state having a different ratio between the lengths of the first and second periods is determined, and the determined comparison level difference is determined as a target boost level of the reproduction signal. A boost adjustment method, wherein a boost level of the reproduction signal is set so as to have a corresponding target comparison level difference. 2. The data slicer according to claim 1, wherein the data slicer is configured to compare the reproduced signal with a first compare level to generate binary data, and wherein the binary data is at a first level. A comparator level generating means for counting up to a given up-count unit at the time of, and counting down to a given down-count unit when the binary data is at the second level to generate a count value; And a D / A converter that converts the analog signal into an analog signal and outputs the analog signal as the first comparator level. 3. The method according to claim 2, wherein a count value counted by the compare level generating means in a first up-count unit and a down-count unit is used as the compare level in the first state, and A boost adjustment method characterized by using a count value counted by said comparator level generating means in second up-count units and down-count units as a state compare level. 4. A boost adjusting method for adjusting a boost level for boosting a reproduction signal supplied to a data slicer for performing a binarization process on the basis of a comparator level to which an offset value is added, Detecting a duty ratio of the binarized data generated by the data slicer; and determining a duty ratio of the binarized data binarized by the data slicer with a target duty ratio corresponding to a target boost level of the reproduction signal. A boost level of the reproduction signal. 5. The duty ratio according to claim 4, wherein the duty ratio is a first and second count value corresponding to the length of the first and second periods of the first and second levels of the binary data. A boost adjustment method comprising: setting a boost level corresponding to a difference between the first and second count values as the boost level of the reproduced signal. 6. The data slicer according to claim 4, wherein the data slicer compares the reproduced signal with a first comparator level to generate first binary data; Comparator level generation for counting up when the binary data of 1 is at a first level and counting down when the first binary data is at a second level to generate a comparator level corresponding to the count value Means, a first D / A converter that converts the compare level into an analog signal and outputs the analog signal as the second compare level, an adder that adds a given offset value and the count value, and the addition. A second D / A converter that converts the addition result of the device into an analog signal and outputs the analog signal as a second comparator level; Second and a comparator, boost adjustment method duty ratio of the second binary data, characterized in that it is detected that generates a second binary data by comparing the rate levels. 7. The boost adjustment method according to claim 6, wherein the compare level generating means has a value equal to the count-up unit and the count-down unit. 8. The boost adjustment method according to claim 1, wherein the reproduction signal is a signal amplified to a certain level by an automatic gain control unit. 9. The reproduction signal according to claim 1, wherein the reproduction signal is a DSV (Digital) of a modulation code.
A boost adjustment method characterized in that modulation is performed so that the value of Sum Value is zero. 10. An information reproducing apparatus for reproducing information recorded on a recording medium, comprising: means for reading the information recorded on the recording medium to generate the reproduction signal; The automatic gain control means for amplifying; a boost means for boosting the signal amplified by the automatic gain control means in accordance with a boost level adjusted by the boost adjustment method according to any one of claims 1 to 9; An information reproducing apparatus, comprising: the data slicer that binarizes a signal boosted by boosting means.