JP2002202824A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which outputs a reference voltage free from load variation and less in temperature dependency. SOLUTION: The circuit for the band-gap reference voltage Vref is equipped with 1st and 2nd transistors QN1 and (QN2 to QN5) which are biased forward with different current density, a resistance RP2 connected to the emitters of the transistors QN1 and (QN2 to QN5), the transistor QN3 and a resistance RP1 which are connected to the emitter of the transistor QN1, resistances RP5 and RP4 which are connected to the collector of the transistor QN1 in series, a resistance RP3 which is connected to the collectors of the transistors (QN2 to QN5), a resistance RP6 and transistors QN6 and QN7 which are connected to the common point of both the resistances RP3 and RP4, an adjusting means TRIM-BGR connected to the resistance RP5 in parallel, and an amplifier circuit AMP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit using a bandgap reference voltage capable of outputting a reference voltage having a small temperature dependency.

[0002]

2. Description of the Related Art FIG. 2 shows a design example of a semiconductor integrated circuit using a band gap reference voltage according to the prior art and the present invention. In FIG. 2, a semiconductor integrated circuit using a bandgap reference voltage includes an npn-type first transistor QN1 which is short-circuited between a base and a collector and is forward-biased, and a junction current density (J1) of the first transistor QN1. ), A second transistor (QN2 to QN5) which is forward biased with a smaller junction current density (J2), and first and second transistors QN1, QN1.
A second resistor RP2 connected to the emitters of (QN2 to QN5), and a third transistor QN8 and a first resistor RP1 connected between the emitter of the first transistor QN1 and the power supply 0V and forward biased. Circuit and first and second transistors QN
1, connected to the collectors of (QN2 to QN5) and both transistors QN
1, the forward currents I1 and I2 of (QN2 to QN5) are distributed in a predetermined ratio, for example, equal values, and the first transistor QN1
RP25 connected to the collector of the second transistor, a third resistor RP3 connected to the collector of the second transistor and commonly connected to the other terminal of the resistor RP25, a common point of the resistors RP3 and RP25 and the reference voltage output Vref. Between the series circuit of the resistor RP22 connected between the first and second transistors QN6 and QN7 and the collectors of the first and second transistors QN1 and (QN2 to QN5). An operational amplifier that amplifies a voltage and outputs the amplified output as a reference voltage Vref, for example, transistors (QN9 to QN14), Pch-FETs (MP1, MP2), Nch-FETs (MN1),
And an amplifier circuit AMP including resistors R1 and RP23 and a capacitor C1.

[0003] One design example of a bandgap reference voltage circuit having such a configuration and having little temperature dependence will be described below. Here, reference output voltage Vref ≒ 5V, resistance RP2 = 7.5k
Circuit constants targeting Ω, a voltage drop across the resistor RP1 ≒ 0.3 V, and a voltage drop across the resistors RP3 and RP25250.9 V are shown in parentheses in FIG. However, here, the unit of resistance value kΩ is simply abbreviated as k.

In order to simplify the description, an amplifier circuit AM
Set the offset voltage of P to zero. In addition, RP3 = RP25 = 187.5 kΩ, RP1 = 30 kΩ, RP24 = 127.5 k
And four second transistors (QN2 to QN5) having a pair characteristic with the first transistor QN1. Under such conditions,
Assuming that the emitter currents of the first and second transistors QN1 and (QN2 to QN5) are I1 and I2 and the current densities are J1 and J2, the relations of the equations (1) and (2) are obtained.

[0005]

(Equation 1)

[0006]

[Expression 2] Vref = RP1 × 2I1 + Vbe8 + Vbe1 + RP25 × I1 + Vbe6 + Vbe7 + RP22 × 2I1 = 4Vbe + (2RP1 + RP25 + 2RP22) × (kT / q) · ln4 / RP2 = 4Vbe + (8 + 25 + 34) (kT / q) · k2 q) ・ ln4 ≒ 4.864 V (at T = 25 ° C) ・ ・ ・ ・ (2) The temperature characteristics of this bandgap reference voltage can be obtained by performing partial differentiation of equation (2) with temperature T as follows: Get.

[0007]

(Equation 3) Here, k: Boltzmann's constant (1.38 × 10 ⁻²³ ) q: charge of electrons (1.602 × 10 ⁻¹⁹ ) T: absolute temperature However, in the above equations (1) to (3), ln4 is that the characteristics of the transistor QN1 and the transistors (QN2 to QN5) are uniform (pair), that is, the current density ratio (J1 / J2) of the junction is 4. However, in an actual semiconductor integrated circuit, characteristics vary from one integrated circuit to another, and the characteristics are not uniform. Therefore, the voltage value of the reference voltage represented by the equation (3) also varies. Also, the temperature characteristics do not become zero.

In the prior art, in order to adjust the deviation of the temperature characteristic from the design value due to such variations, the resistor RP22 shown in FIG.
The deviation of the temperature characteristic from the design value is adjusted by RP24. In this circuit, the adjustment resistor RP24 is made of 7.5 kΩ × n (n> 17) and has an adjustment terminal to select which of n voltage division points is selected. This adjustment is performed by the reference voltage output Vref = 4.864. Select and adjust the partial pressure point so that it becomes V.

[0009]

In the configuration of the prior art,
An adjustment resistor is inserted between the source of the N-channel field effect transistor forming the output circuit of the operational amplifier and the reference voltage output. Therefore, when the output current is taken from the reference voltage output, the value of the reference voltage fluctuates or the output current cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-mentioned problems, and there is no change in the reference voltage even when the load current is taken from the reference voltage output.
It is another object of the present invention to provide a semiconductor integrated circuit that outputs a reference voltage with a reference voltage output within a predetermined allowable voltage range and has a small temperature dependence of the reference voltage.

[0011]

In order to achieve the above object, a bandgap reference voltage for compensating a forward voltage of a forward-biased semiconductor having a negative temperature coefficient with a voltage proportional to an absolute temperature according to the present invention. A semiconductor integrated circuit constituting a circuit includes a first transistor biased in a forward direction, a second transistor biased in a forward direction at a junction current density smaller than the junction current density of the first transistor, and a first transistor. A second resistor connected to the emitter of the second transistor;
And a series circuit of a third transistor and a first resistor, which are forward biased and connected to the collectors of the first and second transistors, and connect the forward current of both transistors to a predetermined ratio. A fifth resistor connected to the collector of the first transistor, a fourth resistor connected in series to the fifth resistor, and the other terminal of the fourth resistor connected to the collector of the second transistor. , A sixth resistor connected between the common point of the third resistor and the fourth resistor and the reference voltage output, and two forward-biased fourth transistors. A series circuit; adjusting means connected in parallel with the fifth resistor for dividing the voltage drop of the fifth resistor to selectively detect the voltage drop; and a difference between the output detected by the adjusting means and the potential of the collector of the second transistor. Amplify the voltage and output this amplification An amplifier circuit for outputting a reference voltage, shall comprise.

With such a configuration, the amplifier circuit amplifies the difference voltage between the voltage selectively detected by the adjustment means and the potential of the collector of the second transistor, and feeds back the result as a bandgap reference voltage, so that the order of the first transistor is reduced. A current proportional to the absolute temperature can be generated by the second resistor from a difference voltage between the direction voltage and the forward voltage of the second transistor smaller than the junction current density. The emitter current ratio of the first transistor and the second transistor is:
Since the series-parallel circuit composed of the fourth and fifth resistors and the plurality of series resistors of the adjusting means and the third resistor are controlled at a predetermined ratio, the first transistor and the third transistor biased in the forward direction are controlled. The base-emitter forward voltage of the fourth transistor having a negative temperature coefficient is proportional to the absolute temperature, and the emitter current of the first and second transistors is a resistor RP
A band gap reference voltage circuit having little temperature dependence of the reference voltage can be configured by compensating for the voltage generated as a voltage drop of RP5, RP5, the series resistance of RP5 and RP5.

The first transistor is an npn transistor having a base-collector short-circuited. The second transistor has a plurality of bases connected in common with the base of the first transistor, and a collector and an emitter each connected in parallel. It can be composed of npn transistor circuits. With this configuration, the second transistor junction current density can be reduced to a fraction of the first transistor junction current density.

In the amplifier circuit, an emitter circuit of two npn transistors is connected in common, the emitter circuit is connected to a power supply of 0 V by a series circuit of a transistor and a resistor which are biased in a forward direction, and a collector circuit is connected to a P-channel transistor. A high-resistance circuit is formed by driving a field-effect transistor (hereinafter abbreviated as Pch-FET) at a constant current, and the output voltage of one of the high-resistance circuits is converted to an N-channel field-effect transistor (hereinafter, Nch-FET).
The power can be amplified by a source follower circuit (hereinafter abbreviated as FET) and used as a reference output.

With this configuration, the base potential of the first-stage differential amplifier constituting the amplifier circuit can be matched with the collector potentials of the first and second transistors constituting the bandgap reference voltage. The circuit can be configured with a simple circuit, and the Pch-FET is driven at a constant current as a load resistance on the collector circuit side of the differential amplifier to form a high-resistance circuit. And amplify this amplified voltage to Nch-FE
By amplifying the power with the T source follower circuit, it is possible to output the reference voltage output without deteriorating the high gain.

The adjusting means for selectively detecting the voltage drop of the fifth resistor includes a plurality of series resistor circuits, a first field-effect transistor connected to a node of the series resistor circuit and serving as a switch, and a first electric field effect transistor. A second field-effect transistor which connects the other electrode adjacent to the effect transistor in pairs and is connected to this node to perform a switching action;
A third field-effect transistor connected to this node and connecting the other electrode adjacent to the other of the field-effect transistor in a pair and forming a switching function, and an arbitrary node of the series resistance circuit which is sequentially decoded in the same manner as described above. 4th to m-th field effect transistors to be selected, 2m NAND gates connected to each other in series by applying H and L level control signals to the first to m-th field effect transistors, and m To the top NAND gate
Means for applying H, L level control signals.

According to this configuration, the control signals of H and L levels are applied to the m leading NAND gates to adjust the reference voltage output within a predetermined reference voltage range. By fixing the state of the L-level control signal in the integrated circuit, a bandgap reference voltage circuit that falls within a predetermined reference voltage range and has little temperature dependence of the reference voltage can be configured.

[0018]

FIG. 1 is a semiconductor integrated circuit diagram of one embodiment according to the present invention, FIG. 2 is a circuit diagram illustrating a design example of a reference voltage circuit, and FIG. 3 is an internal circuit diagram of an adjusting means according to one embodiment. FIG. 4 is a schematic diagram after the selection and adjustment by the adjustment means.
The same members corresponding to are assigned the same reference numerals. (Embodiment 1) In FIG. 1, a bandgap reference voltage circuit for compensating a forward voltage of a semiconductor which is forward-biased and has a negative temperature coefficient with a voltage proportional to an absolute temperature T (° K) is constructed according to the present invention. Semiconductor integrated circuits
The first transistor QN1 whose emitter is forward biased (Vbe1) and the junction current density J2 smaller than the junction current density J1 of the first transistor QN1 are forward biased (Vbe1).
In the illustrated example of be2), a second transistor (QN2 to QN5) connecting four transistors in parallel and a second resistor connected to the emitters of the first and second transistors QN1 and (QN2 to QN5)
RP2, a series circuit of a third transistor QN8 and a first resistor RP1 connected between the emitter of the first transistor QN1 and the power supply 0V and biased in the forward direction (Vbe3), and the first and second transistors QN1, (QN2 ~ QN5)
The QN1, (QN2 to QN5) forward currents (I1, I
2) is distributed to a predetermined ratio, and the first transistor Q
A fifth resistor RP5 connected to the collector of N1;
A fourth resistor RP4 connected in series to the resistor RP5, and a fourth resistor RP4 connected to the collectors of the second transistors (QN2 to QN5).
A third resistor RP3 commonly connected to the other terminal of
A sixth resistor 22 connected between the common point of the resistor RP3 and the fourth resistor RP4 and the output of the reference voltage Vref and two forward biased transistors (Vbe6, Vbe7) QN6, QN7 And the fifth resistor connected in parallel with the fifth resistor RP5
Adjusting means TR for selectively detecting the voltage drop of RP5 by dividing the voltage drop
Output OUT detected by IM-BGR and this adjusting means TRIM-BGR
And an amplifier circuit AMP for amplifying a difference voltage between the potential of the collector of the second transistor (QN2 to QN5) and the amplified output as a reference voltage.

With this configuration, the amplifier circuit AMP amplifies the difference voltage between the voltage selectively detected by the adjusting means TRIM-BGR and the potential of the collector of the second transistor (QN2 to QN5), and amplifies the difference voltage as the bandgap reference voltage Vref. By feeding back, the second transistor (QN2 to QN5) having a smaller forward voltage Vbe1 of the first transistor QN1 and a smaller junction current density.
Absolute temperature T (° K) from the difference voltage ΔVbe from the forward voltage Vbe2 of
Can be generated by the second resistor RP2. The emitter current ratio (I1: I2) of the first transistor QN1 and the second transistor (QN2 to QN5) is the fourth / fifth.
Multiple series resistors of resistors RP4, RP5 and adjusting means TRIM-BGR
(RP6 to RP21) and the third resistor RP3 are controlled at a predetermined ratio, so that the first transistor QN1 and the third transistor QN1 which are biased in the forward direction (Vbe1).
The base-emitter forward voltage (Vbe8, Vbe6, Vbe7) having a negative temperature coefficient of the fourth transistor QN8, QN6, QN7 is increased by the emitter current I1 of the first and second transistors proportional to the absolute temperature T (° K). , I2 is compensated by the parallel resistance of the resistors RP1 and RP5 and the series resistors (RP6 to RP21) of the adjusting means, and the voltage generated as the voltage drop of the resistors RP4 and RP22, so that the bandgap with little temperature dependence of the reference voltage Vref A reference voltage circuit can be configured.

[0020]

(Embodiment 1) In FIG. 3, an adjusting means TRIM-BGR, which is connected in parallel to a fifth resistor RP5 and selectively detects a voltage drop of the fifth resistor RP5, comprises a plurality of series resistors. In the example shown, a series resistance circuit (RP6 to RP21) illustrated with 16 resistors
(Hereinafter, the description will be made with 16 series resistors), and the first field-effect transistors (M0 to M15) connected to the nodes (p1 to p16) of this series resistor circuit (RP6 to RP21) and functioning as switches, First field effect transistors (M0, M1), (M2, M3)
A second field-effect transistor (M16 to M23) which connects the other electrodes of (M12, M13) and (M14, M15) in pairs and is connected to this node to perform a switching action, similarly to the second field-effect transistor The other adjacent electrodes of the transistors (M16 to M23) are connected in pairs and connected to this node, and the third field-effect transistor (M24 to M27) which functions as a switch. Any one node px (x = 1 to 1) of the resistance circuit (RP6 to RP21)
16) Select the fourth field effect transistor (M28, M29)
And H, L to the first to fourth field effect transistors (M1 to M29)
Apply level control signals and connect them in series in pairs
The 2m (= 8) NAND gates (N0 to N7) and the four leading NAND gates (N1, N2, N5, N6) control the H and L level control signals (Z1, Z2, Z3,
Z4), for example, by providing internal terminals to connect / apply H / L level control voltage, or to connect H / L level control voltage inside / out of the integrated circuit by fusing / non-fusing of the fuse. , And means for controlling the

With this configuration, the series resistance circuits (RP6 to RP
21) is connected to the high potential side of the resistor RP5 shown in FIG. 1, the LOW side of the resistor RP6 is connected to the low potential side of the resistor RP5, and the control signals (Z1, Z2, Z3, Z4) controls the field-effect transistors (M0 to M27) to turn on and off, and inputs the voltage of any selected node (p1 to p16) to the detection output OUT to the amplifier circuit AMP, and the amplifier circuit AMP Is output as a reference voltage Vref, and this reference voltage Vref is supplied to the amplifier circuit AM via a band gap circuit.
Negative feedback control is applied to P.

The control signal (Z1, Z2, Z3, Z4) of the adjusting means TRIM-BGR shown in FIG. 3 has a central node p9 of the series resistance circuit (RP6 to RP21) when Z1 to Z4 are all at H level. Is selected.
If the reference voltage Vref at this time is lower than a predetermined target value, Z4 is set to the L level.If the reference voltage Vref is lower than the target value, Z3 is set to the L level. When the signal is higher or lower than the target value, the control signal (Z1, Z2, Z3, Z4) is set to H level from Z4 side to Z1 side, and when it is lower than the target value, it is set to L level. By doing so, the reference voltage Vref can be adjusted to be within a predetermined target value range. Next, by fixing the state of the adjusted H, L level control signals (Z1, Z2, Z3, Z4) in the integrated circuit, the control signals fall within a predetermined reference voltage range, and A bandgap reference voltage circuit capable of keeping the temperature dependency within a predetermined target value range can be configured. (Embodiment 2) Next, an amplifier circuit AMP according to an embodiment of the present invention will be described with reference to FIG. In FIG. 1, an amplifier circuit AMP
Connects the emitter circuits of two npn transistors QN10 and QN11 in common, and connects this emitter circuit with a series circuit of a transistor QN9 and a resistor RP23 which are biased in the forward direction and a power supply of 0 V
The collector circuit is connected to the gates of P-channel field-effect transistors (hereinafter abbreviated as Pch-FETs) MP1 and MP2, and the gate is connected to the drain of Pch-FET (MP2). The Pch-FETs (MP1, MP2) are driven at a constant current to form a high resistance circuit. Then, the output voltage of the high-resistance circuit of the Pch-FET (MP1) can be amplified by the source follower circuit of an N-channel field-effect transistor (hereinafter abbreviated as Nch-FET) (MN1) to obtain a reference output Vref. . Although detailed description is omitted, the resistor R1, the Pch-FET (MP3), and the transistors QN12 to QN14 act to improve the startup characteristics of the reference voltage circuit when the power is turned on.

With such a configuration, the base potentials of the first-stage differential amplifiers QN10 and QN11 forming the amplifier circuit AMP are changed to the first and second transistors QN forming the bandgap reference voltage.
Since it can be selected near the collector potential of 1, (QN2 to QN5), it can be configured with a simple circuit of the emitter circuits QN9 and RP23 of the differential amplifier. Also, the differential amplifiers QN10, QN1
Pch-FET (MP1, MP2) as load resistance on the collector circuit side of 1
Is driven by a constant current to form a high resistance circuit, so high gain is secured with few circuit elements, and this amplified voltage is
By amplifying the power by the source follower circuit of the h-FET (MN1), it is possible to configure an amplifier circuit AMP that outputs the reference voltage output Vref without loss of high gain.

FIG. 4 illustrates a state after the circuit constants and the reference voltage have been adjusted to the target values in one embodiment according to the present invention. That is, the current distribution ratio (I1 / I2 ≒ 1) is inherited from the basic design concept described earlier with reference to FIG.
7.5kΩ) instead of RP4 (142.5kΩ) and RP5
(60kΩ) and adjusting means TRIM-BGR series resistance circuit (RP6 ~ RP2
1) A parallel circuit with (120 kΩ) and a series circuit with (182.5 kΩ)
Is a difference.

With this configuration, the adjustment terminal determines which node px of the series resistance (RP6 to RP21) of the adjusting means TRIM-BGR is to be used to adjust the base voltage of the transistor QN10NO with the differential voltage of the differential amplifiers QN10 and QN11 of the amplifier circuit AMP. 4 bits of Z1 to Z4 are selected, and the transistor QN1 that composes the bandgap
(QN2 to QN5) should be the same. actually,
Adjustment is performed so that the reference voltage output Vref ≒ 4.864V. As a result, in each of the manufactured semiconductor integrated circuits, it is possible to guarantee the temperature dependence characteristic expression ln4 expressed by the expression (3), and to adjust the temperature characteristic of the reference voltage Vref to near 0, and In addition, a semiconductor integrated circuit that does not affect the reference voltage output Vref due to a load change can be configured. Also, four Nch-FETs acting as selection switches for the adjusting means TRIM-BGR in the base circuit of the transistor QN10 of the differential amplifier circuit
However, since the base current of the transistor QN10 is very small at about 40 nA, the effect can be neglected.

Further, as a feature of the present invention, the reference voltage Vref
Since the output of ≒ 5 V can be configured with a low current consumption of about 20 μA, a semiconductor integrated circuit suitable for a reference voltage circuit of a battery-operated device such as a portable device can be provided.

[0027]

As described above, according to the present invention, even if the load current is taken from the reference voltage output, it is not affected by load fluctuations, and the reference voltage output is kept within a predetermined allowable voltage range. In addition, it is possible to provide a semiconductor integrated circuit that outputs a reference voltage with little temperature dependence of the reference voltage.

[Brief description of the drawings]

FIG. 1 is a diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a design example of a reference voltage circuit.

FIG. 3 is an internal circuit diagram of an adjusting unit according to one embodiment.

FIG. 4 is a schematic diagram after selective adjustment by an adjusting unit.

FIG. 5 is a diagram of a semiconductor integrated circuit according to the related art.

[Explanation of symbols]

 QN1 to QN14 npn Transistor MP1 to MP3 Pch-FET MN1 Nch-FET R1, RP1 to RP25 Resistance C1 Capacity TRIM-BGR Adjusting means ZI to Z4 Control signal OUT detection signal Vref Reference voltage VCC Power supply voltage I1, I2 current J1, J2 current Density N0 ~ N7 NOT element MO ~ M29 Nch-FET p1 ~ p16, px Node Vbe, Vbe1, Vbe2 Forward bias voltage

Claims (4)

[Claims] 1. A semiconductor integrated circuit comprising a bandgap reference voltage circuit for compensating a forward voltage of a semiconductor having a negative temperature coefficient and being forward-biased with a voltage proportional to an absolute temperature. A first transistor and the first transistor
A second transistor biased forward at a junction current density less than the junction current density of the transistor;
A second resistor connected to the emitter of the second transistor, a third transistor connected between the emitter of the first transistor and a power supply of 0 V, and biased in the forward direction;
A fifth resistor connected to the collector of the first transistor; a fifth resistor connected to the collector of the first transistor; a fifth resistor connected to the collectors of the first and second transistors; A fourth resistor connected in series to the fifth resistor, a third resistor connected to the collector of the second transistor and commonly connected to the other terminal of the fourth resistor, and a third resistor and a fourth resistor. A series circuit of a sixth resistor connected between the common point and the reference voltage output and two forward-biased fourth transistors, and a voltage drop of the fifth resistor connected in parallel with the fifth resistor Adjusting means for selectively detecting the voltage by dividing the voltage, and the output detected by the adjusting means and the second
An amplifier circuit for amplifying a difference voltage from a potential of a collector of the transistor and outputting the amplified output as a reference voltage. 2. The semiconductor integrated circuit according to claim 1, wherein the first transistor is an npn transistor having a short-circuit between a base and a collector, and the second transistor has a first base.
A semiconductor integrated circuit comprising a plurality of npn transistor circuits connected in common with a base of a transistor and having a collector and an emitter connected in parallel, respectively. 3. The semiconductor integrated circuit according to claim 1, wherein the amplifier circuit is formed by connecting an emitter circuit of two npn transistors in common, and the emitter circuit is a series circuit of a forward-biased transistor and a resistor. Connect the power supply to 0V and drive the collector circuit with a P-channel field-effect transistor (hereinafter abbreviated as Pch-FET) at a constant current to form a high-resistance circuit. Output voltage of one high-resistance circuit is an N-channel field-effect transistor (Hereinafter abbreviated as Nch-FET)
Wherein the power is amplified by the source follower circuit and used as a reference output. 4. The semiconductor integrated circuit according to claim 1, wherein the adjusting means for selectively detecting the voltage drop of the fifth resistor is connected to a plurality of series resistor circuits and a node connected to the series resistor circuit. And a second electrode adjacent to the first field-effect transistor
A second field-effect transistor connected to this node and connected to this node to perform a switching operation, and similarly, the other adjacent electrode of the second field-effect transistor is connected to a pair and connected to this node to perform a switching operation. , A fourth to m-th field-effect transistor for sequentially decoding in the same manner and selecting an arbitrary node of the series resistance circuit, and H, L for the first to m-th field-effect transistors. Level control signal and 2m units connected in series in pairs
A semiconductor integrated circuit, comprising: a NAND gate; and means for applying H, L level control signals to the m leading NAND gates.