JP2002197897A - Semiconductor memory and its discriminating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can perform discrimination by manufacturing conditions and its discriminating method. SOLUTION: In a semiconductor memory 1206, a discriminating circuit 1208 and a test signal are provided in the part of a data output circuit 1207, the discriminating circuit outputs a result in which an internal address signal is compared with fuse information to an external terminal by turning on a test signal. Therefore, the discriminated result can be outputted to the external terminal without damaging the characteristics of a product by turning on the test signal and scanning the address. Also, as the information of the discriminating circuit is successively outputted and only an external terminal of at least one pin is additionally required, the number of terminals can be saved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of identifying the same, and more particularly, to a semiconductor memory device capable of performing identification according to manufacturing conditions and a method of identifying the same.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit is manufactured by printing a pattern on a semiconductor substrate (hereinafter, referred to as a wafer) using a mask on which a pattern of the integrated circuit is drawn. Usually, a plurality of semiconductor integrated circuit patterns are drawn on this mask. Each chip made by this mask is separated from the wafer, packaged, and commercialized.

When a defect is found in a test or evaluation after the product is commercialized, it is determined from the positional information on the wafer whether or not the defect is caused by a diffusion process in a chip manufacturing process. You can judge. In other words, if the distribution of defects has regularity, suspicions such as exposure unevenness during diffusion and scratches on the multi-faced reticle appear.

Therefore, in the past technology, the package was destroyed, the chip inside was taken out, and the judgment was made by a circuit or display for identification. As an improvement of this conventional technique, a second conventional technique for identifying a defective method without destroying a package is disclosed in, for example, Japanese Patent Application Laid-Open No. H10-209384 (Cited Document 1).

FIG. 11 shows a block diagram of the second prior art. Referring to FIG. 11, this second prior art employs a blown fuse 110 corresponding to a position on a wafer.
3 is mounted on an external terminal,
When a specific voltage is applied to the external terminal, a specific current characteristic is exhibited. As a result, a circuit configuration 1101 for identifying a position on the wafer can be determined from a combination of terminals indicating a specific current value, and it is possible to determine where the chip is located on the wafer after enclosing the package.

[0006]

However, in the configuration for connecting the identification circuits described in Patent Document 1, the identification circuits are intensively arranged near the input / output terminal PAD, and the integration of the chip is advanced. In today's product, if the number of chips on a wafer is large, the number of external terminals is small.

For example, 256 (hexadecimal = F)
If it is desired to identify all the chips in F), eight or more external terminals are required, so that this is not applicable to products with seven or less.

Furthermore, in recent years, the operating frequency of semiconductor memory devices has tended to increase, and the configuration in which an identification circuit not required for normal operation is connected to a plurality of external terminals increases the load on input / output terminals, resulting in an increase in the number of products. However, there is also a problem that the lowering of the input level sensing capability adversely affects the high frequency operation.

It is an object of the present invention to provide a semiconductor memory device and a method for identifying the semiconductor memory device, in particular, to be able to specify a position of a semiconductor memory device on a wafer in a state of being enclosed in a package.

[0010]

According to the present invention, there is provided a semiconductor memory device comprising a data input circuit, a data output circuit, a memory cell group, and a row selector / column selector. The identification circuit compares the internal address signal of the semiconductor memory device with the fuse information in the identification circuit corresponding to the position on the semiconductor substrate of the semiconductor memory device. The result is output to an external terminal by turning on the test signal.

Further, the semiconductor memory device of the present invention has a configuration in which the identification signal is output to an external terminal by turning on the test signal in a state where the semiconductor memory device is sealed in an IC package.

Further, in the semiconductor memory device according to the present invention, a position on the semiconductor substrate is identified by scanning the internal address signal, and the fuse information in the identification circuit becomes high by cutting the fuse. A level or low level may be generated, and the method of cutting the fuse may be determined by a single number that does not overlap with the position on the semiconductor substrate.

Further, in the method for identifying a semiconductor memory device according to the present invention, an identification circuit and a test signal are provided in a data output circuit, and the internal address signal of the semiconductor memory device and a semiconductor substrate of the semiconductor memory device are provided by the identification circuit. A configuration including a comparison step of comparing fuse information in the identification circuit corresponding to the upper position, a test signal on step of turning on the test signal based on the comparison result, and an output step of outputting the test signal to an external terminal It can also be.

Further, the method for identifying a semiconductor memory device according to the present invention comprises an identification step of identifying a position on the semiconductor substrate by scanning the internal address signal. And a level generating step of generating a high level or a low level by cutting the fuse, and a fuse cutting step determined by a number which does not overlap with the other from the position on the semiconductor substrate.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a semiconductor memory device capable of performing identification based on manufacturing conditions and a method for identifying the same. Be identified.

An identification circuit and a test signal are provided in the data output circuit, and the identification circuit outputs the result of comparison between the internal address signal and the fuse information to an external terminal by turning on the test signal. .

That is, for the address expression, the line =
X, column = Y, row address = internal X address (row
Address) = row selector. Also, column address = internal Y address (column address) = column selector. In other words, this circuit compares a fuse blown according to a position address (index) to which a chip on a wafer is arbitrarily allocated, and an internal address for selecting a RAM address of a device.

FIG. 12 shows a configuration diagram of a semiconductor memory device according to the present invention. The semiconductor memory device according to the present invention includes a data input circuit 1204, a data output circuit 1207, a memory cell group and 1206, a row selector / column selector 120.
5 is a configuration in which an identification circuit 1208 and a test signal TEST are added to a data output circuit 1207 in accordance with the present invention, in contrast to the configuration of a general storage device composed of five.

The identification circuit 1208 of the semiconductor memory device
Is composed of a fuse group cut in a combination that does not overlap with other chips from the position on the wafer and an internal address signal that determines the access address of the RAM. The internal address is compared with the fuse information by scanning the internal address. Then, if it matches the combination cut in advance by the position on the wafer, data different from other addresses is output.

Therefore, from the data having different execution results,
The position on the wafer can be identified. Since the discriminating circuit is not connected near the external terminal PAD, there is no increase in the load on the input / output terminals, and there is no effect on the high-speed operation due to the decrease in input level sensitivity.

The identification circuit 12 is synchronized with the internal CLK.
08 information is sequentially output. Therefore, since there is only one external terminal having at least one pin, it is possible to obtain an effect of being applicable to a product having a small number of external terminals.

Next, a semiconductor memory device according to a first embodiment of the present invention will be described.

FIG. 2, FIG. 3, and FIG. 4 show a circuit configuration in the vicinity of a single fuse of the semiconductor memory device of the present invention.
5A is a circuit example (a) in which high or low is output depending on whether a fuse is blown or not, and a truth table (b) thereof.

FIG. 2 is a circuit in which the output y1 goes low unless the fuse 222 is blown when the clock CLK is high, and FIG.
Is a high level, and when the selector signal sel is at a high level, the output y2 is at a low level unless the fuse 322 is blown.

FIG. 4 shows a circuit in which the output y3 is determined by a low-level pulse signal of the inverted set signal set_b, and the output y3 becomes low if the fuse 422 is cut.

FIG. 1 shows an identification circuit of the semiconductor memory device according to the first embodiment of the present invention.

Referring to FIG. 1, the identification circuit of the semiconductor memory device according to the first embodiment of the present invention includes a column selector signal (YP0T to YPnT) and a row selector signal (XP0T to YP0T).
XPnT), the TEST signal, and the reference clock CLK.

In these fuse circuits, those related to the row selector signals (XP0T to XPnT) include transistors (121-0, 121-1,... 121-n) and fuses (122-0, 122-1). , ... 122-n)
, EXOR (123-0, 123-1,...) Corresponding to the row selector signals (XP0T to XPnT).
123-n).

The fuse circuits related to the column selector signals (YP0T to YPnT) include transistors (125-0, 125-1,... 125-
n) and fuses (126-0, 126-1,... 12)
6-n), and the column selector signals (YP0T to YP0
nT), and EXOR (127-0, 127-
1,... 127-n).

Further, these fuse circuits are provided by EXO
R- (123-0, 123-1,..., 123-n) and the EXOR (127-n).
0, 127-1,... 127-n).
It has a NOR 130 that receives 128 outputs.

The identification circuit has a latch circuit 131 for latching the output of the NOR 130 with the reference clock CLK, and outputs the output of the latch circuit 131 to the outside of the identification circuit.

The column selector signals (YP0T to YPnT) and the row selector signals (XP0T to XPnT) are address signals for accessing the RAM. The TEST signal activates the identification circuit and switches the read bus.

As shown in the wafer map of FIG. 9C, the fuse cutting method sets a column address and a row address on a matrix which do not overlap with other chips for each chip.
From the table of FIG. 9D, it is determined that “1” is disconnected and “0” is not disconnected.

At this time, the fuse corresponds to the address of the RAM, the fuse on the MSB side corresponds to the upper address of the internal selector, and the LSB corresponds to the lower address of the internal selector. The row selector and column selector signals are shown in FIG.
Are compared with the outputs on the fuse side shown in FIG.

The resulting output can be output to the data bus by the test signal TEST. Different output data is output to an external terminal when all the bits of the fuses of the row selector signals (XP0T to XPnT) and the column selector signals (YP0T to YPnT) match.

The data output circuit and the row / column selector generating means shown in FIG. 1 are well known to those skilled in the art and are not directly related to the present invention, so that the detailed description of the structures will be omitted.

Next, the operation of the semiconductor memory device according to the first embodiment of the present invention will be described.

First, the operation of the identification circuit of FIG. 1 will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

By making the test signal TEST high, the reference clock CLK is taken into the identification circuit, so that the fuse circuit becomes operable, and the external output terminal DOUTi can output the identification circuit information from the read bus information. Become.

When the reference clock CLK is high, the column selector signal (YP0T to YPnT) and the row selector signal (X
(P0T to XPnT) and the corresponding fuse (LS)
B to MSB) and the result is output simultaneously.
Further, different data is transferred to the next-stage latch circuit 131 only when all the comparison results match. The latch circuit 131 latches through when the reference clock CLK is high and latches when the reference clock CLK is low.

As described above, the comparison results are sequentially output by scanning the internal addresses in synchronization with the reference clock CLK.

The operation of the identification circuit of FIG. 1 will be described in more detail with reference to the timing chart of FIG.

First, at time t01, the internal address (x,
y) = (0,0) is input. Then, the test signal TE
By setting ST to high, the NAND 111 is turned on, and operation by the reference clock CLK becomes possible.

That is, the NAND 134 turns off and the NA
The ND 133 turns on, and the output of the identification circuit becomes possible. At this time, the reset release of the latch circuit 131 (CLK = H
Through, and latched when CLK = L).

Since the reference clock CLK is high, X
The LSB-MSB of the side fuse is compared with the X internal address. If the comparison results match, the NAND 124 outputs a low level.

Also, the LSB-MSB of the Y-side fuse and Y
The internal address is compared. If the comparison results match, N
AND 128 outputs a low level.

The latch circuit 131 includes NANDs 124, 1
Because of the NOR of 28, H is taken in when the X, Y address comparison result is (L, L). That is, when all the comparison results of LSB to MSB of X and Y are the same.
Output to external terminal.

Even if the reference clock CLK goes low, the output of the latch circuit 131 is held until the next cycle.

In the expression in the figure, (XFuse0 A
ND YFuse0) represents an AND output of a comparison result between the X-side internal address = 0 and the fuse and a comparison result between the Y-side internal address = 0.

Next, at time t02, the same operation as at time t01 is performed, except that the internal address is different.
That is, the internal address (x, y) = (1, 0) is input.

Similarly, at time t03, the same operation as at time t01 is performed, and the internal address is the internal address (x, y) =
(2, 0) is input, and the operation at time t04 is the same as at time t01, and the internal address is the internal address (x, y) =
(1, 1) is input, and the operation at time t05 is the same as at time t01, and the internal address is the internal address (x, y) =
(1, 2) is input. In the semiconductor memory device according to the first embodiment of the present invention, the fuse is blown by making the internal address of the device correspond to the row index and the column index on the wafer. When a match occurs, a high level, which is a result different from other addresses, is output.

When used in combination with FAIL MAP, which is frequently used in a DRAM failure analysis tool, the physical position can be easily confirmed. For example, the position on the wafer (X = 6, Y =
FIG. 1 shows a case where the chip blown with the fuse set at 5) is inspected, and the FAIL MAP is viewed at the expected value row.
As shown in FIG. 3 (b), only one of the internal addresses X = 6 and Y = 5 is failed.

Next, a semiconductor memory device according to a second embodiment of the present invention will be described. FIG. 5 shows an identification circuit of the semiconductor memory device according to the second embodiment of the present invention.

Referring to FIG. 5, the identification circuit of the semiconductor memory device according to the second embodiment of the present invention includes a column selector signal (YP0T to YPnT) and a row selector signal (XP0T to XP0T).
XPnT), the TEST signal, and the reference clock CLK.

In these fuse circuits, those related to the row selector signals (XP0T to XPnT) include the fuses (522-0T, 522-0n, 522-1T, 522).
-1n,... 522-nT, 522-nn) and the row selector signals (XP0T to XPnT), the transistors (524-0T, 524-0n, 524-1T,
524-1n,... 524-nT, 524-nn).

The fuse circuits related to the column selector signals (YP0T to YPnT) include fuses (525-0T, 525-0n, 525-1T, 5).
25-1n,... 525-nT, 525-nn),
In response to the column selector signals (YP0T to YPnT), the transistors (527-0T, 527-0n, 527-1)
T, 527-1n, ... 527-nT, 527-n
n).

Then, the discrimination circuit includes the transistor 521
Circuit 5 for latching the output of the latch with reference clock CLK
31 and outputs the output of the latch circuit 531 to the outside of the identification circuit.

The column selector signals (YP0T to YPnT) and the row selector signals (XP0T to XPnT) are address signals for accessing the RAM. The TEST signal activates the identification circuit and switches the read bus.

The fuse cutting method is such that the fuse on the MSB side is associated with the upper address of the internal selector, and the LSB is associated with the lower address of the internal selector, and as shown in the wafer map of FIG. The column address and the row address are set, and “1” in the table of FIG. 9D cuts the fuse corresponding to each selector signal side (T). "0" is set so that each selector signal is disconnected on the inversion side (N).

For example, when a fuse is set at address X = 8, a fuse cut on the inversion side (N) of the address XP0T, a fuse cut on the inversion side (N) of the address XP1T, and a fuse cut on the inversion side (N) of the address XP2T. Cut, fuse cut on address XP3T side (T), fuse cut on inverted side (N) of address XP4T,.
・ A fuse is cut on the inversion side (N) of the address XPnT.

That is, in this circuit, the short-circuited output y2 cannot be set to the low level only at address 8. Therefore, when the test signal TEST is set high and the reference clock CL
When the address is scanned in synchronization with K, the output terminal
Since the data is different from the data output at other addresses, identification becomes possible.

Since the operation timing of the semiconductor memory device according to the second embodiment of the present invention is the same as that of the semiconductor memory device according to the first embodiment of the present invention, a detailed description thereof will be omitted.

Next, a semiconductor memory device according to a third embodiment of the present invention will be described.

Referring to FIG. 6, the identification circuit of the semiconductor memory device according to the third embodiment of the present invention comprises a row selector output and a column selector side of the semiconductor memory device according to the second embodiment of the present invention. Is configured as a logical OR, and an OR circuit 63
It is a circuit having 0.

The operation timing of the semiconductor memory device according to the third embodiment of the present invention is, as shown in FIG. 10B, the output data is a logical OR of the comparison result on the row selector side and the comparison result on the column selector side. Is output.

For example, if X = 6 and Y = 5, FAI
When viewed from L MAP, as shown in FIG. 13 (c), one FAIL in each of the vertical and horizontal directions, and the FAIL intersection indicates a location on the wafer.

In this circuit, the row selector signal (XP0T)
To XPnT) and the column selector signal (YP0).
Since it is the OR of the comparison result on the (T to YPnT) side, it is not necessary to scan all addresses.

If Y is fixed at 0 and X is all scanned, and X is fixed at 0 and Y is all scanned, the row position and the column position can be identified.

Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described.

Referring to FIG. 7, the semiconductor memory device according to the fourth embodiment of the present invention is a circuit configured only from the row selector side of the semiconductor memory device according to the second embodiment of the present invention. Needless to say, the configuration can be made using only the column selector of the semiconductor memory device according to the second embodiment of the present invention.

The fuse cutting method of the semiconductor memory device according to the fourth embodiment of the present invention is shown in FIG. 9 (a) in which the fuse on the MSB side corresponds to the upper address of the internal selector and the LSB corresponds to the lower address of the internal selector. As shown in FIG. 9, a serial address which does not overlap with the others is set, and "1" in the table of FIG. 9B cuts the fuse corresponding to the selector signal side (T). In the case of "0", it is set so that the inverting side (N) of the selector signal is disconnected.

For example, if address 6 is set, FAIL
When viewed from the MAP, as shown in FIG. 13A, only the address X = 6 is FAIL, and the location on the wafer can be identified from the FAIL address.

As for the operation timing, as shown in FIG. 10A, the comparison result is sequentially output by scanning the internal address in synchronization with the reference clock CLK.

Next, a semiconductor memory device according to a fifth embodiment of the present invention will be described.

Referring to FIG. 8, the semiconductor memory device according to the fifth embodiment of the present invention is a circuit configured using the fuse circuit of FIG.

The fuse cutting method is the same as that of the semiconductor memory device according to the first embodiment of the present invention.

As shown in FIG. 10D, a one-shot LOW pulse signal is generated when the power is turned on, and a low pulse of the power-on bar signal PONB used as a reset signal when the power is turned on in a DRAM or the like. Input before the identification work to determine the fuse level. The expected value of the output is the same as that of the semiconductor memory device according to the first embodiment of the present invention.

[0078]

As described above, the present invention provides a TES
By turning on the T signal and scanning the address, the data of the identification circuit is sequentially output from any terminal,
It is possible to provide a method of performing identification without impairing the characteristics of a product.

In the present invention, since the identification circuit is not connected near the external terminal PAD, the load on the input / output terminal does not increase. In addition, since the information of the identification circuit is sequentially output, it is only necessary to provide an external terminal of at least one pin, so that the present invention can be applied to a product having a small number of external terminals.

Therefore, the chip can be easily identified without opening or destroying the package, and the package can be used without concern for the number of external terminals, input / output load, and the limit of the number of identifications.
The present invention can be used for all semiconductor memory devices represented by RAM and RDRAM.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a fuse circuit used in the semiconductor memory device according to the embodiment of the present invention.

FIG. 3 is a circuit diagram of another fuse circuit used in the semiconductor memory device according to the embodiment of the present invention;

FIG. 4 is a circuit diagram of another fuse circuit used in the semiconductor memory device according to the embodiment of the present invention;

FIG. 5 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a block diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing a wafer position and a fuse circuit diagram of the semiconductor memory device of the present invention.

FIG. 10 is a time chart for explaining a normal operation of the semiconductor memory device and the identification method thereof according to the first embodiment of the present invention;

FIG. 11 is a block diagram of a conventional semiconductor memory device.

FIG. 12 is a block diagram of a semiconductor memory device of the present invention.

FIG. 13 is a wafer map diagram showing a wafer position of the semiconductor memory device.

[Explanation of symbols]

111 NAND circuit 121-j (j = 1 to n), 125-j (j = 1 to n)
Transistors 122-j (j = 1 to n), 126-j (j = 1 to n)
Fuse 123-j (j = 1 to n), 127-j (j = 1 to n)
EXOR 222, 322, 422 Fuse 131, 531 Latch circuit 1102 Identification circuit 1103 Fuse 1104, 1204 Data input circuit 1105, 1205 Column selector / row selector 1106, 1206 Memory cell group 1107, 1207 Data output circuit 1208 Identification circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 G11C 11/34 371A 5L106 21/822 H01L 27/04 T 27/10 491 (72) Inventor Tohru Arimori 1-403 53 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within the NEC Icy Microcomputer System Co., Ltd. F-term within the company (reference) 2G132 AA08 AC03 AD06 AG08 AL12 4M106 AA04 CA26 DA15 DJ21 DJ38 5B024 AA15 BA29 CA07 EA01 EA04 5F038 AV15 DT03 DT06 DT12 DT13 DT16 EZ20 5F083 AD00 GA27 LA10 ZA20 5L106A

Claims (7)

[Claims] 1. A semiconductor memory device comprising a data input circuit, a data output circuit, a memory cell group, and a row selector / column selector, wherein an identification circuit and a test signal are provided in a part of the data output circuit. The identification circuit compares the internal address signal of the semiconductor memory device with the fuse information in the identification circuit corresponding to the position of the semiconductor memory device on the semiconductor substrate, and turns on the test signal to determine the external terminal. A semiconductor memory device for outputting the data to a memory device. 2. The test signal is turned on in a state where the semiconductor memory device is sealed in an IC package.
2. The semiconductor memory device according to claim 1, wherein the identification result is output to an external terminal. 3. The semiconductor memory device according to claim 1, wherein a position on said semiconductor substrate is identified by scanning said internal address signal. 4. The fuse information in the identification circuit generates a high level or a low level by cutting the fuse, and the method of cutting the fuse is determined by a number that does not overlap with another from a position on the semiconductor substrate. The semiconductor memory device according to claim 1. 5. An identification circuit and a test signal are provided in a data output circuit, and the identification circuit fuse information corresponding to an internal address signal of the semiconductor memory device and a position of the semiconductor memory device on a semiconductor substrate in the identification circuit. A test signal on step of turning on the test signal based on the result of the comparison, and an output step of outputting the test signal to an external terminal. 6. The method according to claim 5, further comprising an identification step of identifying a position on the semiconductor substrate by scanning the internal address signal. 7. A level generating step of generating a high level or a low level by cutting off the fuse, and a fuse cutting step determined by a number that does not overlap with another from a position on the semiconductor substrate. 7. The method for identifying a semiconductor memory device according to claim 5, comprising: