JP2002197886A - Sample-and-hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit in which offset quality is restricted to a constant value. SOLUTION: Voltage B that is made to differ by a constant value from voltage A indicated by an analog input voltage signal IN is generated by a constant difference voltage generating circuit 13, offset quantity generated by influence of clock field through is restricted to a constant value by selecting and outputting the voltage B from a multiplexer 14 by a switching clock CLK and applying it to a gate of a NMOS transistor 11 and performing sample-and- hold for an analog input voltage signal IN to a capacitor 12, even when magnitude of the analog input voltage signal IN is varied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a sample and hold circuit for sampling and holding an analog voltage signal.

[0002]

2. Description of the Related Art Conventionally, a MOS switch provided on a transmission path of an analog voltage signal and a capacitor disposed at a subsequent stage of the MOS switch have been provided. There is known a sample-and-hold circuit that performs the operation. Such a sample-and-hold circuit is incorporated in an A / D converter and plays a role in converting an analog voltage signal into a digital voltage signal.

FIG. 5 is a diagram showing a configuration of a conventional sample / hold circuit incorporated in an A / D converter.

A sample and hold circuit 100 shown in FIG. 5 has an NMO provided on a transmission line for an analog voltage signal IN.
S transistor 101 and its NMOS transistor 1
01 and a capacitor 102 that holds the analog voltage signal IN. N
The switching signal SW is provided at the gate of the MOS transistor 101.
Is entered.

In the sample and hold circuit 100, when the "H" level is applied as the switching signal SW, the NMO
The S transistor 101 is turned on, whereby the capacitor 102 is charged with a charge corresponding to the magnitude of the analog voltage signal IN. Next, the switching signal SW becomes “H”.
When the level is switched to the “L” level, the NMOS
The transistor 101 changes from the on state to the off state, whereby the analog voltage signal IN is cut off. In this way, the analog voltage signal IN is held by the capacitor 102 and output to the outside as the signal OUT.

[0006]

In the sample and hold circuit 100 described above, the NMOS transistor 101
The "H" level voltage applied as a switching signal SW to the gate of is constant regardless of the magnitude of the input analog voltage signal IN (in the case of an NMOS transistor,
Usually, the power supply voltage V _DD is applied). Here, when the switching signal SW is switched from the “H” level to the “L” level, the signal is affected by the clock feedthrough caused by the floating capacitance between the gate of the NMOS transistor 101 and the capacitor 102, and An offset occurs in the voltage of OUT (referred to as a hold voltage).

FIG. 6 is a graph showing input / output characteristics of the sample and hold circuit shown in FIG.

The horizontal axis of FIG.
The voltage Vin of the analog voltage signal IN input to 0 is shown, and the vertical axis shows the voltage of the signal OUT (hold voltage Vout) output from the sample and hold circuit 100. The ideal input / output characteristic of the sample and hold circuit 100 shown in FIG.
This is a relation of the input voltage Vin. However, the input / output characteristics of the actual sample-and-hold circuit 100 show an offset in the hold voltage Vout due to the influence of the clock feedthrough described above, so that the curve B is shifted from the ideal straight line A by the offset. Become. Further, since the amount of the offset varies depending on the magnitude of the input voltage Vin, for example, in a MOS switch represented by the NMOS transistor 101 in a multi-bit A / D converter or the like, the dependency of the offset on the input voltage Vin is as follows. The linearity characteristic of the A / D converter is adversely affected, and it is difficult to perform the A / D conversion with high accuracy.

The present invention has been made in view of the above circumstances, and has as its object to provide a sample and hold circuit in which the offset amount is kept constant.

[0010]

According to the present invention, there is provided a sample-and-hold circuit comprising: a MOS switch provided on a transmission line for an analog voltage signal; and an analog switch disposed downstream of the MOS switch. And a capacitor for holding the analog voltage signal, wherein offset correction means for maintaining a constant offset amount of the analog voltage signal held by the capacitor is provided.

Here, the offset correction means is a constant difference voltage generating circuit for turning on the MOS switch by applying a gate voltage at which a difference voltage from an analog input voltage signal is constant to the gate of the MOS switch. Is preferred.

In the sample and hold circuit according to the present invention, since the offset amount of the analog voltage signal held by the capacitor is kept constant by the offset correcting means, even when the magnitude of the analog voltage signal changes, The amount of offset generated by the influence of clock feedthrough can be kept constant. Therefore, as compared with the conventional technology in which the offset amount changes depending on the magnitude of the analog voltage signal, the input / output characteristics become linear, and when the sample-and-hold circuit of the present invention is incorporated in the A / D converter, A / D conversion can be performed with high accuracy without adversely affecting the linearity characteristics of the A / D converter.

[0013]

Embodiments of the present invention will be described below.

FIG. 1 is a diagram showing one embodiment of a sample and hold circuit of the present invention.

The sample and hold circuit 10 shown in FIG. 1 has an NMO provided on a transmission line of the analog voltage signal IN.
An S-transistor 11 (an example of a MOS switch according to the present invention) and a capacitor 12 which is disposed at a subsequent stage of the NMOS transistor 11 and holds the analog voltage signal IN are provided. The sample and hold circuit 10 includes a constant difference voltage generation circuit 13 and a multiplexer 14. Constant difference voltage generation circuit 1
3 receives the voltage A represented by the analog input voltage signal IN. Although the configuration of the constant difference voltage generation circuit 13 will be described later, the constant difference voltage generation circuit 13 generates a voltage B at which the difference voltage from the input voltage A is constant. The generated voltage B is input to one terminal of the multiplexer 14. The other terminal of the multiplexer 14 is connected to the ground GND. Also, multiplexer 1
The switching clock CLK is applied to the control terminal 4.
The multiplexer 14 selectively outputs the voltage B from the constant difference voltage generation circuit 13 when the “H” level is applied as the switching clock CLK, and grounds when the “L” level is applied as the switching clock CLK. GN
The D voltage (L 'level voltage) is selectively output.

FIG. 2 is a diagram showing a configuration of the constant difference voltage generation circuit shown in FIG.

The constant difference voltage generating circuit 13 shown in FIG.
A PMOS transistor 13_2 and a PMOS transistor 13_2 connected in series are provided between the power supply voltage V _DD and the ground GND. The voltage A is input to the gate of the PMOS transistor 13_1. Further, a PMOS transistor 13_3 and a PMOS transistor 13_4 connected in series are provided between the power supply voltage V _DD and the ground GND. The gates of the PMOS transistors 13_1 and 13_3 are commonly connected, and receive a control voltage VB from a current source (not shown). Also, PM
OS transistor 13_1 and PMOS transistor 13
_2 is connected to the gate of the PMOS transistor 13_4. In the constant difference voltage generation circuit 13 configured as described above, the control voltage VB from the current source causes
MOS transistors 13_1 and 13_3 also function as constant current transistors. Here, the PMOS transistor 1
By operating 3_1 in the saturation region, the voltage difference between the gate and the source of the PMOS transistor 13_2 (the voltage difference between A and N in FIG. 2) becomes constant and acts as a source follower circuit. Similarly, when the PMOS transistor 13_4 is operated in the saturation region, the voltage difference between the gate and the source (the voltage difference between N and B in FIG. 2) becomes constant. Therefore, in the constant difference voltage generating circuit 13, the voltage difference between the input voltage A and the output voltage B is always constant. In FIG. 2, a two-stage source follower circuit is shown as an example, but this may be one stage or three or more stages according to the amplitude of the input voltage A and the power supply voltage.

Returning to FIG. 1, the operation of the sample and hold circuit 10 will be described. Sample hold circuit 1
The analog voltage signal IN is input to the constant difference voltage generation circuit 13 and the NMOS transistor 11 constituting 0.
In the constant difference voltage generation circuit 13, the analog voltage signal I
As described with reference to FIG. 2, the voltage A represented by N generates a voltage B having a constant difference voltage from the voltage A, and outputs the voltage B to the multiplexer 14. Multiplexer 14
Selectively outputs the voltage B in response to the application of the 'H' level as the switching clock CLK. The selected and output voltage B is applied to the gate of the NMOS transistor 11. Then, the NMOS transistor 11 is turned on, whereby the voltage A represented by the analog voltage signal IN is output.
Is charged in the capacitor 12. Then
The switching clock CLK is switched from the “H” level to the “L” level. Then, the multiplexer 14
'L' level voltage is selectively output. This “L” level voltage is applied to the gate of the NMOS transistor 11, thereby turning off the NMOS transistor 11. Thus, the analog voltage signal IN is held by the capacitor 12 and output to the outside as the signal OUT.

The sample and hold circuit 10 of the present embodiment
Is applied to the gate of the NMOS transistor 11 by the constant difference voltage generation circuit 13 so that the voltage B having a constant difference voltage from the voltage A is applied. In addition, the amount of offset generated due to the influence of clock feedthrough can be kept constant. Therefore, as compared with the conventional technology in which the offset amount changes depending on the magnitude of the analog input voltage signal, the input / output characteristics become linear, and when the sample and hold circuit 10 of the present embodiment is incorporated in an A / D converter, the A
A / D conversion can be performed with high accuracy without adversely affecting the linearity characteristics of the / D converter.

In the sample and hold circuit 10 of the present embodiment, an NMOS transistor has been described as an example of the MOS switch. However, this is because of the input voltage and the power supply voltage.
It goes without saying that a configuration using both OS transistors may be used. FIGS. 3 and 4 show an example in which a PMOS transistor of a MOS switch is used.

FIG. 3 is a diagram showing a sample-and-hold circuit using PMOS transistors, and FIG. 4 is a diagram showing a configuration of the constant difference voltage generating circuit shown in FIG.

The sample and hold circuit 20 shown in FIG. 3 includes a PMOS transistor 21, a capacitor 22,
A constant difference voltage generation circuit 23 and a multiplexer 24 are provided. As shown in FIG. 4, the constant difference voltage generating circuit 23 includes NMOS transistors 23_1, 23_2,
3_3 and 23_4. With the circuits shown in FIGS. 3 and 4, similar to the circuits shown in FIGS. 1 and 2,
It is clear that the amount of offset generated by the influence of clock feedthrough can be kept constant.

[0023]

As described above, according to the sample and hold circuit of the present invention, the offset amount can be kept constant.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a sample and hold circuit of the present invention.

FIG. 2 is a diagram showing a configuration of a constant difference voltage generation circuit shown in FIG.

FIG. 3 is a diagram showing a sample and hold circuit using a PMOS transistor.

FIG. 4 is a diagram showing a configuration of a constant difference voltage generation circuit shown in FIG. 3;

FIG. 5 is a diagram showing a configuration of a conventional sample and hold circuit incorporated in an A / D converter.

6 is a graph showing input / output characteristics of the sample and hold circuit shown in FIG.

[Explanation of symbols]

10,20 sample hold circuit 11,23_1,23_2,23_3,23_4 NM
OS transistor 12, 22 Capacitor 13, 23 Constant difference voltage generation circuit 13_1, 13_2, 13_3, 13_4, 21 PM
OS transistor 14, 24 Multiplexer

Claims (2)

[Claims] 1. A sample and hold circuit comprising: a MOS switch provided on a transmission path of an analog voltage signal; and a capacitor disposed after the MOS switch for holding the analog voltage signal. A sample-and-hold circuit comprising an offset correction means for keeping the offset amount of the analog voltage signal constant. 2. The method according to claim 1, wherein the offset correction unit is configured to switch the MOS
By applying to the gate of the switch a gate voltage at which the difference voltage from the analog input voltage signal is constant, the MOS
2. The sample-and-hold circuit according to claim 1, wherein the sample-and-hold circuit is a constant difference voltage generation circuit that turns on a switch.