JP2002197140A - Method of forming macro-block library for logical simulation and layout designing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming the macro-block library for logical simulation capable of setting a proper delay time not including the excess margin, to a macro-block wherein a clock control circuit is inserted between a macro-clock input terminal and a synchronizing output circuit, and to provide a layout designing method capable of easily eliminating the timing error, and remarkably shortening a time for designing. SOLUTION: The circuit connecting information from which the clock control circuit and the circuit connecting information connected to the circuit are eliminated, is formed for the macro-block wherein the clock control circuit is connected between the macro-clock input terminal and a clock input terminal of the synchronizing output circuit, the clock control circuit is formed outside of the macro-block, and the equivalent circuit connecting information equivalent to the circuit connecting information of the original macro-block is produced to verify the timing of an integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for creating a macroblock library for logic simulation and a layout design method using the macroblock library for logic simulation, and more particularly to designing a semiconductor chip by a timing-driven layout method using macroblocks. The present invention relates to a method of creating a logic simulation macro block library and a layout design method using the logic simulation macro block library.

[0002]

2. Description of the Related Art Recently, the circuit scale of an LSI has become larger and the chip area of a semiconductor chip has been rapidly increasing. For this reason, the ratio of wiring having a long wiring length exceeding several mm in the wiring on the semiconductor chip is increasing, the wiring resistance and the wiring capacitance are increasing, and the wiring delay is increasing. On the other hand, LSI
Has been increasing, and the influence of wiring delay on the operating speed of LSI has become more serious.

In addition, reflecting the increase in circuit scale and the complexity of the circuit, the difference between the wiring delay calculated from the virtual layout performed after the circuit design is completed and the wiring delay calculated from the final layout increases. The accuracy of the timing verification performed using the wiring delay calculated from the virtual layout after the circuit design has been remarkably deteriorated. For this reason, it is becoming difficult to satisfy the timing of the LSI in the conventional layout design method.

Therefore, in recent LSI layout design, it is extremely important to proceed with the layout design while compensating timing. TDL is a design method that performs layout while compensating for timing.
(Timing DrivenLayout) design method is known. This TDL design method restricts a delay time between an output terminal of a circuit block and an input terminal of another circuit block and a path connecting input / output terminals of a plurality of circuit blocks. This is a layout design method in which a delay time is restricted and placement and routing is performed within the given delay time restriction.

[0005] A first conventional example of a TDL design method will be described with reference to FIG. 8. FIG. 8 is a flowchart showing a first conventional TDL design method. In step S 801, circuit connection information 81 of an integrated circuit is stored. Input and step S80
In step 2, circuit block layout information 82 for automatic layout used in automatic layout is input. Here automatic layout circuit block layout information 82, the outer shape of the circuit blocks, terminal information such as the terminal position and attribute, an information such as routing prohibited area.

In step S803, a circuit block delay library 83 defining the delay of the circuit block is input. In step S804, the circuit connection information 81 of the integrated circuit, the circuit block layout information for automatic layout 82, and the target chip area are obtained. With reference to the layout of the circuit blocks, a schematic wiring between the circuit blocks is generated in step S805. If the result of the general wiring satisfies the evaluation criterion, detailed wiring is performed to generate a semiconductor chip.

Next, in step S806, the wiring delay between the circuit blocks is calculated with reference to the wiring information between the circuit blocks generated in step S805.
At 07, timing analysis between flip-flops is performed using the wiring delay generated at step S806.

In step S808, it is determined with reference to the timing analysis result in step S807 whether or not a timing error such as a setup time error or a hold time error exists in the analysis result. If determined, in step S809, in order to correct the timing and eliminate the timing error, a buffer for driving a wiring having a large wiring delay is additionally inserted, or the wiring having a large wiring delay is connected to the output terminal. For example, processing such as replacing the existing circuit block with a circuit block having the same function as this circuit block and a large driving capability is performed.

Next, in step S810, a change in the wiring required by the timing correction is performed, and then, in step S811, the wiring delay of the changed wiring portion is calculated. Then, returning to step S807, the timing analysis is performed again using the wiring delay calculated in step S811, and step S807 is performed until all timing errors are resolved.
To Step S811 are repeated.

If it is determined in step S808 that all timing errors have been resolved, the process proceeds to step S808.
At 812, an integrated circuit layout pattern 84 for producing a mask is output.

Next, a first conventional example of the TDL design method will be specifically described with reference to FIGS. FIG. 9 shows flip-flops 92 and 95 and combinational circuits 93 and 94.
A macro clock input terminal 91 represents a clock signal input terminal of the macro block 90, and an output terminal 96 outputs an output signal from the flip-flop 95 to an output signal of the macro block 90. Represents a terminal to be taken out.

Now consider the conflict between the data input to the data input terminal 99 of the flip-flop 95 and the clock signal input to the clock input terminal 910. The delay of the path from the starting point A to the data input terminal 99 is as follows:
It consists of delays τ1 to τ3 corresponding to each path of (3). That is, τ1 is from the start point A to the flip-flop 92
Represents a wiring delay to the clock input terminal 97, τ2 represents a delay time from the change of the clock signal applied to the clock input terminal 97 to the output of data to the output terminal 98, and τ3 represents the output terminal 98. To data input terminal 9
9 represents the delay time of the path to 9.

Further, the delay time τ3 is a wiring delay τ31 from the output terminal 98 to the input terminal of the combinational circuit 93.
The delay time τ32 of the combination circuit 93, the wiring delay τ33 between the output terminal of the combination circuit 93 and the input terminal of the combination circuit 94, the delay time τ34 of the combination circuit 94, the output terminal of the combination circuit 94 and the flip-flop 95. Delay τ35 to the data input terminal 99 of
Consists of

The wiring delay corresponding to the path (4) from the starting point A to the clock input terminal 910 is defined as τ4.

When the timing of the circuit of FIG. 9 is analyzed in step S807 of FIG. 8, τ1, τ2, τ31 to τ35,
τ4 is τ1 = 50 psec, τ2 = 200 psec, τ
31 to τ33 = 100 psec, τ34 = 200 psec
c, τ35 = 450 psec, τ4 = 200 psec.

Here, the delay times .tau.2, .tau.32, .tau.34 are stored in the circuit block delay library 8 in step S803 in FIG.
A value read from the 3, τ1, τ31, τ33,
τ35 and τ4 are wiring delays calculated in step S806 or step S811 in FIG.

Using the above values, step S807 in FIG.
At the starting point A → (1) path → (2) path →
The delay time T1 from the path (3) to the data input terminal 99 is T1 = 50 + 200 + 100 × 3 + 20
It is calculated as 0 + 450 = 1200 psec = 1.2 nsec.

The period of the paths to the data input terminal 99 from the start point A as described above, the clock signal delay time T1 in determining the setup time to be applied to the 1.2nsec next, whereas macro clock input terminal 91 Is 1 nsec, the delay time τ4 for determining the setup time for the path from the starting point A to the clock input terminal 910 is 1.0 + 0.2 = 1.2 nsec
c, and the delay time T1 and the delay time τ4 have the same value.

If the setup time of the flip-flop 95 is read as 10 psec in step S803 in FIG. 8, data input to the data input terminal 99 and a clock signal input to the clock input terminal 910 are input simultaneously. , A setup error occurs in the flip-flop 95.

For this reason, it is determined that there is a timing error in step S808 of FIG. 8, and in order to correct the timing in step S809, as shown in FIG.
Buffer 101 is additionally inserted into the circuit of FIG.

Generally, as the wiring length increases and the wiring capacitance increases, it takes time to drive the wiring capacitance and the wiring delay increases.
In the example of (1), the signal is additionally inserted into the output of the combinational circuit 94 having the largest wiring delay.

Then, in step S811, the buffer 101
, The wiring delay connected to the data input terminal 99 is calculated. This value is 400 psec, and the buffer 101 read out from the circuit block delay library 83 is calculated.
If the delay time is 10 psec, step S8
At 07, the delay time T1 ′ from the start point A to the data input terminal 99 via the buffer 101 is T1 ′ = 50 + 200
+ 100 × 3 + 200 + 400 + 10 = 1160 pse
It is calculated as c = 1.16 nsec.

Therefore, the data input to the data input terminal 99 is input 40 psec earlier than the clock signal input to the clock input terminal 910, thereby satisfying the setup time of the flip-flop 95 of 10 psec.

As described above, the first of the TDL design methods
In the conventional example, although it is possible to correct a timing error such as a setup error or a hold time error in an LSI internal circuit, a delay difference between a clock signal wiring route and a data signal wiring route is detected. Since the delay correction and the timing correction are performed as described above, there are the following restrictions.

1) The delay difference between the clock signal wiring path and the data signal wiring path can be corrected only by the clock input terminal of a specific flip-flop and the clock of the next flip-flop of the flip-flop. This is limited to the case where a single-phase clock signal is supplied to the input terminal from the same node.

2) In the first conventional example of the TDL design method, the delay definition file stored in the delay library needs to define the delay time from each input terminal to each output terminal. However, CPU
Since the function such as to be a complex macro-blocks, the state of the output terminals is not determined uniquely by the state of the input terminals,
The delay time between each input terminal and each output terminal cannot be uniquely defined. For this reason, SOC (System
In the development of a large-scale LSI represented by On Chip), there is a problem that the first conventional example of the TDL design method cannot be used for the design.

In order to solve the above-described constraint of the first conventional example of the TDL design method, a synchronization output flip-flop in which a single-phase clock is applied to an output terminal of a macro block is added as necessary. Accordingly, the second part of the TDL design method using a macroblock of a type in which a part of the output of the macroblock is output in synchronization with a clock signal.
Has been proposed.

In the TDL design method according to the second conventional example, a delay library in which a delay time from each input terminal to each output terminal is defined without using a complicated logic operation inherent in a macroblock is used.

Next, a method of creating a macro block delay library used in the second conventional example of the TDL design method will be described with reference to FIG.
12 and the circuit diagram of the macro block shown in FIG.

[0030] In step S111 of FIG. 11 enter the circuit connection information inside macroblocks, macroblock wiring delay information (macroblock wiring delay information) 112 of the wiring constituting the macroblock in step S112, input at step S111 In addition to the internal circuit connection information,
Circuit connection information of a macro block having wiring delay information is generated.

An example of the macroblock wiring delay information 112 will now be described with reference to FIG. FIG.
(A) shows circuit blocks A, B,
Shows a circuit diagram of a macro block having a C, and the terminal P1 of the terminal P0 and the circuit block A is connected, connected to the terminal P4 of the terminal P3 and the circuit block C terminal P2 and the circuit block B of the circuit blocks A are doing.

FIG. 15B shows macro block wiring delay information 112 corresponding to the macro block shown in FIG. 15A. In the first row, the wiring delay between the terminal P0 and the terminal P1 is three.
psec, and the second row shows the terminal P2 and the terminal P
3 indicates that the wiring delay between the terminal P2 and the terminal P4 is 1 psec.
0 psec. As described above, the macro block wiring delay information 112 is basically represented by the information of the terminal pair and the wiring delay corresponding to this terminal pair.

Next, in step S113, the internal circuit constituting the circuit connection information of the macro block is replaced with the delay library of the corresponding internal circuit. Subsequently, step S11
In step 4, all the delay processing flags included in the output terminal information of the synchronization output flip-flop are set to 0 indicating that no processing is performed as an initial setting. Here, the synchronization output flip-flop is provided to output the output of the macro block in synchronization with the macro clock signal. The synchronization output flip-flop is generally provided with an input terminal of the macro block by a synchronization output circuit. The delay between the delay processing flag and the output terminal can be uniquely defined based on the macro clock signal. Next, it is determined in step S115 whether or not all the delay processing flags are 1, and in step S114, the delay processing flags are all set to 0. Since it has been set, step S116
Is performed. In step S116, an output terminal on which a delay processing flag of 0 is set is searched.

Next, in step S117, as shown in an example of the path (1) in FIG. 12, the wiring delay from the macro clock input terminal which is the clock input terminal of the macro block to the clock input terminal of the synchronization output flip-flop is reduced. calculate.

Next, in step S118, as shown by the path (3) in FIG. 12, a wiring delay from the output terminal of the synchronization output flip-flop to the output terminal of the macro block is calculated.

[0036] Then in step S119, step S117 and a wiring delay calculated respectively step S118, the output data from the clock input is changed from the flip-flop 125 is the output flip as shown in path (2) in FIG. 12 The delay time until the signal propagates to the output terminal Q of the loop is added, and the sum is calculated as a clock delay value. That is, the value obtained by adding the delays shown in the paths (1) to (3) in FIG. 12 is the clock delay value.

[0037] Next, at step S120, and stores the clock delay values calculated in step S119 to the clock delay value file 114, followed by delay processing included in the output terminal information of the output flip-flop of calculating the clock delay value in Step S121 The flag is set to 1 indicating that the delay processing has been completed.

Steps S115 to S1 until the delay processing flag included in the output terminal of the output flip-flop becomes 1 indicating that the processing is completed.
Step 21 is repeated.

If it is determined in step S115 that the delay processing flags included in the output terminal information of the synchronization output flip-flop are all "1", all clock delay values are stored in the clock delay file 114 in step S122.
Read from. In step S123, the clock delay value read in step S122 is converted into data in a table format representing the delay time between the input terminal and the output terminal of the macroblock, and is generated as a macroblock delay library 115.

[0040]

However, the above-mentioned TD
In the method of creating a macroblock delay library used in the second conventional example of the L design method, the macroblock delay library 115 is focused on a change in a rising edge or a falling edge of a clock signal applied to a macroclock input terminal. When a logic circuit is inserted in the clock signal propagation path inside the macro block for generation, there is a problem that an accurate delay library cannot be generated.

Next, with respect to the above-mentioned problem when a logic circuit is inserted in the clock signal propagation path inside the macro block, the circuit diagram of the macro block shown in FIG. 13 and the timing of this macro block shown in FIG. This will be specifically described with reference to a chart.

The macro block shown in FIG. 13 has a macro clock input terminal 132 and a synchronization output flip-flop 13.
An exclusive OR 133 is inserted between the common node of each of the clock input terminals 4 and 135, and the other input of the exclusive OR 133 is the clock selection terminal 1
31.

By setting the control signal CSEL applied to the clock selection terminal 131 to a low level (“0”), the clock signal applied to each clock input terminal of the synchronization output flip-flops 134 and 135 is changed to the macro clock signal MCLK. And the control signal CS
By setting EL to high level (“1”), the clock signal applied to each clock input terminal of the synchronization output flip-flops 134 and 135 is changed to the macro clock signal M.
Controlling the phase opposite to CLK.

As can be seen from FIG. 14, the control signal CSE
At time t1 when L is “0”, data is output from output terminal OUT1 with a delay of delay time τ (0) from the rise of macro clock signal MCLK.
At time t2 when SEL is “1”, the output terminal OUT1 is delayed from the rise of the macro clock signal MCLK by a delay time τ (1) obtained by adding the delay time τ (0) by a half clock cycle of the macro clock signal MCLK. The macro clock input terminal 132 and the output terminal OU
The delay time between T1 is not uniquely determined, and the control signal CSE
The problem that it differs depending on L occurs.

The technique of inserting a control gate for controlling a clock signal into a clock signal propagation path is a kind of gated clock technique for reducing power consumption. This is an extremely effective method for suppressing an increase in power.

Therefore, it is considered that a large number of macroblocks having control gates inserted in the clock signal propagation path will be designed in the future. However, when a delay library is created in a macroblock having such a synchronized output flip-flop. This causes an excessive timing margin.

In other words, the delay time τ (0) at time t1 in FIG. 14 and the delay time τ (1) at time t2 must be considered. time, it is necessary to ensure generically circuit operation even at any operating conditions, the delay time larger tau (1) the selection inevitably.

However, in actual circuit operation, the control signal C
When SEL is 0, the delay time is essentially τ
(0) should be sufficient, resulting in an excess margin for a half clock cycle. Therefore, there is a problem that the delay library created by the processing flow shown in FIG. 11 cannot be applied to the design of an integrated circuit that requires high-speed operation.

Therefore, an object of the present invention is to provide a macro block in which a logic circuit is inserted between a macro clock input terminal for inputting a clock signal from the outside and a synchronization output circuit such as a synchronization output flip-flop. It is another object of the present invention to provide a method of creating a macroblock library for logic simulation that can set an appropriate delay time without including an excessive margin.

Another object of the present invention is to provide a method for creating a macroblock library for logic simulation which can set a highly accurate delay time and can be applied to an integrated circuit which operates at high speed.

A further object of the present invention is to provide a timing driven layout design method using a macro block library for logic simulation according to the present invention, whereby a timing error can be easily eliminated and a design period can be greatly reduced. Is to provide.

[0052]

Therefore, a method of creating a macroblock library for logic simulation according to the present invention comprises: a clock control circuit for performing a logical operation on a macroclock signal input from a macroclock terminal to generate an internal clock signal; A synchronous output circuit that outputs data to a macro output terminal in synchronization with the internal clock signal. The macro circuit of the macro block including the macro clock terminal is used when performing a logic simulation of an integrated circuit including the macro block. In the method for creating a logic simulation macro block library in which a delay between an input terminal and the macro output terminal is defined, a circuit connection to be connected to the clock control circuit and an input terminal of the clock control circuit from circuit connection information inside the macro block. Delete the information and said A virtual terminal is provided at an output terminal of the lock control circuit, a wiring delay between the virtual terminal and an input clock terminal of the synchronization output circuit to which the internal clock signal is input, and the synchronization output circuit responds to the internal clock signal. The delay time until data is output to the output terminal of the synchronization output circuit, and the wiring delay time between the output terminal of the synchronization output circuit and the macro output terminal are added, It is characterized in that it is used as delay information constituting a delay library of a macro block.

Further, the layout design method according to the present invention
A macro block including a clock control circuit that performs a logical operation on a macro clock signal input from a macro clock terminal to generate an internal clock signal, and a synchronization output circuit that outputs data to a macro output terminal in synchronization with the internal clock signal Wherein the clock control circuit and the circuit connection information connected to the input terminal of the clock control circuit are deleted from the circuit connection information inside the macro block, and a virtual connection is made to the output terminal of the clock control circuit. A wiring delay between the virtual terminal and the input clock terminal of the synchronization output circuit to which the internal clock signal is input, and the synchronization output circuit responds to the internal clock signal, The delay time until data is output to the output terminal, the output terminal of the synchronization output circuit and the (B) a first step of adding an interconnect delay time between output terminals to generate an edited macroblock having the added value as delay information; and a circuit connection information of the integrated circuit and a circuit connection information of the clock control circuit. And replacing the macro block with the edit macro block, providing the clock control circuit outside the edit macro block, between a virtual terminal of the edit macro block and an output terminal of the clock control circuit, and A terminal of the integrated circuit connected to an input terminal of the clock control circuit in a macro block is connected to an input terminal of the clock control circuit, and equivalent circuit connection information equivalent to circuit connection information of the integrated circuit is connected. A second step of connecting, and referring to the equivalent circuit connection information, refer to a circuit block constituting the equivalent circuit connection information. A third step of placing and wiring between circuit blocks, a fourth step of calculating a wiring delay of the wiring generated in the second step, and a step of calculating the delay of the clock control circuit disposed in the macro block. A fifth step of calculating a wiring delay of the input wiring, and the wiring delay generated in the fourth step and the fifth step.
A sixth step of calculating a delay difference from the wiring delay generated in the step, and a timing analysis of the integrated circuit with reference to the equivalent circuit connection information and the wiring delay generated in the fourth step. A seventh step;
An eighth step of deleting the clock control circuit and the circuit connection information connected thereto from the equivalent circuit connection information when the timing analysis result in the step satisfies a predetermined judgment criterion; and Connect the open circuit connection information with the obtained circuit connection information,
Generating circuit connection information equivalent to the circuit connection information of the integrated circuit; and referring to the circuit connection information and the delay difference, the inter-circuit blocks are connected so that a newly generated wiring delay cancels the delay difference. A ninth step of performing the above wiring.

[0054]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for creating a macroblock library for logic simulation according to the present invention will be described with reference to FIGS.

FIGS. 1 and 2 are flow charts showing a method of creating a macro block library for logic simulation according to the present invention. The macro block library for logic simulation includes synchronized output flip-flops 39 and 310 as shown in FIG. It is generated for a macro block having a synchronization output circuit 313.

That is, the synchronization output circuit built in the macro block synchronizes the data input from inside the macro block to the synchronization output circuit to the outside of the macro block in synchronization with the macro clock signal input from outside the macro block. Output. This synchronization output circuit does not need to be provided for all output terminals of the macroblock, but is provided only for output terminals that need to satisfy timing constraint conditions.

First, referring to FIG. 3, the macro blocks used in the method for creating a macro block library for logic simulation according to the present invention will be specifically described. The macro block shown in FIG. 3 includes data input terminals 31 and 32, a clock selection terminal 33, a macro clock input terminal 34,
Output terminals OUT1 and OUT2 for extracting an output signal from the macro block, combination circuits 35 to 38,
A synchronization output circuit 313 including synchronization output flip-flops 39 and 310, a clock control circuit 311A including an exclusive OR 311 and a virtual terminal 312 are provided.

The input signal IN1 applied to the data input terminal 31 is logically processed by the combination circuits 35 and 36, and is input to the data input terminal D of the synchronization output flip-flop 39. Similarly, the input signal IN2 applied to the data input terminal 32 is logically processed by the combination circuits 37 and 38, and is input to the data input terminal D of the synchronization output flip-flop 310.

The macro clock signal MCLK applied to the macro clock input terminal 34 is phase-controlled to the positive or negative phase by the control signal CSEL input to the clock selection terminal 33, so that the synchronization output flip-flop 39,
310 is applied to the clock input terminal.

Therefore, output signals synchronized with the macro clock signal MCLK are output to the output terminals Q of the synchronization output flip-flops 39 and 310 constituting the synchronization output circuit 313, respectively.

Next, with reference to FIGS. 1 and 2, an embodiment of a method for creating a macroblock library for logic simulation according to the present invention will be described.
The circuit connection information 1 inside the macro block including the clock control circuit for controlling the phase and the like of the macro clock signal
And the wiring delay information 2 of the wiring forming the macro block, and adding the wiring delay information 2 of the wiring forming the macro block to the circuit connection information 1 inside the macro block to obtain a macro having the wiring delay information. Generate circuit connection information for the block.

Next, in step S12, a clock control circuit for controlling the macro clock signal existing on the path between the macro clock input terminal and the clock input terminal of the synchronization output circuit is searched. This clock control circuit performs an operation such as arbitrarily controlling the phase of the macro clock signal from 0 to 180 degrees as in the exclusive OR 311 shown in FIG.

In step S13, it is determined whether or not a clock control circuit exists in the macro block. If it is determined that the clock control circuit exists, the process in step S14 is performed, and the clock control circuit does not exist. If it is determined that the process ends.

Next, in step S14, the wiring delay of the wiring connected to the input terminal of the clock control circuit is calculated. For macro-block shown in FIG. 3, with reference to the wiring capacitance and wiring resistance between the input terminals of the clock selection terminals 33 and exclusive OR311, calculates the wiring delay of the wiring path, similarly, the macro clock terminal 34 With reference to the wiring capacitance and the wiring resistance between the input terminals of the exclusive OR 311, the wiring delay of this wiring path is calculated,
It is output as input wiring delay information 3 of the clock control circuit. The input wiring delay information 3 of this clock control circuit
Is used in the timing driven layout design method using the macro block library for logic simulation according to the present invention shown in FIG. 4 when laying out a semiconductor chip.

Next, in step S15, the clock control circuit and the wiring delay information added to the input terminal of the clock control circuit are deleted from the circuit connection information with wiring delay information generated in step S11, and the clock control circuit is deleted. Is output as wiring delay information 4 excluding wiring delay information related to.

Next, in step S16, the clock control circuit and the circuit connection information connected to the input terminal of the clock control circuit are deleted from the circuit connection information 1 inside the macro block, and the clock control circuit is connected to the clock control circuit as shown in FIG. Generate a virtual terminal at the output.

That is, a new virtual terminal 312 is generated,
Circuit connection information for connecting the exclusive OR 311 shown on the left side (input side) of the virtual terminal 312 to the clock selection terminal 33 and the input terminal of the exclusive OR 311, and connection between the macro clock input terminal 34 and the input terminal of the exclusive OR 311 And deleting the circuit connection information to be connected to the clock input terminals of the synchronization output flip-flops 39 and 310 shown on the right side (output side) of the virtual terminal 312 without deleting the circuit connection information. do.

The clock control circuit and the connection information connected to the input terminal of the clock control circuit are deleted from the circuit connection information inside the macro block, and the clock control circuit and the circuit connected to each input terminal of the clock control circuit are deleted. The circuit connection information 5 of the macro block excluding the connection information and the circuit connection information 6 of the clock control circuit are generated.

Next, in step S17 of FIG. 2, the macro block layout information 7 and the macro block circuit connection information 5 excluding the clock control circuit and the circuit connection information connected to this input terminal are referred to, and the macro block A virtual terminal is generated for the layout information of

Subsequently, in step S18, referring to the layout information of the macro block generated in step S17, an automatic layout composed of information on the outer shape of the macro block, terminal information such as terminal positions and attributes, and information such as a wiring prohibited area is provided. And output the macro block layout information 8. At this time, in the macro block layout information 8 for automatic layout, each terminal on the layout corresponding to the clock selection terminal 33 and the macro clock input terminal 34 in FIG. 3 remains as it is.

Next, in step S19, the wiring delay information 4 excluding the wiring delay information related to the clock control circuit
With reference to the clock control circuit and the circuit connection information 5 of the macro block excluding the circuit connection information connected to each input terminal of the clock control circuit, the synchronization output circuit and the input connection information of this output circuit are deleted. Instead, it generates circuit connection information within a macro block with wiring delay information having virtual terminals.

Next, at step S20, step S
Referring to the circuit connection information in the macro block generated in step 19 and the delay library 9 in the macro block in which the delay between the input terminal and the output terminal is defined for the internal circuit constituting the macro block, Replace circuit blocks with corresponding delay libraries.

Subsequently, in step S21, the delay processing flags included in the output terminal information of the synchronization output circuit are all set to 0 indicating that no processing is performed as an initial setting.

Next, at step S22, it is determined whether or not the delay processing flags included in the output terminal information of the synchronization output circuit are all "1". Since the delay processing flags are all set to "0" at step S21, Step S23 is performed. In step S23, an output terminal on which a delay processing flag of 0 is set is searched.

Next, in step S24, step S
The synchronization flip-flops 39 constituting the synchronization output circuit 313 from the virtual terminal 312 shown in FIG.
Path (4) to each clock input terminal 310;
(4) Calculate virtual clock wiring delays which are wiring delays respectively corresponding to '.

Next, in step S25, the synchronization output flip-flop 3 shown as an example in FIG.
The wiring delays respectively corresponding to the paths (6) and (6) ′ from the output terminals Q of Nos. 9 and 310 to the output terminals OUT1 and OUT2 of the macroblock are calculated.

Subsequently, in step S26, the virtual clock wiring delay calculated in step S24 and the
The wiring delay from the output terminal of the synchronization output circuit to the output terminal of the macro block calculated in step 25 and the data input to the output flip-flops 39 and 310 shown in FIG. , And a delay time until the signal propagates to the output terminal Q is added, and the added value is calculated as a clock delay value. That is, in the example shown in FIG. 3, a value obtained by adding delays corresponding to paths (4), (5), and (6), and a path (4) ′,
The value obtained by adding the delays corresponding to (5) and (6) ′ is the clock delay value.

Next, in step S27, step S
The clock delay value calculated in step 26 is stored in the clock delay value file 10, and the delay processing flag included in the output terminal information of the synchronization output circuit whose clock delay value has been calculated in step S28 indicates that the delay processing has been completed. Is set to 1.

[0079] Thus delay processing flag contained in the output terminal of the synchronization output circuit, until 1 indicating that all processing is complete, the process is repeated step S22~ step S28.

If it is determined in step S22 that all the delay processing flags included in the output terminal information of the synchronization output circuit are 1, all clock delay values are read from the clock delay value file 10 in step S29. Then, in step S30, the clock delay value read in step S29 is converted into table format data representing the delay time between the input terminal and the output terminal of the macro block,
Generated as the macro block delay library 11.

Next, a first embodiment of a timing-driven layout design method using a macroblock library for logic simulation according to the present invention will be described with reference to FIG.
5 and a circuit diagram which is a part of the integrated circuit shown in FIGS.

Referring first to FIG. 5, FIG. 5 shows a circuit diagram of a part of an integrated circuit, and data input terminals 51 and 5 are shown.
2, an external clock input terminal 53, an output terminal 54,
It has a macro block 55 having a built-in synchronization output circuit, combination circuits 56 and 58, and a flip-flop 57.

That is, the macro block 55 receives the external clock signal ECL applied to the external clock input terminal 53.
The data calculated inside the macro block 55 is output to the output terminals OUT1 and OUT2 in synchronization with K.

The following description will be given of the macro block 55 as a circuit shown in FIG. That is, the control signal generated by the combination circuit 58 is input to the clock selection terminal 33 in FIG.
Is input to the exclusive OR 311 constituting.

External clock signal ECLK is applied to node 5
9 and input to the macro clock input terminal 34, and further to the exclusive OR 311. The output of the exclusive OR311 is inputted to the clock input terminal of the synchronization control circuit 313 via the virtual terminal 312.

[0086] The external clock signal ECLK is node 5
9 is also applied to the clock input terminal of flip-flop 57. Thus, the data synchronized with the external clock signal ECLK is output to the output terminal OUT of the macro block 55.
1 and further subjected to logical operation by the combinational circuit 56 and input to the data input terminal of the flip-flop 57. This data is output to output terminal 54 in synchronization with external clock signal ECLK.

Next, the processing flow of FIG. 4 will be described. In step S401 of FIG. 4, the circuit connection information 41 of the integrated circuit and the circuit connection information 6 of the clock control circuit generated in step S16 of FIG. 1 are referred to. FIG. 6 shows an example in which a macro block having a built-in synchronization output circuit is replaced with a macro block in which a clock control circuit and connection information existing between a virtual terminal and a macro clock input terminal and a clock selection terminal are deleted. The equivalent circuit connection information logically equivalent to the circuit connection information 41 of the integrated circuit is generated.

That is, in FIG. 6, the macro block 55 in FIG. 5 is replaced by a macro block 55 'in which the clock control circuit and the connection information existing between the virtual terminal and the macro clock input terminal and the clock selection terminal are deleted from the virtual terminal. As shown in FIG. 6, the exclusive OR 311 of FIG. 3 constituting the macro block 55 is changed to the node 59 and the macro block 5 as the exclusive OR 510.
5 'is connected between the virtual terminals. Here, the layout information for the automatic layout of the macro block 55 'is basically the same as the layout information for the automatic layout of the macro block 55, such as the outer shape and the terminal position.

Therefore, the logical operation from the output of the node 59 and the combination circuit 58 to the virtual terminal through the exclusive OR 510 in FIG. 6 is performed by changing the macro clock input terminal and the clock selection terminal from the output of the node 59 and the combination circuit 58 in FIG. This is the same as the logic operation reaching the virtual terminal of FIG.

Next, in step S402, referring to the equivalent circuit connection information generated in step S401, the circuit block layout information for automatic layout 42, and the circuit block delay library 43, the macro block and the like constituting the integrated circuit are referred to. Automatically place circuit blocks.

Here, the automatic layout circuit block layout information 42 is an automatic layout composed of the macro block outer shape, terminal information such as terminal positions and attributes, and information such as a wiring prohibited area generated in step S18 in FIG. It includes both the macro block layout information 8 for the basic logic circuit such as an AND gate and a flip-flop, terminal information such as terminal positions and attributes, and information such as a wiring prohibited area.

Further, the circuit block delay library 43 includes:
It includes both the macroblock delay library 11 generated in step S30 of FIG. 2 and a basic logic circuit delay library that defines the delay between the input terminal and the output terminal of the basic logic circuit.

Next, in step S403 in FIG. 4, with reference to the arrangement information of the circuit blocks generated in step S402, general wiring between circuit blocks such as macro blocks and basic logic circuits is performed. If it is appropriate, detailed wiring between circuit blocks is performed, and step S
In 404, a wiring delay between circuit blocks is calculated with reference to the wiring information of the detailed wiring generated in step S403.

Next, in step S405, the following two editing processes are performed with reference to the wiring delay generated in step S404.

1) The wiring delay from the output of the clock control circuit to the virtual terminal of the macro block is set to 0. In the example of FIG. 6, the wiring delay of a path indicated by a dotted line from the output of the exclusive OR 510 to the virtual terminal of the macro block 55 'is set to 0. This is the exclusive OR5 in FIG.
The wiring delay between the output of the terminal 10 and the virtual terminal corresponds to the wiring delay between the output of the exclusive OR 311 and the virtual terminal 312 in FIG. 3, and since the wiring delay is substantially 0, such processing is performed.

2) The clock control circuit which is the difference between the input wiring delay information 3 of the clock control circuit generated in step S14 of FIG. 1 and the input wiring delay information of the clock control circuit generated in step S404 of FIG. Calculate the wiring delay difference value.

By performing wiring processing of the wiring input to the clock control circuit so that the clock control circuit wiring delay difference value finally becomes 0, an equivalent circuit diagram corresponding to the equivalent circuit connection information shown in FIG. And a layout of an integrated circuit chip which is logically and timing equivalently laid out using a circuit diagram corresponding to the circuit connection information shown in FIG. it is possible to generate.

Next, in step S406, timing analysis between flip-flops is performed using the wiring delay edited in step S405. And step S40
In step 7, with reference to the timing analysis result in step S406, it is determined whether a timing error such as a setup time error or a hold time error exists in the analysis result. If it is determined that a timing error exists, In order to correct the timing in step S408 and eliminate the timing error, a buffer for driving a wiring with a large wiring delay is additionally inserted, or a circuit block in which the wiring with a large wiring delay is connected to the output terminal is Processing such as replacing the circuit block with a circuit block having the same function as the circuit block and having a large driving capability is performed.

Next, in step S409, the wiring required by the timing correction is changed, and then, in step S410, the wiring delay of the changed wiring part is calculated. Then, returning to step S406, the timing analysis is performed again using the wiring delay calculated in step S410, and step S406 is performed until all timing errors are eliminated.
Step S410 is repeated.

If it is determined in step S407 that all timing errors have been resolved, step S407 is executed.
In step 411, the clock control circuit and the circuit connection information connected thereto are deleted from the equivalent circuit connection information generated in step S401.

In the example shown in FIG. 6, the exclusive OR
The circuit connection information for connecting the input of the exclusive OR 510 and the output of the node 59 and the combinational circuit 58, and the circuit connection information for connecting the output of the exclusive OR 510 and the virtual terminal are deleted.

Next, in step S412, circuit connection information is generated between the terminals that have become open as the processing in step S411. In the example of FIG. 6, circuit connection information between the node 59 and the macro clock input terminal, and circuit connection information between the output of the combinational circuit 58 and the clock selection terminal are generated. Then, based on this circuit connection information, a rewiring process of the wiring connected to the clock control circuit is performed so as to compensate for the clock control circuit wiring delay difference value calculated in step S405.

For example, the clock control circuit wiring delay difference value (defined as “input wiring delay of clock control circuit of macroblock in FIG. 1—input wiring delay of clock control circuit generated in step S404”) is +1 ns.
If it is c, rewiring is performed such that the wiring delay due to the rewiring generated in step S412 is 1 nsec greater than the input wiring delay of the clock control circuit generated in step S404.

As a result, the layout using the equivalent circuit diagram corresponding to the equivalent circuit connection information shown in FIG. 6 is the layout of the integrated circuit chip when the layout is laid out using the circuit diagram corresponding to the circuit connection information shown in FIG. Is logically and timingly equivalent.

Finally, in step S413, the layout pattern 44 of the integrated circuit for producing a mask is output.

In step S13 of FIG. 1, the processing is completed when there is no clock control circuit inside the macro block. However, the processing is not stopped, and a method similar to the macro block delay library creating method shown in FIG. 11 is used. it is also possible to continue the process. The delay library obtained in this way and the delay library obtained by the present invention shown in FIGS. 1 and 2 can be mixed on an integrated circuit and designed according to the design flow shown in FIG.

Next, a second embodiment of the timing driven layout design method using the macro block library for logic simulation according to the present invention will be described with reference to the flowchart shown in FIG.

The processing flow of the present invention corresponds to step S4 in FIG.
In step 12 ′, circuit connection information is generated between the terminals that have been opened as the processing in step S411, and based on this circuit connection information, the clock control circuit wiring delay difference value calculated in step S405 is not considered, and the clock connection information is generated. A rewiring process of the wiring connected to the control circuit is performed.

In order to compensate for the timing, steps S412 and S4 of the processing flow shown in FIG.
13, the processing of step S414 for calculating the wiring delay of the rewiring unit shown in FIG. 7, and the processing of step S406 in FIG.
Step S415 for performing timing analysis and timing correction similarly to the processing of Step S410.

In the timing driven layout design method using the logic simulation macro block library according to the present embodiment, the wiring connected to the clock control circuit is re-wired without considering the clock control circuit wiring delay difference value in step S412 '. Processing,
The feature is that the design process is fast.

Although the synchronizing output circuit has been described as being composed of a flip-flop, it may be composed of a latch or a register. Further, the present invention can be similarly applied even when the exclusive OR is an exclusive NOR.

A clock control circuit which does not operate as a circuit is arranged near a macro block on an integrated circuit chip designed by the method of preparing a macro block library for logic simulation and the layout design method of the present invention. Since the area of the clock control circuit is small, the area of the integrated circuit chip hardly increases due to the clock control circuit. In addition, when a small gate is required near a macro block due to a circuit modification or the like, there is an advantage that the clock control circuit can be used to change from a wiring process to cope with the problem.

[0113]

As described above, the method of creating a macro block library for logic simulation and the method of layout design according to the present invention provide a macro clock input terminal for inputting a clock signal from the outside and a synchronization output such as a synchronization output flip-flop. It is possible to set an appropriate delay time for a macro block in which a logic circuit is inserted between the circuit and the macro block without including an excessive margin.

Further, the method for creating a macroblock library for logic simulation according to the present invention can set a highly accurate delay time. Therefore, an integrated circuit that performs high-speed operation using the macroblock library for logic simulation according to the present invention can be provided. Can be realized.

Further, it is possible to easily eliminate the timing error and greatly reduce the design period. Actually, in the design of an integrated circuit in which the timing error did not disappear even if it took more than two weeks in the conventional design method, the design was performed in accordance with the method of creating the macro block library for logic simulation and the layout design method of the present invention. The timing condition was satisfied.

[Brief description of the drawings]

1 is a flowchart illustrating a method of creating a macro block library for the logic simulation according to the present invention in conjunction with FIG.

FIG. 2 is a flowchart showing a method of creating a macroblock library for logic simulation according to the present invention, together with FIG.

FIG. 3 is an example of a circuit diagram of a macro block having a synchronization output circuit for explaining a method of creating a macro block library for logic simulation according to the present invention.

FIG. 4 is a flowchart showing a first embodiment of a layout design method using a logic simulation macro block library according to the present invention.

FIG. 5 is a partial circuit diagram of an integrated circuit for explaining a layout design method of the present invention.

6 is an equivalent circuit diagram corresponding to the equivalent circuit connection information generated in step S401 in FIG. 4, that is, an equivalent circuit diagram that is logically equivalent to the circuit in FIG.

FIG. 7 is a flowchart illustrating a layout design method using a logic simulation macro block library according to a second embodiment of the present invention;

FIG. 8 is a flowchart illustrating a first conventional example of a TDL design method.

FIG. 9 is a circuit diagram of a macro block for explaining a first conventional example of a TDL design method.

FIG. 10 is a circuit diagram of the macro block generated in step S810 of FIG.

11 is a flowchart showing a delay library creation method of macroblocks used in the second conventional example of TDL design method.

FIG. 12 is a circuit diagram of a macro block for explaining a method of creating a macro block delay library used in a second conventional example of a TDL design method.

FIG. 13 is a circuit diagram of a macro block for explaining a method of creating a delay library of the macro block used in the second conventional example of the TDL design method, wherein a clock control circuit is connected to a clock input terminal of a synchronization output circuit; FIG. 3 is a circuit diagram of a macro block in operation.

[14] The second conventional example for explaining a problem regarding the timing margin in view of the TDL design method 13
6 is a timing chart of the macroblock shown in FIG.

FIG. 15 is an example of macroblock wiring delay information.

[Explanation of symbols]

1,111 Macroblock circuit connection information 2,112 Macroblock wiring delay information 3 Clock control circuit input wiring delay information 4 Clock control circuit related information edited wiring information 5 Clock control circuit related information edited macroblock circuit Connection information 6 Circuit connection information of clock control circuit 7 Macro block layout information 8 Macro block layout information for automatic layout 9, 113 Delay library inside macro block 10, 114 Clock delay value file 11, 115 Macro block delay library 31, 32, 51, 52 Data input terminal 33, 131 Clock selection terminal 34, 91, 120, 132 Macro clock input terminal 35-38, 56, 58, 93, 94, 121-124
Combination circuits 39, 310, 92, 95, 125, 126, 134,
135 Flip-flop 133, 311, 510 Exclusive OR 312 Virtual terminal 313 Synchronization output circuit 41, 81 Circuit connection information of integrated circuit 42, 82 Circuit block layout information for automatic layout 43, 83 Circuit block delay library 44, 45, 84 Integrated Circuit layout pattern 53 External clock input terminal 54, OUT1, OUT2, 96, 98 Output terminal 55, 55 'Macroblock with built-in synchronization output circuit 59 Node 90 Macroblock 97, 910 Clock input terminal 99 Data input terminal 101 Buffer A, B, C circuit blocks P1 to P4 terminals

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA06 JA05 KA06 5F064 BB03 BB04 BB06 BB19 BB28 DD02 DD10 DD25 EE02 EE42 EE43 EE47 EE54 EE57 HH06 HH09 HH12

Claims (7)

[Claims] 1. A clock control circuit for performing a logical operation on a macro clock signal input from a macro clock terminal to generate an internal clock signal, and a synchronization output circuit for outputting data to a macro output terminal in synchronization with the internal clock signal A logic simulation macro block library which is used when performing a logic simulation of an integrated circuit having a macro block including a macro block and defines a delay between a macro input terminal and a macro output terminal of the macro block including the macro clock terminal. In the creation method, the clock control circuit and circuit connection information connected to an input terminal of the clock control circuit are deleted from circuit connection information inside the macro block, and a virtual terminal is provided at an output terminal of the clock control circuit. A virtual terminal and the same input to which the internal clock signal is input; A wiring delay between input clock terminals of the synchronized output circuit, a delay time until the synchronized output circuit outputs data to an output terminal of the synchronized output circuit in response to the internal clock signal, and Generating a macro block library for logic simulation, wherein an output terminal of a circuit and a wiring delay time between the macro output terminals are added, and the added value is used as delay information constituting a delay library of the macro block. Method. 2. A clock control circuit for performing a logical operation on a macro clock signal input from a macro clock terminal to generate an internal clock signal, and a synchronization output circuit for outputting data to a macro output terminal in synchronization with the internal clock signal A logic simulation macro block library which is used when performing a logic simulation of an integrated circuit having a macro block including a macro block and defines a delay between a macro input terminal and a macro output terminal of the macro block including the macro clock terminal. In the creation method, a first step of inputting circuit connection information inside the macro block and wiring delay information inside the macro block, and calculating circuit connection information with wiring delay information including these information, Calculate the wiring delay of the wiring connected to the input terminal of the circuit Step 2 and a wiring delay to be connected to the clock control circuit with reference to the circuit connection information with wiring delay information calculated in the first step and the wiring delay calculated in the second step. A third step of calculating no wiring delay information; and removing the clock control circuit and circuit connection information connected to an input terminal of the clock control circuit from the circuit connection information inside the macro block, A fourth step of generating circuit connection information in which virtual terminals are provided at the output of the second step, and a wiring delay including both the wiring delay information generated in the third step and the circuit connection information generated in the fourth step. A fifth step of generating circuit connection information with information; and between the virtual terminal and the input clock terminal of the synchronization output circuit to which the internal clock signal is input. A wiring delay and a wiring delay between the output terminal of the synchronization output circuit and the macro output terminal are calculated, and these wiring delays and the synchronization output circuit of the synchronization output circuit respond to the internal clock signal. A sixth step of calculating an added value by adding a delay time until data is output to an output terminal, wherein the added value is used as delay information constituting a delay library of the macro block. How to create a macro block library for logic simulation. 3. Referring to layout information of the macro block, arranging the virtual terminal in the layout information,
3. The method for creating a macroblock library for logic simulation according to claim 1, wherein macroblock layout information for automatic layout is generated. 4. The method according to claim 1, wherein the synchronization output circuit is a flip-flop, a latch, or a register. 5. The method according to claim 1, wherein the clock control circuit shifts the phase of the macro clock signal by a control signal to generate the internal clock signal. 6. The clock control circuit is an exclusive OR or an exclusive NOR.
Or the method of creating the logic simulation macroblock library description. 7. A clock control circuit for performing a logical operation on a macro clock signal input from a macro clock terminal to generate an internal clock signal, and a synchronization output circuit for outputting data to a macro output terminal in synchronization with the internal clock signal DOO in the layout method of producing an integrated circuit comprising a macroblock comprising, remove the circuit connection information which connects the circuit connection information inside the macro block to an input terminal of the clock control circuit and the clock control circuit and the clock control circuit A virtual terminal is provided at an output terminal of the synchronization terminal, and a wiring delay between an input clock terminal of the synchronization output circuit to which the virtual terminal and the internal clock signal are inputted, and the synchronization output circuit responds to the internal clock signal, The delay time until data is output to the output terminal of the synchronization output circuit and the output time of the synchronization output circuit A first step of adding a wiring delay time between a terminal and the macro output terminal to generate an edited macro block having the added value as delay information; and a circuit connection information of the integrated circuit and a clock control circuit. Inputting circuit connection information, replacing the macro block with the edit macro block, providing the clock control circuit outside the edit macro block, between the virtual terminal of the edit macro block and the output terminal of the clock control circuit. And an equivalent circuit equivalent to the circuit connection information of the integrated circuit by connecting a terminal of the integrated circuit to which an input terminal of the clock control circuit in the macro block is connected and an input terminal of the clock control circuit. A second step of connecting the connection information; and referring to the equivalent circuit connection information, forming the equivalent circuit connection information. A third step of arranging road blocks and wiring between circuit blocks; a fourth step of calculating a wiring delay of the wiring generated in the second step; and the clock arranged in the macro block. A fifth step of calculating a wiring delay of the input wiring of the control circuit; and a sixth step of calculating a delay difference between the wiring delay generated in the fourth step and the wiring delay generated in the fifth step. A seventh step of performing timing analysis of the integrated circuit by referring to the equivalent circuit connection information and the wiring delay generated in the fourth step; and determining whether a result of the timing analysis in the seventh step is predetermined. If it satisfied the criteria, and an eighth step of deleting the circuit connection information for connecting to said clock control circuit from the equivalent circuit connection information, the eighth Connect the open circuit connection information with the circuit connection information obtained in the step, generate circuit connection information equivalent to the circuit connection information of the integrated circuit, and refer to this circuit connection information and the delay difference. A ninth step of performing wiring between the circuit blocks so that a newly generated wiring delay cancels the delay difference.