JP2002190594A - Insulated gate power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated gate power semiconductor device, wherein short defects between a gate electrode and an emitter electrode can be reduced, and at the same time, the number of processes can be reduced. SOLUTION: The insulated gate type power semiconductor device comprises a first conductivity-type collector region 2 disposed in a lower part of a semiconductor substrate, a second conductivity-type base region 3 disposed in an upper part of the semiconductor substrate, a plurality of the first conductivity type base regions 4 disposed at specified intervals in an upper part of the second conductivity type base region, the second conductivity type emitter region 5 disposed in an upper part of the first conductivity type base region, and gate electrodes 6 disposed on the surface of the semiconductor substrate through a gate insulation film. On the surface of the semiconductor substrate, the gate electrodes 6 are disposed, substantially only on the first conductivity type base region 4 between the base region 3 and the emitter region 5, both of which are of the second conductivity-type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate power semiconductor device, and more particularly to a high withstand voltage insulated gate bipolar transistor having excellent low on-resistance and high-speed operation.

[0002]

2. Description of the Related Art In recent years, power MOSFETs (power MOSFETs) have been developed.
Insulated gate (MOS) type power semiconductor devices using microfabrication technology comparable to LSI, such as S-type field effect transistors and IGBTs (insulated gate bipolar transistors), have low on-resistance, low power loss, and high-speed operation. Due to the development of technologies for high performance and multi-functionality such as performance, it has spread rapidly, and has become the mainstream of power devices, mainly for low breakdown voltage systems. At present, IGBTs show superiority in high breakdown voltage, low on-resistance, etc., compared to power MOSFETs in high breakdown voltage systems due to the mechanism of conductivity modulation based on the bipolar drive system, and are used in low breakdown voltage systems of about several hundred volts. Not limited, several k
Applications to power devices of high withstand voltage of V or more are actively performed.

FIG. 3 is a sectional view showing the structure of a conventional IGBT. A p-type collector region 52 is arranged below the semiconductor substrate 51, and an n-type base region 53 is arranged above the semiconductor substrate 51. A plurality of p-type base regions 54 are arranged at a predetermined interval 66 above the n-type base region 53, and an n-type emitter region 55 is arranged above the p-type base region 54. A collector electrode 60 is connected to the collector region 52, and an emitter electrode 59 is connected to the emitter region 55 and the p-type base region 54. The gate electrode (on the n-type base region 53 disposed between the adjacent p-type base regions 54 and the p-type base region 54 between the emitter region 55 and the n-type base region 53 via the gate oxide film 57. A polysilicon film) 56 is provided.
A terrace oxide film is arranged between n-type base region 53 and gate oxide film 57. An interlayer insulating film 58 is arranged on the gate electrode 56, and the emitter electrode 59 is
And are connected to each other. By applying a positive voltage to the gate electrode to p-type base region 54, an n-type channel is formed on the surface of p-type base region 54 sandwiched between emitter region 55 and n-type base region 53. Is done.

[0004]

When the IGBT is on, the emitter region 55 and the collector region 52 are turned off.
The on-resistance between (E-C) is the on-resistance when carriers (electrons) pass through the channel (channel resistance: Rch) and the on-resistance when carriers (electrons / holes) drift in the n-type base region 53. It is composed of a resistor (drift resistance: Rd) and the like.
The withstand voltage between E and C is determined by the width of the n-type base region 53, the specific resistance, and the like. When the IGBT is designed to have a relatively low withstand voltage of about several hundred volts, the drift resistance can be suppressed low because the width of the n-type base region 53 is small and the specific resistance is low.
The channel resistance is dominant in the ON resistance between E and C. On the other hand, in the case of a specification design with a relatively high withstand voltage, the n-type base region 5
Since the width of 3 is large and the specific resistance is high, the drift resistance becomes dominant.

In order to suppress the drift resistance of the IGBT having a high withstand voltage, it is desirable to increase the predetermined interval 66 between the plurality of p-type base regions 54. By doing this,
Holes injected from the collector region 52 into the n-type base region 53 are less likely to be discharged to the p-type base region 54 (hole discharge resistance is increased), and the hole density in the n-type base region 53 can be increased. . When the hole density in the n-type base region 53 increases, the amount of electrons injected from the source region 55 increases, so that the carrier density of the n-type base region 53 can be increased, and carriers (electrons / holes) can be increased. Can substantially reduce the on-resistance when drifting the n-type base region 53.

However, as the interval between the p-type base regions 54 is increased, the width (area) of the gate electrode 56 is also increased. Normally, when the gate electrode 56 is formed, polysilicon dust is randomly deposited on the surface thereof, and this dust causes a hole in the interlayer insulating film 58, causing the gate electrode 56 and the emitter electrode 59 to form a hole. There is a risk of short-circuit failure. By increasing the area of the gate electrode,
The probability of occurrence of short-circuit failure due to the dust increases.

In addition, as the width (area) of the gate electrode is increased, the gate capacitance between the semiconductor substrate 51 and the gate electrode 56 is increased, so that high-speed operation performance is reduced and switching noise is increased. Although a terrace oxide film 65 is arranged between the n-type base region 53 and the gate electrode 56 which do not directly contribute to channel formation to reduce the gate capacitance, this is not sufficient. Further, the terrace oxide film increases the unevenness of the gate electrode and the emitter electrode disposed thereon, and there is a possibility that an open defect may occur at the stepped portions such as the gate electrode 56 and the emitter electrode 59.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and an object thereof is to reduce short-circuit defects between a gate electrode and an emitter electrode, and at the same time, to shorten the process. An object of the present invention is to provide an insulated gate power semiconductor device.

Another object of the present invention is to provide an insulated gate type power semiconductor device having high speed operation performance and low on-resistance.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is characterized in that a semiconductor substrate having a front surface and a rear surface facing each other and a collector of a first conductivity type disposed below the semiconductor substrate including the rear surface. A region, a second conductivity type base region disposed above the surface including the surface of the semiconductor substrate, and a plurality of first conductivity type base regions disposed at predetermined intervals above the second conductivity type base region; An emitter region of a second conductivity type selectively disposed above the base region of the first conductivity type;
A gate electrode disposed on the surface of the semiconductor substrate via the gate insulating film, an interlayer insulating film disposed on the gate electrode, a first conductive type base region and an emitter region, An insulated gate power semiconductor device having an emitter electrode disposed therein, wherein the gate electrode is a first conductive type substantially disposed between the second conductive type base region and the emitter region on the surface of the semiconductor substrate. That is, it is arranged only on the mold base region.

According to the feature of the present invention, since the gate electrode is not arranged on the second conductivity type base region between the adjacent first conductivity type base regions as in the prior art, the width (area) of the gate electrode is reduced. ) Does not spread. Therefore, the probability of occurrence of short-circuit failure between the gate electrode and the emitter electrode due to dust made of the gate electrode material randomly deposited on the surface of the gate electrode can be suppressed.

Further, since the width (area) of the gate electrode does not increase, an increase in gate capacitance can be suppressed. Further, since the necessity of the terrace oxide film for reducing the gate capacitance is eliminated, the manufacturing process of the terrace oxide film can be reduced. Further, by removing the terrace oxide film, the flatness of the interlayer insulating film and the emitter electrode disposed on the gate electrode is improved, and it is possible to prevent an open failure of the emitter electrode at a step portion.

In the embodiment, when the predetermined interval between the adjacent first conductivity type base regions is widened to reduce the on-resistance of the transistor described later, the operation and effect of the first feature of the present invention described above. Increases significantly.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, parts similar to those of the related art are denoted by similar reference numerals.

(First Embodiment) FIG. 1 shows an IGBT (Insulated Gate Bipolar Transistor) according to a first embodiment of the present invention.
It is sectional drawing which shows the structure of r). As shown in FIG. 1, the IGBT according to the first embodiment is formed on a semiconductor substrate 1 such as a silicon substrate having a front surface 11 and a back surface 12 facing each other. A collector region 2 to which a p-type impurity such as boron (B) is added is disposed below the semiconductor substrate 1, and the collector region 2 is exposed on the back surface 12 of the semiconductor substrate 1. An n-type base region 3 to which an n-type impurity such as phosphorus (P) or arsenic (As) is added is disposed above the semiconductor substrate 1, and the n-type base region 3 is exposed on a surface 11 of the semiconductor substrate 1. I have. Collector region 2 and n-type base region 3 form a pn junction.

Above n-type base region 3, a plurality of p-type base regions 4 to which p-type impurities are added are arranged at predetermined intervals 16, and each p-type base region 4 is formed on surface 11 of semiconductor substrate 1. It is expressed in. Above each p-type base region 4, an emitter region 5 doped with an n-type impurity is selectively disposed, and the emitter region 5 is exposed on the surface 11 of the semiconductor substrate 1. In each p-type base region 4, the central portion 13 and the outer peripheral portion 14 are exposed on the surface 11 of the semiconductor substrate 1, and the emitter region 5 is exposed on portions other than the central portion 13 and the outer peripheral portion 14.

An emitter electrode 9 is connected to a central portion of each p-type base region 4 and a part of the emitter region 5. The gate oxide film 7 is disposed on the surface 11 of the semiconductor substrate 1 except for the emitter electrode 9. A gate electrode 6 made of a polysilicon film is selectively disposed on the outer peripheral portion 14 of the p-type base region 4 and the gate oxide film around the peripheral portion 14. On the gate oxide film 7 and the gate electrode 6, an interlayer insulating film 8 is arranged. An emitter electrode 9 is arranged on the interlayer insulating film 8, and the plurality of p-type base regions 4 and the emitter regions 5 on the semiconductor substrate 1 are connected by the emitter electrode 9.

On the other hand, a collector electrode 10 is disposed on the entire back surface 12 of the semiconductor substrate 1 and is connected to the collector region 2.

Next, a method of manufacturing the IGBT shown in FIG. 1 will be described.

(A) First, a semiconductor substrate (silicon substrate) 1 to which n-type impurities such as phosphorus (P) and arsenic (As) having the same concentration as the n-type base region 3 are added is prepared. With the surface 11 of the silicon substrate 1 exposed, the gate oxide film 7 is formed on the surface 11 of the silicon substrate 1 by using a normal heat treatment method.
To form A polysilicon film is deposited using a CVD method or the like, and the polysilicon film is patterned by a normal lithography process and an RIE process to form a gate electrode 6.

(B) Next, a resist pattern having a window in the region where the p-type base region 4 is to be formed is formed. Using this pattern as a mask, boron (B) or the like is selectively formed on the upper and lower portions of the semiconductor substrate. Is diffused and activated by applying a predetermined heat treatment. A p-type base region 4 and a collector region 2 are formed. Further, a resist pattern having a window in a region where the emitter region 5 is to be formed is formed, and using this pattern as a mask, n-type impurities are diffused and activated by a predetermined heat treatment. An emitter region 5 is formed. After that, the resist pattern is removed.

(C) Next, a silicon oxide film to be the interlayer insulating film 8 is deposited on the surface 11 of the semiconductor substrate 1 by using the CVD method. Then, a resist pattern having a window in the central portion of the p-type base region 4 and a portion of the emitter region 5 is formed, and a contact hole in which the semiconductor substrate 1 is selectively exposed is formed using the pattern as a mask by RIE. I do. Finally, a metal film such as aluminum (Al) is deposited on the front surface 11 and the back surface 12 of the semiconductor substrate 1 by using a sputtering method or the like, and a desired patterning is performed. A metal film is buried in the contact hole, and an emitter electrode 9 and a collector electrode 10 are formed. Through the above steps, the IGBT shown in FIG. 1 can be manufactured.

In the step of forming the polysilicon film to be the gate electrode 6, dust existing inside the film forming apparatus may adhere to the element surface. One of the causes is that the polysilicon film is deposited not only on the wafer surface but also on the inner wall surface of the film forming container and the jig in the container, and the polysilicon film is peeled off. When the polysilicon dust adheres on the gate electrode 6, the protrusion shape of the dust is also reflected on the interlayer insulating film 8 formed thereon, and a pinhole is formed in the resist pattern at the time of forming the contact hole. . The interlayer insulating film in the pinhole portion is etched and removed together with the contact hole RIE, resulting in a short circuit between the emitter electrode 9 and the gate electrode 6. In the present invention, since the area of the gate electrode 6 can be made smaller than that of the related art when viewed from the surface 11 of the semiconductor substrate 1, the gate electrode 6
The probability that dust adheres to the top can be reduced.

Next, the operation of the IGBT shown in FIG. 1 will be described. By applying a positive static voltage higher than the gate threshold voltage to the gate electrode 6 with respect to the emitter electrode 9, an n-type inversion layer (channel) is formed on the surface of the outer peripheral portion 14 of the p-type base region 4, 5 and the n-type base region 3 become conductive, that is, the IGBT is turned on. When a voltage higher than that of the emitter electrode 9 is applied to the collector electrode 10, electrons are injected from the emitter region 5 to the n-type base region 3 via the channel, and holes are injected from the collector region 2 to the n-type base region 3. Is injected, and a current flows from the collector electrode 10 to the emitter electrode 9. Some of the holes injected into the n-type base region 3
The holes are eliminated by recombination with electrons injected from the GaN layer, and the remaining portions of the holes are discharged from the n-type base region 3 to the p-type base region 4. By reducing the number of holes discharged to the p-type base region 4, the hole density in the n-type base region 3 is increased, and the number of holes that recombine with electrons can be increased. Increasing the number of holes to be recombined means that the on-resistance (drift resistance) when carriers drift in the n-type base region 3 is substantially reduced, and the on-resistance of the IGBT is reduced.

Here, by reducing the size of the p-type base region 4 and the emitter region 5 and directly narrowing the region from which holes are discharged, the number of holes discharged to the p-type base region 4 is reduced. However, this method has its own limit due to the precision of fine processing. On the other hand, by increasing the predetermined interval 16 between the adjacent p-type base regions 4, even if the p-type base region 4 and the emitter region 5 are relatively narrowed when viewed from the whole chip, they are discharged to the p-type base region 4. Holes can be reduced.

When the latter method is used, since the gate electrode 6 is not arranged on the n-type base region 3 between the adjacent p-type base regions 4 as in the prior art, the width (area) of the gate electrode 6 is reduced. ) Does not spread. Therefore, the probability of occurrence of polysilicon dust that is randomly deposited on the gate electrode 6 does not increase. Therefore, the probability of occurrence of a short circuit between the gate electrode 6 and the emitter electrode 9 due to the dust on the gate electrode 6 does not increase. That is, even if the predetermined interval 16 between the adjacent p-type base regions 4 is increased, the probability of occurrence of short-circuit failure due to dust deposited on the gate electrode 6 can be suppressed.

Further, since the gate electrode 6 is not disposed on the n-type base region 3 between the adjacent p-type base regions 4 as in the conventional case, an increase in gate capacitance can be suppressed. Further, since the necessity of the terrace oxide film for reducing the gate capacitance is eliminated, the manufacturing process of the terrace oxide film can be reduced. Furthermore, by removing the terrace oxide film, the flatness of the interlayer insulating film 8 and the emitter electrode 9 disposed on the gate electrode 6 is improved, and the open failure of the emitter electrode 9 at the step portion is prevented. it can.

(Second Embodiment) The IGBT shown in the first embodiment of the present invention is different from the conventional IGBT structure in that the terrace oxide film is removed, the pattern shape of the gate electrode 6 is changed, and the like. However, the main effect of the present invention is achieved by changing the pattern shape of the gate electrode 6. In the second embodiment of the present invention, an IGBT capable of achieving the main effects of the present invention by a simpler method than the first embodiment will be described.

FIG. 2 is a sectional view showing a configuration of an IGBT according to a second embodiment of the present invention. As shown in FIG. 2, the IGBT according to the second embodiment of the present invention
The p-type base region 4 adjacent to the IGBT shown in FIG.
The semiconductor device further includes a terrace oxide film 15 shown in the related art, which is disposed between two gate electrodes 6 disposed therebetween. Terrace oxide film 15 is arranged between gate oxide film 7 and n-type base region 3.
The other configuration is the same as that of the IGBT shown in FIG. 1, and the description is omitted here.

According to the second embodiment of the present invention, the first
Similarly to the embodiment, the area of the gate electrode can be reduced, and the probability of generation of dust that is randomly deposited on the gate electrode 6 can be reduced. Therefore, a short circuit between the emitter electrode 9 and the gate electrode 6 due to dust can be suppressed. In addition, by arranging a terrace oxide film having the same thickness between the gate electrodes 6, the interlayer insulating film 8 can be formed.
Further, the flatness of the emitter electrode 9 is further improved as compared with the first embodiment. Further, the same effect as in the first embodiment of the present invention can be obtained by changing only the mask pattern for patterning the gate electrode 6 using the existing production line as it is.

[0031]

As described above, according to the present invention, a short circuit between a gate electrode and an emitter electrode can be reduced,
At the same time, it is possible to provide an insulated gate power semiconductor device capable of reducing the number of steps.

Further, according to the present invention, it is possible to provide an insulated gate power semiconductor device having a high speed operation performance and a low on-resistance.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of an IGBT according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of an IGBT according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a configuration of an IGBT according to the related art.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 collector region 3 n-type base region 4 p-type base region 5 emitter region 6 gate electrode 7 gate oxide film 8 interlayer insulating film 9 emitter electrode 10 collector electrode 11 front surface 12 back surface 13 central portion 14 outer peripheral portion 15 terrace oxide film 16 Predetermined interval

Claims (1)

[Claims] 1. A semiconductor substrate having a front surface and a back surface facing each other, a first conductivity type collector region disposed at a lower portion including a back surface of the semiconductor substrate, and a semiconductor substrate disposed at an upper portion including a surface of the semiconductor substrate. A two-conductivity-type base region; a plurality of first-conductivity-type base regions disposed at predetermined intervals above the second-conductivity-type base region; and selectively disposed above the first-conductivity-type base region. A second conductive type emitter region, and a gate insulating layer substantially only on the first conductive type base region disposed between the second conductive type base region and the emitter region on the surface of the semiconductor substrate. A gate electrode disposed via a film, an interlayer insulating film disposed on the gate electrode, connected to the first conductivity type base region and the emitter region, and disposed on the interlayer insulating film. Emitter Insulated gate power semiconductor device and having a pole.