JP2002190538A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate effect of gate bird's-beak phenomenon with respect to the channel width of each semiconductor element of a semiconductor integrated circuit device formed on the surface of a silicon substrate, by giving an oxidation resistance to a portion of each element isolation insulating film of the circuit device. SOLUTION: In the semiconductor integrated circuit device, the three-layer insulation film comprising a silicon oxide film 101, a silicon nitride film 102, and a silicon oxide film 103 in this order is formed on a silicon substrate 100. Then, the portion of the three-layer insulation film, which is present on the active region of each semiconductor element of the circuit device is etched and removed therefrom, so as to form each element isolation film comprising the three layers 101, 102, 103. In the oxidation processes required when manufacturing the semiconductor integrated circuit device, since the diffusions of oxygen radicals diffusing in the silicon oxide film are blocked by the silicon nitride film having oxidation resistance, the oxygen radicals will not reach the substrate, so that the gate electrode of each semiconductor element which comprises a polysilicon film is not oxidized in its contacting surface with each element isolation insulation film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a nonvolatile semiconductor memory device represented by a flash EEPROM has been highly integrated, and its elements have been miniaturized. In these nonvolatile semiconductor memory devices, in order to operate storage elements (memory cells) and control circuit elements normally, an insulating film for physically and electrically separating these elements is required. Is important. A region that separates element formation regions for forming elements is referred to as a device isolation region, and an insulating film formed in the device isolation region is referred to as a device isolation insulating film. In a semiconductor memory device, device isolation is performed by a selective oxidation method (LOCOS). ). That is, a silicon oxide film having a thickness of about 50 nm and a
A silicon nitride film having a thickness of about 400 nm is sequentially laminated, and after removing the silicon nitride film in the element isolation region by using photolithography technology and dry etching technology, thermal oxidation is performed to form a silicon oxide film. An element isolation insulating film is used. However, in the LOCOS method, a phenomenon called a bird's beak occurs at a boundary between an element isolation region and an element formation region (active region), in which an isolation oxide film cuts into the active region, thereby preventing miniaturization of the element. In recent years, as a new element isolation method suitable for miniaturization, (1) a silicon oxide film having a uniform thickness is formed on a silicon substrate surface, and (2) a silicon oxide film in an active region is formed by photolithography and dry etching technology. Patterning and removing (3)
A method of forming a side wall (sidewall) of a silicon oxide film on a side surface of a patterned silicon oxide film has been proposed (for example, US005595924A). FIG. 5 is a cross-sectional view showing a specific process of this element isolation method. First,
As shown in FIG. 5A, a silicon oxide film 501 having a uniform thickness is formed on the surface of a silicon substrate 500 by a chemical vapor deposition (CVD) method. Next, as shown in FIG. 5B, a photosensitive resist 502 is formed in the element isolation region by using a photolithography technique. Further, FIG.
As shown in (1), the silicon oxide film 501 in the active region is removed by dry etching using the photosensitive resist 502 as a mask to form a substantially vertical wall surface, and the photosensitive resist 502 is peeled off. Subsequently, as shown in FIG. 5D, a silicon oxide film 503 having good step coverage is grown using low-pressure CVD or the like. Finally, as shown in FIG. 5E, the silicon oxide film 503 is etched back by anisotropic dry etching to form a silicon oxide film side wall (sidewall) 504. In addition, as shown in FIG.
At the boundary between the active region and the element isolation region, the wall surface of the silicon oxide film 501 for element isolation is inclined (taper angle θ) 601.
By performing anisotropic etching having
(D) Step of FIG. 5E can be omitted. For example, Japanese Unexamined Patent Publication No. 4-340767 describes a flash EEPROM of a virtual ground line configuration (Virtual Ground Array) using element isolation formed through the manufacturing method of FIG. 5 or FIG. 7 and 8
FIG. 1 schematically shows the device structure of the flash EEPROM, including the peripheral circuit area. The memory cell uses a buried diffusion layer (BN +) as a bit line, and has a three-layer stacked structure having a floating gate, a control gate, and an erase gate. 7 and 8, reference numeral 700 denotes a silicon substrate having a P-type main surface, and reference numeral 701 denotes an element isolation made of a silicon oxide film formed by the process shown in FIG. Reference numeral 702 denotes an active region which is an inverted pattern of the element isolation 701. 703 is a sub-bit line BN +, 704
Is a floating gate made of a polycrystalline silicon film, 705 is a control gate made of a polycrystalline silicon film or a polycide film as a word line, and 706 is an erase gate made of a polycrystalline silicon film or a polycide film. 707 is a first gate insulating film formed on the silicon substrate 500, 708 is a second gate insulating film formed between the floating gate 704 and the control gate 705, and 709 is between the floating gate 704 and the erase gate 706. Third gate insulating film 71 formed in
Reference numeral 0 denotes an insulating film that insulates the control gate 705 from the erase gate 706. 711 is a gate of a transistor formed in the peripheral circuit region, 712 is an interlayer insulating film,
Reference numeral 13 denotes a metal wiring, which becomes a main bit line in the memory cell area. 714 is a contact. In the flash EEPROM shown here, the width of the active region defined by the element isolation insulating film interval is the channel width of the memory cell and the peripheral transistor. When a memory having the structure shown in FIGS. 7 and 8 is manufactured, many oxidation steps are performed after each gate electrode is formed. For example, after the formation of the floating gate electrode, the second gate oxide film 70 is formed.
5. During the thermal oxidation step in the third gate insulating film 709 and various ion implantations into the source / drain of the peripheral transistor, thermal oxidation is performed as an oxide film formation on the substrate surface for the purpose of preventing metal contamination. In these oxidation steps, oxygen radicals generated in the space between the cores easily diffuse in the element isolation silicon oxide film formed by CVD,
It reaches the floating gate electrode of the memory cell and the gate electrode of the peripheral transistor, and oxidizes the silicon substrate and the polycrystalline silicon film or polycide film that is the electrode material. In particular, oxidation progresses at both ends of the floating gate electrode or the bottom of the gate electrode, and the thickness of the gate oxide film at both ends of the bottom of the gate electrode becomes thick, so that a so-called gate bird's beak digging phenomenon of a silicon oxide film occurs.

[0003]

However, in the conventional example, the thickness of the gate insulating film sandwiched between the substrate and the floating gate electrode of the memory cell or the gate electrode of the peripheral transistor due to the oxidation step after the gate electrode is formed. There is a problem that the end portion is thickly oxidized and the ON current of the memory cell and the peripheral transistor is significantly reduced. The reason is that, since the element isolation insulating film is formed of a silicon oxide film formed by CVD, which has poor oxidation resistance, oxygen radicals are generated in various oxidation steps after formation of the floating gate electrode or after formation of the gate electrode. Diffusion in the element isolation silicon oxide film formed by CVD reaches the interface of the gate electrode-gate insulating film-semiconductor substrate, forms a large gate = bird's beak, reduces the effective channel width, and reduces the gate insulating film. This is because the effective film thickness is increased. Further, there is a problem that it is difficult to simply reduce the size of the memory cell, and it is difficult to reduce the cost by miniaturization. The reason is that the existence of the gate bird's beak causes the effective channel width of the memory cell to be smaller than the designed channel width. Further, since the size of the gate = bird's beak is unique to the manufacturing process, the smaller the device size, the larger the effect on the effective channel width unless the manufacturing process is changed. An object of the present invention is to provide a semiconductor memory device suitable for miniaturization, in which the gate-bird's beak is minute, the on-state current of the memory cell and the peripheral transistor is large, and the manufacture thereof.

[0004]

In order to achieve the above object, a method for manufacturing a semiconductor integrated circuit device according to the present invention has a multilayer structure of a silicon oxide film-an oxidizing film-a silicon oxide film on a silicon substrate. Forming a plurality of device isolation regions, forming a first gate insulating film in a device forming region between the device isolation regions, forming a first gate electrode on the first gate insulating film, Thermally oxidizing the surface of the first gate electrode. A step of forming a plurality of element isolation regions made of a silicon oxide film on a silicon substrate; a step of forming a sidewall of an oxidation-resistant film on a side surface of the element isolation region; and a step of forming an element formation region between the element isolation regions. Forming a first gate insulating film;
Forming a first gate electrode on the first gate insulating film; and thermally oxidizing a surface of the first gate electrode to form a first thermal oxide film on the surface. The method further includes a step of forming a second gate electrode on the first thermal oxide film, and a step of thermally oxidizing a surface of the second gate electrode to form a second thermal oxide film on the surface. Is what it is. Further, a semiconductor memory device according to the present invention includes a plurality of element isolation regions formed on a silicon substrate, and a first gate insulating film, a floating gate electrode, and a second gate insulating film formed between the element isolation regions in order from the bottom. And a nonvolatile memory transistor having a control gate electrode, wherein the element isolation region has a multilayer structure of a silicon oxide film-an oxidizing film-a silicon oxide film. Further, a semiconductor memory device according to the present invention includes a plurality of element isolation regions formed on a silicon substrate, and a first gate insulating film, a floating gate electrode, and a second gate insulating film formed between the element isolation regions in order from the bottom. And a non-volatile memory transistor having a control gate electrode,
The element isolation region has a side wall made of an antioxidant film on a side wall thereof. Further, the oxidation resistant film is a silicon nitride film. An oxidation-resistant insulating film layer is formed on a part of the element isolation insulating film. Therefore, in various thermal oxidation steps, oxygen radicals are blocked by the oxidation-resistant insulating film layer and cannot diffuse to the boundary region between the element isolation insulating film and the gate electrode. Generation is suppressed. As a result, the effective reduction of the channel width and the effective increase of the gate insulating film caused by the gate bird's beak do not occur,
There is no decrease in the on-current of the memory cell or the transistor.

[0005]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a sectional view showing a method for manufacturing a semiconductor memory device according to Embodiment 1 of the present invention. First, FIG.
As shown in (a), the surface of the silicon substrate 100 has CV
A silicon oxide film 101 is formed by D or thermal oxidation, and then a silicon nitride film 102 and a silicon oxide film 103 are sequentially formed by CVD. Next, as shown in FIG. 1B, a photosensitive resist 10 is formed by photolithography.
4 is patterned to cover the element isolation region. continue,
Using the photosensitive resist 104 as a mask, for example, the silicon oxide film 10 is placed in an atmosphere in which a mixed gas of carbon tetrafluoride (CF 4) and carbon trifluoride (CHF 3) is turned into plasma.
1. Exposing the silicon nitride film 102 and the silicon oxide film 103, the removal side surface has a constant inclined shape (taper).
Oxide film 103 / silicon nitride film 1
02. The silicon oxide film 101 is sequentially removed by etching. Further, when the photosensitive resist 102 is peeled off, FIG.
As shown in (c), the silicon oxide film 101, the silicon nitride film 102, and the silicon oxide film 1 have a tapered side surface.
03 is obtained. 7 and 8
For the flash EEPROM described with reference to
Regarding the case where the silicon oxide film / silicon nitride film / silicon oxide film of the present embodiment is used as the element isolation insulating film and the case where the conventional silicon oxide film (single layer) is used, the gate in the memory cell = Bird's Beak SE
A comparison of the M observation sketch is shown in FIG. As is clear from FIG. 2, when the element isolation structure of the present embodiment shown in FIG. 2A is used, gate = bird's beak is higher than when the conventional element isolation structure shown in FIG. 2B is used. It can be seen that the generation of 210 is significantly suppressed. (Embodiment 2) Next, Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 shows another manufacturing method for forming element isolation of a semiconductor memory device. First, FIG.
As shown in FIG. 1, a silicon oxide film 301 is formed on the surface of the silicon substrate 100 by CVD. Subsequently, FIG.
As shown in (1), the photosensitive resist 104 is patterned by a photolithography process so as to cover the element isolation region in the memory cell region. Next, the photosensitive resist 1
04 as a mask, for example, carbon tetrafluoride (CF4)
The silicon oxide film 103 is exposed to an atmosphere in which a mixed gas of carbon dioxide and carbon difluoride (CH2F2) is turned into plasma, so that the silicon oxide film 3 is removed so that the removal side surface becomes vertical.
01 can be removed by etching. Further, when the photosensitive resist 104 is peeled off, an element isolation silicon oxide film 302 having a vertical side surface as shown in FIG. 3C is obtained. Next, as shown in FIG. 3D, a silicon nitride film 303 having a thickness equal to or less than half of the minimum element separation interval is grown by CVD. Finally, as shown in FIG. 3E, the silicon nitride film 303 is etched back by anisotropic dry etching, and a sidewall 304 of the silicon nitride film is provided on the side wall of the silicon oxide film 302. Since the side surfaces of the element isolation insulating film formed in this manner are covered with a silicon nitride film having high oxidation resistance, oxygen radicals diffused in the silicon oxide film 302 in a thermal oxidation atmosphere reach the active region. And there is no room for gate bird's beak to occur at both ends of the bottom of the gate electrode. FIG.
As a device isolation insulating film of the flash EEPROM of FIG. 8, a case where a silicon oxide film having the silicon nitride film of this embodiment as a side wall is used and a case where a conventional silicon oxide film (single layer) is used are described. FIG. 4 shows a measurement result of the on-state current when the channel width of the memory cell is changed. In the case where the element isolation of the conventional B is used, it can be seen that as the channel width is reduced, the influence of gate = bird's beak is large and contributes to the ON current. On the other hand,
When the embodiment A is applied, the on-current keeps a linear relationship with the channel width. In the first and second embodiments, a mixed gas of CF4 and CHF3 or a mixed gas of CF4 and CH2F2 is used as a dry etching reaction gas for forming element isolation. In any gas that etches the silicon oxide film and the silicon nitride film when the silicon oxide film and the silicon nitride film are changed, etching conditions can be found under which the sidewalls of the silicon oxide film and the silicon nitride film are tapered from vertical. The most widely used reaction gases include the chemical formulas CF4, CHF3, CH2F2, C4F8, CO, S
A mixed gas composed of a combination of substances represented by F6 and Ar. In any combination, a silicon oxide film is formed by optimizing process parameters such as pressure, mixed gas flow rate, mixed gas flow ratio, and plasma generation voltage. In addition, the silicon nitride film can be etched so that the side wall becomes vertical or tapered.

[0006]

As described above, according to the present invention, the ON current of the memory cell and the peripheral transistor can be secured. The reason is that since an oxidation-resistant film exists in a part of the element isolation insulating film, oxygen radicals diffused in the element isolation film do not reach the gate electrode-silicon substrate interface, and the gate = This is because the occurrence of bird's beak is suppressed. Further, the semiconductor memory device is simply reduced (S
hrink) and can be easily manufactured. The reason is that the generation of gate = bird's beak is suppressed,
This is because the on-state current of the memory cell and the peripheral transistor changes linearly with respect to the channel width, and even if the semiconductor device is miniaturized, the proportional reduction side is established.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing Embodiment 1 of the present invention.

FIG. 2A is a cross-sectional view illustrating a semiconductor memory device of the present invention, and FIG. 2B is a cross-sectional view illustrating a conventional semiconductor memory device.

FIG. 3 is a process sectional view showing Embodiment 2 of the present invention.

FIG. 4 is a characteristic diagram showing experimental results comparing the performance of a semiconductor memory device of the present invention with that of a conventional semiconductor memory device.

FIG. 5 is a process sectional view showing a conventional example.

FIG. 6 is a process sectional view showing a conventional example.

FIG. 7 is a plan view showing a conventional semiconductor memory device.

FIG. 8 is a sectional view taken along line AA of FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 silicon substrate 101 silicon oxide film 102 silicon nitride film 103 silicon oxide film 104 photosensitive resist 200 silicon oxide film 201 floating gate 202 control gate 203 erase gate 301 silicon oxide film 302 element isolation silicon oxide film 303 silicon nitride film 304 silicon nitride film Side wall

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 29/788 29/792 F term (Reference) 5F032 AA12 CA17 CA21 DA02 DA25 DA53 5F048 AB01 BA16 BG01 BG03 BG11 5F083 EP03 EP22 GA09 JA53 KA06 KA07 LA12 LA16 NA08 NA10 PR39 5F101 BA12 BA13 BB02 BD35 BH03

Claims (7)

[Claims] A step of forming a plurality of device isolation regions having a multilayer structure of a silicon oxide film-an oxidation-resistant film-a silicon oxide film on a silicon substrate; Forming a film;
A method of manufacturing a semiconductor device, comprising: forming a first gate electrode on a gate insulating film; and thermally oxidizing a surface of the first gate electrode. A step of forming a plurality of device isolation regions made of a silicon oxide film on a silicon substrate; a step of forming a sidewall of an oxide film on a side surface of the device isolation region; Forming a first gate insulating film in an element formation region; and forming a first gate insulating film on the first gate insulating film.
A method of manufacturing a semiconductor device, comprising: forming a gate electrode; and thermally oxidizing a surface of the first gate electrode to form a first thermal oxide film on the surface. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a step of forming a second gate electrode on said first thermal oxide film, and a step of heat-treating said second gate electrode surface. Oxidizing to form a second thermal oxide film on the surface thereof. 4. The method according to claim 1, wherein the oxidation-resistant film is a silicon nitride film. 5. A plurality of device isolation regions formed on a silicon substrate, and a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode formed between the device isolation regions in order from the bottom. A semiconductor device comprising: a non-volatile memory transistor; and the element isolation region has a multilayer structure of a silicon oxide film-an oxide film-a silicon oxide film. 6. A plurality of device isolation regions formed on a silicon substrate, and a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode formed between the device isolation regions in order from the bottom. A semiconductor device comprising: a non-volatile memory transistor comprising: a semiconductor device; wherein the element isolation region has a side wall made of an oxidation-resistant film on a side wall thereof. 7. The semiconductor device according to claim 5, wherein said oxidation resistant film is a silicon nitride film.