JP2002182632A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the data bus occupation rate of an image layer memory by eliminating unnecessary repeated execution of the same composing operation even in the case that a display frame is not updated at display of a multi-layer picture. SOLUTION: A frame update flag 110 indicating whether the display frame has been updated or not for each frame and an update frequency flag 111 indicating whether a low frequency mode in which the update frequency of the display frame is lower than a reference value is set or not are provided. When the low frequency mode is set and the frame update flag 110 indicates that the display frame has been updated, a plurality of image layers 101 to 104 are successively read out from the picture layer memory 100 to generate a composite picture, and this image is not only preserved in the image layer memory 100 as a composite layer but also supplied to a display monitor 117. When the low frequency mode is set and the frame update flag 110 indicates that the display frame has been not updated, the preserved composite layer 105 is read out and supplied to the display monitor 117.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image display device for creating a composite image from a plurality of image layers stored in an image layer memory and displaying the composite image on a display monitor.

[0002]

2. Description of the Related Art For example, in a car navigation system, a composite image is created and displayed from a plurality of image layers such as a terrain image, a place name text image, a traffic information image, and a sightseeing guide image.

In creating such a multi-layer composite image, a conventional image display device sequentially reads out one line data of each image layer from the image layer memory while alternately using two image compositing memories. The operation of creating one line (image synthesizing operation) is completed within one horizontal scanning period of the display monitor, and the created one line is displayed in the next one horizontal scanning period of the display monitor.

[0004]

According to the above conventional image display device, the display frame on the display monitor can be updated, for example, by updating the content of a certain image layer in the image layer memory. However, the display frame is not always updated every frame. In some cases, the same image may be displayed on a display monitor over a plurality of frames.

However, in the conventional image display apparatus, even when the display frame is not updated, the same synthesizing operation is repeatedly executed. In addition, due to the useless image synthesizing operation, the data bus of the image layer memory is occupied for a long time.

Further, in the conventional image display device, since the synthesizing operation for all the image layers is completed within one horizontal scanning period of the display monitor, the number of layers to be synthesized is greatly restricted.

An object of the present invention is to realize a reduction in the image composition operation when the display frame on the display monitor is updated infrequently, and a reduction in the data bus occupancy of the image layer memory.

Another object of the present invention is to increase the number of layers that can be combined when the display frame on the display monitor is updated infrequently.

[0009]

To achieve the above object, the present invention provides an image display apparatus for creating a composite image from a plurality of image layers stored in an image layer memory and displaying the composite image on a display monitor. The result of image composition is stored in the image layer memory as a composite layer,
This composite layer is used for displaying a frame on a display monitor.

More specifically, a first image display device according to the present invention comprises a frame update flag indicating whether or not a display frame on a display monitor is updated for each frame, and an update of a display frame on the display monitor. A configuration including an update frequency flag indicating whether the frequency is a high frequency mode equal to or higher than a reference value or a low frequency mode lower than the reference value, and an image supply unit for supplying an image to be displayed to a display monitor. When the update frequency flag indicates the high frequency mode, the image supply unit sequentially reads a plurality of image layers from the image layer memory to create a composite image, and stores the composite image in the image layer memory. Function to supply to display monitor without saving, update frequency flag indicates low frequency mode, and frame update flag A function of sequentially reading a plurality of image layers from the image layer memory to create a composite image when indicating that there is an update, storing the composite image in the image layer memory as a composite layer, and supplying the composite image to a display monitor; When the update frequency flag indicates the low frequency mode and the frame update flag indicates no update, a function of reading out the composite layer stored in the image layer memory and supplying it to the display monitor is provided. is there.

The second image display device according to the present invention employs a configuration including an image supply unit for supplying an image to be displayed to a display monitor, wherein the image supply unit is provided on the display monitor. A frame counter for counting the number of display frames on the display monitor is provided so that the display frame is updated once in a plurality of frames, and the intermediate composite layer and the plurality of image layers are sequentially stored in the image layer memory. A function to read out and create a composite image, store the composite image in the image layer memory as a new intermediate composite layer, read the final composite layer from the image layer memory and supply it to the display monitor, Is displayed, the created composite image is saved as the final composite layer. In which it was decided to have a function to supply to Rutotomoni display monitor.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the first and second image display devices according to the present invention will be described in detail with reference to the drawings. Although an example of image composition for each line will be described, the composition unit is not limited to one line.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 shows a configuration of an image display device according to the embodiment. The image display device in FIG. 1 includes an image layer memory 100, a frame update flag 110, an update frequency flag 111, a display monitor 117, a drawing control circuit 119, and an image supply unit 120.

The image layer memory 100 has an area of a composite layer 105 in addition to the image layer areas of the first layer 101, the second layer 102, the third layer 103, and the fourth layer 104.

The frame update flag 110 is a flag indicating whether or not a display frame on the display monitor 117 is updated for each frame. The update frequency flag 111
This flag indicates whether the update frequency of the display frame on the display monitor 117 is equal to or higher than the reference value or the low frequency mode where the update frequency is lower than the reference value. Drawing control circuit 1
19 sets both flags 110 and 111 while monitoring the update status of the image layer memory 100.

The image supply unit 120 is a unit for supplying an image to be displayed to the display monitor 117, and includes an image layer memory control circuit 106, a data bus 107, a synchronization signal circuit 108, a layer input control circuit 109, a combination display mode selection circuit 112, an image combination circuit 113, and a first image combination memory 114.
, A second image synthesizing memory 115, an image data distribution circuit 116, and a layer output control circuit 118. The image layer memory control circuit 106 is a circuit that controls access to the image layer memory 100, and includes information for distinguishing between read (Read) and write (Write), a transfer start memory address, a transfer word number, and the like. , And exchanges data with the layer input control circuit 109 and the layer output control circuit 118 via the data bus 107. The synchronization signal circuit 108 generates a timing signal for synthesizing an image and a timing signal for displaying a synthesized image. Layer input control circuit 109
Receives the image synthesis timing signal, and issues a data transfer request to the image layer memory control circuit 106. At this time, the layer input control circuit 109 controls the first to fourth layers 101 to 101 stored in the image layer memory 100.
One of the read operation of the read operation 104 and the read operation of the composite layer 105 is selected and executed. The selection of these two operations is determined for each frame by the composite display mode selection circuit 112 based on the frame update flag 110 and the update frequency flag 111. The basic operation of the image synthesizing circuit 113 is that the line data of the first to fourth layers 101 to 104 are sequentially received, and the first and second image synthesizing memories 11
That is, an image synthesizing operation is performed by using 4, 115 alternately. These first and second image synthesizing memories 11
4, 115 perform an interleaving operation so that one is used for an image display operation when the other is used for an image display operation. That is, the first image synthesizing memory 11
4 is supplied to the image synthesizing circuit 113 via the image data distribution circuit 116, the final synthesized image left in the second image synthesizing memory 115 is The data is supplied to the display monitor 117 via the circuit 116. When the intermediate composite image created using the second image compositing memory 115 is supplied to the image compositing circuit 113 via the image data distribution circuit 116, the intermediate composite image remains in the first image compositing memory 114. The final synthesized image is supplied to the display monitor 117 via the image data distribution circuit 116. The layer output control circuit 118 operates when the final composite image is stored in the image layer memory 100 as the composite layer 105 according to the instruction of the composite display mode selection circuit 112.

FIG. 2 shows the layer input control circuit 10 in FIG.
9 shows a detailed configuration example of a layer output control circuit 118 and a layer output control circuit 118. The layer input control circuit 109 includes the line counter 20
2, a layer counter 203, a layer area setting register 204, a composite layer area setting register 205, a register selection circuit 206, an image layer data read request circuit 207, and an image data read register 2
09, the layer output control circuit 118 includes an image layer data write request circuit 212 and an image data write register 215. The layer input control circuit 109 determines that the layer to be read is the composite layer 105
A composite layer selection signal 200 indicating whether or not the signal is received from the composite display mode selection circuit 112. The composite layer selection signal 200 has a value of 1 for selecting the composite layer 105 when the update frequency flag 111 indicates the low frequency mode and the frame update flag 110 indicates no update, and otherwise, The value becomes 0 when the combination layer 105 is not selected. The layer output control circuit 118 outputs a composite layer write signal 201 indicating whether or not to store the composite image as the composite layer 105 to the composite display mode selection circuit 11.
Receive from 2. This composite layer write signal 201
Is 1 when the update frequency flag 111 indicates the low frequency mode and the frame update flag 110 indicates that there is an update, and otherwise, the synthetic layer storage is not selected. The value becomes 0.

In the layer input control circuit 109, the synchronization signal input from the synchronization signal circuit 108 includes a line counter 202 for counting the line number of the display frame on the display monitor 117, and a number of the layer to be synthesized during one line period. The counting timing is given to the counting layer counter 203. First to fourth layers 101 to 104
Are input to the register selection circuit 206. The layer area setting register 204 that stores the start address of each of the above and the composite layer area setting register 205 that stores the start address of the composite layer 105 And the layer counter 2
One register is selected by the register selection circuit 206 according to the value of the composite layer selection signal 200. At this time, when the composite layer selection signal 200 has the value 1, the value of the composite layer area setting register 205 is selected,
When the value of the composite layer selection signal 200 is 0, the register value of the layer corresponding to the value of the layer counter 203 is selected from the layer area setting register 204. The image layer data read request circuit 207 inputs the selected register value, the value of the line counter 202, and the composite layer selection signal 200, sets the address of the selected layer to the image layer memory control circuit 106, The signal 208 is issued. Data supplied from the image layer memory 100 via the data bus 107 is received by the image data read register 209, and a synthesis start signal 210 indicating the timing to start synthesis is output from the image layer data read request circuit 207. You. When reading of the required number of layers is completed, the image layer data read request circuit 207 sends a synthesis end signal 211 to the image layer data write request circuit 2.
12 is output.

In the layer output control circuit 118, when the image layer data write request circuit 212 receives the composite end signal 211, the composite layer write signal 2
The following operation is performed according to the value of 01. That is, when the composite layer write signal 201 has a value of 0, no operation is performed. When the composite layer write signal 201 has a value of 1, the address of the composite layer 105 is set in the image layer memory control circuit 106 based on the values of the line counter 202 and the composite layer area setting register 205, and a write request signal 213 is issued. . When the write request signal 213 is output to the image layer memory control circuit 106 in this manner, the image layer data write request circuit 212
Outputs an image synthesis memory read start signal 214 to the image synthesis circuit 113. The line data read from either of the image synthesizing memories 114 or 115 is temporarily stored in the image data writing register 215,
The data is supplied to the image layer memory 100 via the data bus 107.

FIG. 3 shows the operation of the image display device of FIG. 1 in the high frequency mode. That is, this is the case where the update frequency flag 111 indicates the high frequency mode. According to FIG. 3, the line data of the first to fourth layers 101 to 104 is sequentially read from the image layer memory 100 during a certain one line period. In response to this, the image synthesizing circuit 113 creates one line of the synthesized image using the first image synthesizing memory 114. This combined image line is read from the first image combining memory 114 and displayed on the display monitor 117 in the next line period. By repeating the above operation for the number of lines of one frame, one frame is displayed on the display monitor 117. However, the first image synthesizing memory 114 and the second image synthesizing memory 115 perform an interleaving operation every one line period.

FIG. 4 shows the operation of the image display device of FIG. 1 in the low frequency mode when there is a frame update. That is, this is the case where the update frequency flag 111 indicates the low frequency mode and the frame update flag 110 indicates that there is an update. According to FIG. 4, the line data of the first to fourth layers 101 to 104 is sequentially read from the image layer memory 100 during a certain one line period. In response to this, the image synthesizing circuit 113 creates one line of the synthesized image using the first image synthesizing memory 114. This combined image line is stored as the combined layer 105 in the image layer memory 100 during the line period, and the first image combining memory 11 is stored in the next line period.
4 and displayed on the display monitor 117. By repeating the above operation for the number of lines of one frame, one frame is displayed on the display monitor 117. However, the first image synthesizing memory 114 and the second image synthesizing memory 115 perform an interleaving operation every one line period.

FIG. 5 shows the operation of the image display device of FIG. 1 in the low frequency mode when no frame is updated. That is, this is a case where the update frequency flag 111 indicates the low frequency mode and the frame update flag 110 indicates no update. According to FIG. 5, the line data of the composite layer 105 is read from the image layer memory 100 during a certain one line period. This line data, that is, the synthesized image line is written to the first image synthesis memory 114 via the image synthesis circuit 113 as it is,
It is displayed on the display monitor 117 in the next line period. By repeating the above operation for the number of lines of one frame, the same frame as the previous frame is displayed on the display monitor 117. However, the first image synthesizing memory 114 and the second image synthesizing memory 115 perform an interleaving operation every one line period.

As described above, in the low frequency mode of the image display device of FIG. 1, the number of accesses to the image layer memory 100 increases by one per line in the case of the frame update compared to the high frequency mode. When there is no access mode, the number of times of access is drastically reduced as compared with the high frequency mode. Therefore, when the display frame on the display monitor 117 is updated infrequently, the image synthesis circuit 1
13 and the occupancy of the data bus 107 can be reduced.

FIGS. 6A to 6C show examples of updating display frames in the image display device of FIG. 1, respectively. FIG. 6A shows an example in which three out of four frames are different. The display frame update frequency in this case is 3 /
4 (= 0.75). In the example of FIG. 6B, four out of five frames are different, and the display frame update frequency is four.
/ 5 (= 0.80). In the example of FIG. 6C, two of the three frames are different, and the display frame update frequency is 2/3 (= 0.66).

In the example of FIG. 6A, the number of accesses to the image layer memory 100 when the high frequency mode operation of FIG. 3 is selected is Xa, and the low frequency mode operation of FIGS. 4 and 5 is selected. Assuming that the number of accesses to the image layer memory 100 is Ya, Xa / Ya = (4 × 4) / (5 × 3 +
1) = 16/16 Therefore, in the example of FIG. 6A, there is no difference in the number of accesses to the image layer memory 100 regardless of whether the high frequency mode or the low frequency mode is selected.

In the example of FIG. 6B, the number of accesses to the image layer memory 100 when the high-frequency mode operation of FIG. 3 is selected is Xb, and when the low-frequency mode operation of FIGS. 4 and 5 is selected. Assuming that the number of accesses to the image layer memory 100 is Yb, Xb / Yb = (4 × 5) / (5 × 4 +
1) = 20/21 Therefore, in the example of FIG. 6B, it is better to select the high frequency mode.
The number of times 0 is accessed is reduced.

In the example of FIG. 6C, the number of accesses to the image layer memory 100 when the high-frequency mode operation of FIG. 3 is selected is Xc, and when the low-frequency mode operation of FIGS. 4 and 5 is selected. Assuming that the number of accesses to the image layer memory 100 is Yc, Xc / Yc = (4 × 3) / (5 × 2 +
1) = 12/11 Therefore, in the example of FIG. 6C, it is better to select the low frequency mode.
The number of times 0 is accessed is reduced.

As described above, when one composite image is created from four layers, the display frame update frequency is set to 0.
The update frequency flag 1 is selected so that the high frequency mode is selected if the frequency is 75 (= 3/4) or more, and the low frequency mode is selected if the display frame update frequency is less than 0.75.
It can be seen that 11 should be set. In general, when N is an arbitrary integer of 2 or more within a range in which the data transfer speed of the image layer memory 100 can be in time, when one composite image is created from the N layers, the display frame update frequency is The update frequency flag 111 is set so that the high frequency mode is selected if the frequency is equal to or more than (N-1) / N, and the low frequency mode is selected if the display frame update frequency is less than (N-1) / N. Just set it.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
1 shows a configuration of an image display device according to the embodiment. The image display device in FIG. 7 includes an image layer memory 300, a display monitor 319, and an image supply unit 321, and displays a display frame (six-layer composite image) on the display monitor 319 once every two frames. Is updated at the rate of

The image layer memory 300 stores image layers of a first layer 301, a second layer 302, a third layer 303, a fourth layer 304, a fifth layer 305, and a sixth layer 306. In addition, it has a first combined layer 307 and a second combined layer 308.

The image supply unit 321 is a unit for supplying an image to be displayed to the display monitor 319, and includes an image layer memory control circuit 309, a data bus 310, a synchronization signal circuit 311 and a layer input control circuit. 312, a frame counter 313, a layer composition control circuit 314, an image composition circuit 315, a first image composition memory 316, and a second image composition memory 31.
7, an image data distribution circuit 318, and a layer output control circuit 320. Image layer memory control circuit 3
Reference numeral 09 denotes a circuit for controlling access to the image layer memory 300, which receives information for distinguishing read / write, a transfer start memory address, and the number of words to be transferred, and performs layer input control via the data bus 310. Circuit 3
12 and the layer output control circuit 320. The synchronization signal circuit 311 generates a timing signal for synthesizing an image and a timing signal for displaying a synthesized image. The frame counter 313 counts the frame number of the display frame on the display monitor 319 according to the image synthesis timing signal given from the synchronization signal circuit 311. The operation of the layer input control circuit 312 is as follows.
The value is determined based on the value of T.13. The image composition circuit 315
An image synthesizing operation is executed by using the first and second image synthesizing memories 316 and 317 alternately. These first and second
The image synthesizing memories 316 and 317 perform the same interleaving operation as in the first embodiment so that when one is used for an image synthesizing operation, the other is used for an image displaying operation. The layer output control circuit 320 stores the three-layer intermediate composite image in the image layer memory 300 in the first composite layer 307 according to the instruction of the layer composite control circuit 314.
The operation is performed when the final composite image of the six layers is stored as the second composite layer 308 in the image layer memory 300, respectively.

FIG. 8 shows the operation of the image display device of FIG. 7 during the odd frame display period. That is, this is a case where the frame counter 313 indicates an odd value. According to FIG. 8, the line data of the first to third layers 301 to 303 are sequentially read from the image layer memory 300 during a certain one line period. In response, the image composition circuit 315 creates one line of the intermediate composite image using the first image composition memory 316. This intermediate composite image line is stored in the image layer memory 3 during the line period.
00 is stored as the first composite layer 307. Further, during the line period, the line data of the second combination layer 308 is read from the image layer memory 300 and written to the first image combination memory 316. This line data is the last synthesized image line created in the immediately preceding even-numbered frame display period, and is read out from the first image synthesis memory 316 and displayed on the display monitor 319 in the next line period. By repeating the above operation by the number of lines of one frame, the same frame as the immediately preceding even frame is displayed on the display monitor 319. However, the first image combining memory 316 and the second image combining memory 317 perform an interleaving operation every one line period.

FIG. 9 shows the operation of the image display device of FIG. 7 during the even-numbered frame display period. That is, this is a case where the frame counter 313 indicates an even value. According to FIG. 9, during a certain one line period, the line data of the first combined layer 307 is read from the image layer memory 300, and subsequently the fourth to sixth layers 304 to 304 are read.
The line data 306 is sequentially read. In response, the image synthesizing circuit 315 sets the first image synthesizing memory 31
6 is used to create one line of the final composite image. This final combined image line is stored in the image layer memory 300 as the second combined layer 308 during the line period, and is read out from the first image combining memory 316 during the next line period to be displayed on the display monitor. 319 is displayed. By repeating the above operation by the number of lines of one frame, the updated one frame is displayed on the display monitor 319. However, the first image combining memory 316 and the second image combining memory 317 perform an interleaving operation every one line period.

As described above, in the image display device of FIG.
By setting the frequency of updating the display frame on the display monitor 319 to once every two frames, it is possible to increase the number of layers to be combined as compared with the related art.

When M is an arbitrary integer of 3 or more, the display frame can be updated once every M frames. For example, when the frame counter 313 indicates a value of 1, a plurality of image layers are sequentially read from the image layer memory 300 to create an intermediate composite image, and the intermediate composite image is stored in the image layer memory 300 as a first image. The image data is stored as a composite layer (intermediate composite layer) 307, and the second composite layer (final composite layer) 308 is read from the image layer memory 300 and supplied to the display monitor 319. When the frame counter 313 indicates any value from 2 to M-1, the intermediate composite layer 307 and a plurality of image layers are sequentially read from the image layer memory 300 to create an intermediate composite image. In addition, the intermediate composite image is stored as a new intermediate composite layer 307 in the image layer memory 300, and the final composite layer 3 is stored in the image layer memory 300.
08 is read and supplied to the display monitor 319. Further, when the frame counter 313 indicates the value M, the intermediate composite layer 307 and the plurality of image layers are sequentially read from the image layer memory 300 to create a final composite image, and the final composite image is stored in the image layer. It is stored in the memory 300 as the final composite layer 308 and is supplied to the display monitor 319. Here, the number of layers to be combined is arbitrary within a range in which the data transfer speed of the image layer memory 300 can be in time.

[0036]

As described above, according to the first image display device of the present invention, the optimum image synthesis display mode is selected according to the frame update flag and the update frequency flag. It is possible to reduce the image combining operation when the frequency of updating the display frame on the monitor is low, and to reduce the data bus occupancy of the image layer memory.

Further, according to the second image display device of the present invention, the image combining operation is controlled according to the value of the frame counter while the intermediate combined image and the final combined image are stored in the image layer memory. Therefore, when the display frame on the display monitor is updated infrequently, the number of layers that can be combined can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration example of a layer input control circuit and a layer output control circuit in FIG. 1;

FIG. 3 is a timing chart illustrating an operation of the image display device of FIG. 1 in a high frequency mode.

4 is a timing chart illustrating an operation of the image display device in FIG. 1 in a low frequency mode when a frame is updated.

5 is a timing chart showing an operation of the image display device of FIG. 1 in a low frequency mode when no frame is updated.

FIGS. 6A to 6C are conceptual diagrams each showing an example of updating a display frame in the image display device of FIG. 1;

FIG. 7 is a block diagram illustrating a configuration of an image display device according to a second embodiment of the present invention.

8 is a timing chart showing an operation of the image display device of FIG. 7 in an odd frame display period.

9 is a timing chart showing an operation of the image display device of FIG. 7 during an even frame display period.

[Explanation of symbols]

 100, 300 Image layer memories 101 to 104, 301 to 306 Image layers 105, 307, 308 Composite layers 106, 309 Image layer memory control circuits 107, 310 Data buses 108, 311 Synchronous signal circuits 109, 312 Layer input control circuits 110 Frames Update flag 111 Update frequency flag 112 Synthesis display mode selection circuit 113,315 Image synthesis circuit 114,316 First image synthesis memory 115,317 Second image synthesis memory 116,318 Image data distribution circuit 117,319 Display monitor 118, 320 Layer output control circuit 119 Drawing control circuit 120, 321 Image supply unit 313 Frame counter 314 Layer synthesis control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B069 AA01 BA03 BB04 BC02 DD15 LA07 LA12 5C082 AA13 AA24 BA02 BA12 BB22 BB26 BB46 CA56 CB03 DA65 MM02

Claims (2)

[Claims] 1. An image display device for creating a composite image from a plurality of image layers stored in an image layer memory and displaying the composite image on a display monitor, wherein a display frame on the display monitor is updated every frame. A frame update flag indicating the presence / absence of a frame, an update frequency flag indicating whether the update frequency of the display frame on the display monitor is equal to or higher than a reference value or a low frequency mode where the update frequency is lower than the reference value. An image supply unit for supplying an image to the display monitor, wherein the image supply unit sequentially reads a plurality of image layers from the image layer memory when the update frequency flag indicates a high frequency mode. Read to create a composite image, and store the composite image in the image layer memory without storing it in the image layer memory. A function for supplying to a ray monitor, when the update frequency flag indicates a low frequency mode, and the frame update flag indicates that there is an update, a plurality of image layers are sequentially read from the image layer memory to generate a composite image. A function of creating and storing the combined image as a combined layer in the image layer memory and supplying the combined image to the display monitor, the update frequency flag indicating a low frequency mode, and the frame update flag indicating no update An image display device that reads out the composite layer stored in the image layer memory and supplies the composite layer to the display monitor. 2. An image display device for creating a composite image from a plurality of image layers stored in an image layer memory and displaying the composite image on a display monitor, wherein the image display device supplies an image to be displayed to the display monitor. An image supply unit, wherein the image supply unit includes a frame counter for counting display frames on the display monitor so that display frames on the display monitor are updated once per a plurality of frames; And sequentially reading an intermediate composite layer and a plurality of image layers from the image layer memory to create a composite image, and storing the composite image as a new intermediate composite layer in the image layer memory; Function to read out the final composite layer from the computer and supply it to the display monitor , If the frame counter indicates a specific value,
An image display device having a function of storing the created composite image as the final composite layer and supplying the composite image to the display monitor.