JP2002182616A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of a degradation phenomenon. SOLUTION: During a display period, a correction voltage is applied to each signal electrode X1-XN where each of the signal electrodes X1-XN sequentially crosses each of the scanning electrodes Y1-YM from one end to the other end so that an applied time is sequentially longer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simple matrix drive type liquid crystal display device used for OA equipment such as personal computers and word processors, multimedia information terminals, AV equipment, game equipment and the like.

[0002]

2. Description of the Related Art With the spread of personal computers and word processors, as display devices for them,
Large CRT (Cathode-Ra) with large power consumption
In place of y-Tube), a liquid crystal display device that is lightweight, thin, and can be driven by a battery is widely used.

A liquid crystal display device of a simple matrix drive system is a liquid crystal panel in which a plurality of parallel scanning electrodes and a plurality of parallel signal electrodes are arranged so as to intersect in a matrix with a liquid crystal layer interposed therebetween. And a scanning side driving circuit for outputting a scanning voltage to each scanning electrode, and a signal side driving circuit for outputting a signal voltage to each signal electrode. In a simple matrix drive type liquid crystal display device, liquid crystal is driven between a scanning electrode and a signal electrode to which a voltage is applied, respectively. Since a non-linear element such as a thin film transistor for driving each of the arranged pixel electrodes is not required, the manufacturing is relatively easy and the manufacturing cost can be reduced.

However, in such a simple matrix driving type liquid crystal display device, since a scanning voltage is applied to one end of the scanning electrode, the scanning electrode becomes longer as the display screen becomes larger. First, the voltage applied to one scanning voltage sequentially decreases along the longitudinal direction, and a difference occurs in the voltage applied to the liquid crystal layer at a portion intersecting each signal electrode. As a result, a gradation phenomenon in which a luminance difference occurs in a liquid crystal portion driven by one scanning electrode as the distance from the scanning side driving circuit increases. Such a gradation phenomenon is caused by the fact that the width of the scanning electrode and the signal electrode is reduced due to the increase in the resolution of the liquid crystal display device, and the length of the scanning electrode and the signal electrode is increased. As the distance from the circuit increases, the amount of voltage drop generated in one scan electrode increases, so that it becomes more remarkable.

A method for solving this gradation phenomenon is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-212475.
Japanese Patent Application Laid-Open No. Hei 9-21475 discloses a signal driving IC for driving a plurality of signal electrodes, and a signal driving IC for driving each signal electrode arranged from one end to the other end of the scanning electrode. A configuration is disclosed in which an IC is provided with a resistor that gradually decreases, and a voltage applied to each signal electrode arranged from one end to the other end of each scan electrode increases stepwise. In such a configuration, the voltage that sequentially decreases in one scanning electrode is corrected by increasing the voltage of each signal electrode that sequentially crosses each scanning electrode in a stepwise manner. Appropriate voltage is applied to each signal electrode not only during the display period but also during the non-display period. Therefore, the voltage applied to the intersection with the scanning electrode is also corrected during the non-display period.

[0006]

Problems to be Solved by the Invention
In the configuration disclosed in Japanese Patent Application Laid-Open No. 5-105, one signal driving IC is used.
The plurality of signal electrodes to which a voltage is applied are controlled as one unit. Normally, a signal driving IC applies a voltage in units of 100 or more signal electrodes as one unit.
The gradation phenomenon may not be corrected with high accuracy. When the resistance value of each scanning electrode increases due to the enlargement of the display screen and the required correction amount increases, if the same voltage is applied to 100 or more signal electrodes by the signal driving IC, A luminance difference may occur at the boundary between adjacent signal driving ICs, and display unevenness may occur.

One signal driving IC is provided for each horizontal scanning period set in a non-display period including a vertical blanking period.
The correction data is generated based on the display data using the plurality of signal electrodes driven by the unit as one unit, and the generated correction data is intermittently applied to the plurality of signal electrodes via each signal driving IC as the display data. , And the number of times the correction data is applied is stepwise increased for each signal driving IC arranged from one end to the other end of each scanning electrode. Also in this case, to increase the correction accuracy,
In order to reduce the number of signal electrodes in one unit controlled by the signal driving IC and to apply correction data, it is necessary to increase the number of times each signal electrode is scanned. However, since the number of times of scanning each signal electrode to apply the correction data is set within the vertical blanking period, there is a limit to increasing the number of times of scanning each signal electrode. Also, if the number of scans of each signal electrode increases, the number of correction data may increase and the circuit scale may increase, and it is not easy to improve the correction accuracy. In this case, to increase the correction accuracy,
It has also been proposed to employ a pulse width modulation drive system in which the correction data applied intermittently to the signal drive IC is pulse-modulated and the amount of correction voltage is changed stepwise, but a pulse width modulation drive system is employed. Then, a dedicated signal driving IC, a control circuit, and the like are required, which may increase the cost.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide a liquid crystal driving device in which the occurrence of a gradation phenomenon is suppressed by using a low-cost and small-scale circuit system. .

[0009]

According to the liquid crystal display device of the present invention, a plurality of scanning electrodes to which a scanning voltage is applied, and each of the scanning electrodes are arranged so as to be orthogonal to each other with a liquid crystal layer interposed therebetween. A plurality of signal electrodes to each of which a signal voltage is applied, a scan-side drive circuit for applying a voltage to each scan electrode,
A liquid crystal display device having a signal side driving circuit for applying a voltage to each signal electrode, wherein in a non-display period, each signal electrode sequentially intersects from one end to the other end of each scanning electrode, It is characterized in that the correction voltage is applied such that each application time becomes longer sequentially.

[0010] As the application time of the correction voltage to each signal electrode becomes longer, the rate of increase of the application time decreases.

The rate of increase of the application time of the correction voltage to each signal electrode is constant.

The correction voltage is applied to a predetermined number of signal electrodes set in advance, and the number of signal electrodes to which the correction voltage is applied can be changed.

The signal side driving circuit can output a selection voltage and a non-selection voltage according to the shift data.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. The liquid crystal display device includes a liquid crystal panel 1 in which a plurality of parallel scanning electrodes Y1 to YM and a plurality of parallel signal voltages X1 to XN are arranged to be orthogonal to each other with a liquid crystal layer interposed therebetween. A signal-side drive circuit 2 with a serial mode for applying a signal voltage based on display data to each of the signal electrodes X1 to XN, and a scan-side drive circuit 3 for sequentially applying a scan voltage to each of the scan electrodes Y1 to YM. A control circuit 4 for controlling the signal-side drive circuit 2 with serial mode and the scan-side drive circuit 3,
And a power supply circuit 5 for supplying a drive voltage to the signal side drive circuit 2 with serial mode and the scan side drive circuit 3.

The signal-side driving circuit 2 with serial mode performs parallel mode driving in which display data is applied to each of the signal voltages X1 to XN during a display period, and each signal electrode X during a non-display period.
It is configured by a signal drive IC with a serial mode that can also perform a serial mode drive for sequentially applying a correction voltage to 1 to XN. The signal drive IC with the serial mode has a shift register for driving serial data, like the scan side drive circuit 3.

Further, the liquid crystal display device is provided with a gradation correction circuit 10 for controlling the signal side drive circuit 2 with a serial mode while suppressing the gradation phenomenon. The gradation correction circuit 10 is a line counter 6 for detecting a non-display period, and a gradation control signal generation for receiving a signal indicating the non-display period from the line counter 6 and outputting a control signal to the signal side driving circuit 2 with serial mode. It has a circuit 7 and a correction data ROM 8 in which preset correction data is stored.

The power supply circuit 5 generates five types of voltages V1 to V5 to be supplied to the signal drive circuit 2 with serial mode and the scan drive circuit 3. The voltages V1 to V5 are set so as to satisfy the following equation (1).

V1>V2>V3>V4> V5 (1) The voltage V3 is given to the signal-side drive circuit 2 with serial mode and the scan-side drive circuit 3, respectively. It is applied to each of the scanning electrodes. The voltage V1 and the voltage V5 are given only to the scanning side drive circuit 3, and the voltage V1 is applied to the sequentially selected scanning electrodes.
1 and the voltage V5 are applied according to the AC conversion signal FR. The voltage V2 and the voltage V4 are applied only to the signal drive circuit 2 with the serial mode, and the voltage V2 and the voltage V4 are applied to the sequentially selected signal electrodes in accordance with the alternating signal FR.

The line counter 6 of the gradation correction circuit 10 detects a non-display period, and outputs a scan clock signal LP output from the control circuit 4.
And a scanning start signal YD. The line counter 6 counts using the scan clock signal LP, detects a non-display period based on the timing synchronized with the scan start signal YD, generates a non-display period signal DET, and generates the generated non-display period signal DET. To the gradation control signal generation circuit 7.

The gradation control signal generation circuit 7 includes:
Non-display period signal DE output from line counter 6
T, a data shift clock XCK output from the control circuit 4, a scan clock signal LP, and an AC signal FR
Are also input, and an external clock signal CLK, which is a constant pulse signal, is also input from the outside. Further, the gradation control signal generation circuit 7 includes:
A correction data ROM 8 in which correction data is stored is connected.

The gradation control signal generating circuit 7 is adapted to switch the serial mode switching signal S for switching the signal side drive circuit 2 with serial mode to the serial mode based on the non-display period signal DET output from the line counter 6.
GR and a shift direction signal SLR for inverting the shift direction of the correction voltage sequentially applied to each signal electrode in the serial mode, and the generated serial mode switching signal SGR and shift direction signal SLR are serialized. Output to the mode-side signal-side drive circuit 2. Further, the gradation control signal generation circuit 7 also generates the shift clock signal SLP and the shift data SYD indicating the timing of sequentially applying the correction voltage to each signal electrode based on the externally input external clock signal CLK. I do. Note that the shift clock signal SLP is the correction data RO
Based on the correction data stored in M8, correction is made to a pulse interval proportional to the size of the correction data.

The generated shift data SYD and shift clock signal SLP are output to signal side drive circuit 2 with serial mode.

The gradation correction circuit 10 is constituted by a signal side driving IC with a serial mode based on the synchronization timing of the shift data signal SYD and the shift clock signal SLP generated by the gradation control signal generation circuit 7 during the non-display period. A correction voltage for suppressing the gradation phenomenon is applied to the signal electrode driving circuit 2 with serial mode from the signal electrodes X1 to XN to correct the luminance difference (gradation phenomenon) on the screen of the liquid crystal panel 1. In the non-display period, the signal electrode X
When the correction voltage is applied to 1 to XN, the non-selection voltage V3 is applied to all the scan electrodes Y1 to YM.

Tables 1 (a) to 1 (c) show an example of the operation of the signal side drive circuit 2 with serial mode, respectively.
In Table 1 (a), the serial mode switching signal SGR
Is in the low-level, and is driven in the serial mode. The output voltage of the signal side driving circuit 2 with the serial mode is determined by the AC signal FR and the shift data signal SYD output from the gradation control signal generation circuit 7. When the shift data signal SYD is at the HIGH level, and when the AC conversion signal FR is at the HIGH level, the output voltage (correction voltage) of the signal drive circuit 2 with the serial mode becomes the selection voltage V2, and conversely, the AC conversion signal FR Is LOW
Signal level drive circuit 2 with serial mode
Becomes the selection voltage V4. Shift data signal S
When YD is at the LOW level, the non-selection voltage V3 is always output as the output voltage of the signal side drive circuit with serial mode 2 regardless of the output level of the AC conversion signal FR.

Table 1 (b) shows that when the output number of the signal side drive circuit 2 with serial mode is 240, the shift direction signal S
This indicates that the direction in which the voltage is applied to each signal electrode in order is reversed according to LR. When the number of shift bits is 1, if the shift direction signal SLR is at the HIGH level, the data transfer is from the output terminal (X1) to the output terminal (X240), and the shift direction signal SL
If R is at the LOW level, on the contrary, the data transfer is from the output terminal (X240) to the output terminal (X1). When the number of shift bits is three, three adjacent bits are used.
Data transfer is performed sequentially for each of the two output terminals.
As shown in (b), when the shift direction signal SLR is at the LOW level, data transfer is performed at three output terminals (X23).
8, X239, and X240), and thereafter, data is simultaneously transferred to each of the three output terminals and shifted to the output terminals (X1, X2, X3). If the shift direction signal SLR is at a HIGH level, three output terminals (X1, X2, X3) to three output terminals (X23)
8, X239 and X240) are sequentially transferred three by three.

Table 1 (c) shows a generalized data transfer state of a number equal to the number of shift bits a when the number of outputs of the signal side drive circuit 2 with serial mode 2 is p and the number of shift bits is a. , And data transfer is performed sequentially for each output terminal.

[0028]

[Table 1] In such a liquid crystal display device, during the display period, each of the scanning electrodes Y1 to YM is sequentially scanned, and during the scanning, the signal electrodes X1 to XN are provided with a signal arranged close to the scanning side driving circuit 3. A signal voltage is applied in order from the electrode X1. The scanning-side drive circuit 3 sequentially outputs 1 from the scan electrode Y1 based on the scan clock signal LP, the AC signal FR, and the scan start signal YD output from the control circuit 4.
When the AC signal FR output from the control circuit 4 is selected at a high level, the selection voltage V supplied from the power supply circuit 5 to the selected scan electrode is selected.
5, and when the AC conversion signal FR is at the LOW level, the selection voltage V1 supplied from the power supply circuit 5 is applied to the selected scanning electrode. Then, a non-selection voltage V3 is applied to the non-selected scanning electrodes.

In this case, since the serial mode switching signal SGR is not output from the gradation control signal generating circuit 7, the signal side driving circuit 2 with serial mode is driven in the parallel mode, and is output from the gradation control signal generating circuit 7. In response to the display data signal D output from the control circuit 4 based on the scan clock signal LP and the AC conversion signal FR, the AC conversion signal FR and the display data signal D are at the same level (for example, both are HIGH).
(H level or LOW level), the selection voltage V supplied from the power supply circuit 5 is applied to the selected signal electrode.
2 is applied, and when the alternating signal FR and the display data signal D are at different levels (one is HIGH level and the other is LOW level), the power is supplied from the power supply circuit 5 to the selected signal electrode. Is applied. Thereby, the voltage applied to the liquid crystal layer of the liquid crystal panel 1 is converted into an alternating current. Here, the selection voltages V1, V2, V4, V5 and the non-selection voltage V3 are set so as to satisfy the above-mentioned equation (1).

The liquid crystal layer of the liquid crystal panel 1 includes scanning electrodes Yj.
A voltage corresponding to the potential difference between the scanning electrode Yj and the signal electrode Xi is applied to a liquid crystal portion (liquid crystal capacitor, pixel PIX (i, j)) disposed at the intersection of the liquid crystal portion and the signal electrode Xi. Changes according to the effective voltage applied to the liquid crystal capacitance. Therefore, by controlling the voltage applied to each of the signal electrodes X1 to XN and each of the scanning electrodes Y1 to YM, all the pixels PIX (1,1) to PIX (1,1) in the liquid crystal panel 1 are controlled.
The display state of PIX (N, M) is controlled, and an image based on the display data is displayed.

On the other hand, the non-display period of the liquid crystal panel 1 is detected by the line counter 6 and the gradation control signal generation circuit 7 outputs the serial mode switching signal SG.
When R is output, the signal side drive circuit 2 with serial mode
Are switched from parallel drive, which is normal signal side drive, to serial mode drive by a serial mode switching signal SGR. In the signal-side drive circuit 2 with serial mode, in the case of serial mode drive, a correction voltage is applied to each signal electrode based on the shift data signal SYD and the shift clock signal SLP from the gradation control signal generation circuit 7, and correction is performed. The time during which the voltage is applied becomes longer as the signal electrode is disposed farther from the scanning drive circuit 3 side.

FIG. 2 is a timing chart showing a non-display period (a blanking period) as a period for performing correction. The control circuit 4 outputs only one pulse of the scanning start signal YD indicating the display period in synchronization with the scanning clock signal LP. In the case of performing simultaneous driving with a general CRT, the timing of the scanning start signal YD and the scanning clock LP is once every two frames, and the non-display period corresponding to the vertical blanking period of the CRT driving. Exists. In FIG. 2, a non-display period is set after the display period of the second frame. This non-display period is detected by counting the number of pulses of the scan clock signal LP after the output of the pulse of the scan start signal YD. When the simultaneous driving with the CRT is not performed, the non-display period is one in two frames.
The non-display period may be present once in one frame instead of the non-display period, but in the present embodiment, the non-display period exists once in two frames, and the SVGA (Super
Video Graphic Array: 800 × 3
A description will be given of a signal voltage correction for each of the signal electrodes X1 to XN that suppresses a gradation phenomenon in a non-display period by taking an example of a liquid crystal display device that performs dual scan driving of (RGB) × 600 dots. The number of columns of the signal electrodes is 2400 columns (800 × 3) because SVGA has three colors of RGB, and the number of shift bits of the signal side drive circuit 2 with serial mode is 3.

FIG. 3 is a timing chart of the application of the correction voltage to the signal electrode for suppressing the gradation phenomenon during the non-display period. When the pulse of the scanning start signal YD indicating the display period is output, the scanning clock L in one frame is output.
P is output for 300 pulses. The non-display period is the 300th scan clock signal L indicating the display period of the second frame.
The pulses of the 28 scan clock signals LP after the output of P are set to the 301-328th pulse section.

The enlarged portion of the non-display period shown in FIG. 3 shows the operation state of each signal in the non-display period of the liquid crystal display device of the present embodiment. When the 301st pulse of the scan clock signal LP is output from the start of two frames, the line counter 6 outputs the non-display period signal DET to the gradation control signal generation circuit 7. The gradation control signal generation circuit 7 outputs the non-display period signal DET to the line counter 6.
And outputs a serial mode switching signal SGR to the signal side drive circuit 2 with serial mode. Further, the gradation control signal generating circuit 7 outputs the shift direction signal SLR to the signal side driving circuit 2 with the serial mode, and in this non-display period, the farthest side from the scanning side driving circuit 3 is opposite to the display period. The signal electrode X1 disposed closest to the scanning side drive circuit 3 from the signal electrode XN disposed
Until the correction voltage is applied.

In the present embodiment, the scanning direction in which the signal voltage is applied to the signal electrodes in the display period is from the first row of signal electrodes arranged close to the scanning side drive circuit 3 to the 2400th row. In the non-display period, on the contrary, a selection voltage V2 having a different application time is applied to each signal electrode as a correction voltage from the signal electrodes in the 2400th column toward the first column (actually, R, G). , B3 color, the signal electrode is 240
Although there are 0 columns, 800 columns to which the correction voltage is applied since the correction voltage is collectively applied to the signal voltages of the three colors RGB will be described below).

In the non-display period, the shift direction signal SL
After the output of R, the first shift clock signal SLP
When the shift data signal SYD is output in synchronism with the above, the correction voltage V2 is applied from the scanning side drive circuit 3 to the signal electrode of the 800th column on the far side. When the shift data signal SYD is output in synchronization with the next shift clock signal SLP, the correction voltage V2 is applied from the scanning drive circuit 3 to the farther 800th and 799th column signal electrodes.
Hereinafter, every time the shift data signal SYD is output, the correction voltage V2 is sequentially changed from the signal electrode arranged on the far side of the scanning side driving circuit 3 to the signal electrode arranged near the scanning side driving circuit 3. Is applied. As a result, the voltage applied to each signal electrode is such that the application time of the selection voltage V2, which is the correction voltage applied to each signal electrode, is changed from the 800th column of the signal electrodes far from the scanning side driving circuit 3 to the scanning side. The shift clock signal SLP sequentially decreases by one pulse interval toward the first column of the signal electrode close to the drive circuit 3. As a result, the application time of the correction voltage V2 to the signal electrode located farther from the scanning side drive circuit 3 is the longest, and the application time of the correction voltage V2 to the signal electrode is sequentially increased as the scanning electrode 3 approaches the scan side drive circuit 3. Be shorter.
As described above, in the non-display period, the correction voltage is applied so that the application time becomes longer as the distance from the scanning-side drive circuit 3 increases with respect to each signal electrode.
In each scanning electrode, a voltage drop that increases as the distance from the scanning side drive circuit 3 increases is corrected. As a result, a gradation phenomenon of an image displayed on the liquid crystal panel 1 is suppressed.

The correction voltage applied to the signal electrode becomes the non-selection voltage V3 when the signal electrode is not selected, and becomes the selection voltage V2 or V4 when the signal electrode is selected.
Which of the selection voltages V2 and V4 is selected is determined by the alternating signal FR as described above. In the non-display period, the scanning side driving circuit 3 outputs the non-selection voltage V3 to each scanning electrode. As a result, the applied voltage value to the liquid crystal layer is V2-V3 (plus value) or V3-V4
(Negative value).

In this case, the gradation control signal generation circuit 7 accesses the correction data ROM 8, reads correction data given in advance to the correction data ROM 8, and outputs the external clock signal input to the gradation control signal generation circuit 7. CLK based on the shift clock signal S
The LP pulse interval is determined and output based on the magnitude of the read correction data. In this embodiment, the number of shift clock signals SLP output during the non-display period is 800 because the number of shift bits of the signal-side drive circuit 2 with serial mode is 3 in this embodiment, and thus 800 shift clock signals are output. A shift data signal SYD is also output for each SLP. The selection voltage V2 or V4, which is a correction voltage applied to each signal electrode, is output based on the shift clock signal SLP, and the pulse interval of the shift clock signal SLP decreases as the pulse changes from the first pulse to the 800th pulse. Correction data is set. As a result,
800 from the first pulse of shift clock signal SLP
The pulse interval gradually decreases as the third pulse starts. As a result, the application time of the correction voltage gradually increases. However, as the application time of the correction voltage increases, the increasing rate of the application time decreases. From this, the correction data ROM
8, the total memory capacity of the correction data can be reduced, and the circuit scale and cost can be reduced.

By making the pulse interval between the first pulse and the 800th pulse of the shift clock signal SLP constant, even if the rate of increase of the correction voltage application time is constant, the total memory capacity of the correction data is maintained. Is 80 from the first pulse of the aforementioned shift clock signal SLP.
The same effect as in the present embodiment can be obtained by making the pulse interval of the 0th pulse equal to the total memory capacity of the correction data obtained by sequentially reducing the pulse interval.

Table 2 is a specific example of the above-described correction data previously provided to the correction data ROM 8. The correction data corresponds to the pulse width (application time) of the correction voltage to each signal electrode in the 800th column to the first column. Accordingly, as shown in FIG. 3, the pulse of the shift clock signal SLP is 1
The interval (period) between pulses of the shift clock signal SLP becomes smaller as the shift clock signal changes from the 800th to the 800th. Therefore, although the correction voltage is applied for a longer time at the 800th column of the signal electrode, the correction voltage is applied for a longer time. The rate of increase is smaller.

[0041]

[Table 2] Table 3 shows the application time (correction data) of the correction voltage applied to each signal electrode for each column. The sum of the application time of the correction voltage applied to each signal electrode based on the pulse interval of each shift clock signal SLP decreases from the 2400th column to the 1st column. Since the sum of the application time based on the pulse interval of each shift clock signal SLP of the correction voltage for each column of each signal electrode is proportional to the total of the application time of the correction voltage for each signal electrode, during the next display period, In each scanning electrode, the voltage drop is corrected as the distance from the scanning side driving circuit 3 increases, and the luminance of the liquid crystal layer during the display period is corrected so as to become brighter from the first column to the 2400th column of the signal electrode. become.

[0042]

[Table 3] FIG. 6 shows the luminance of the liquid crystal layer corresponding to the first to 2400th columns of the signal electrode not particularly corrected when a voltage drop occurs in each scanning electrode during a display period in which an image is displayed. It is a graph which shows distribution. A gradation phenomenon occurs in which the luminance of the liquid crystal layer decreases from the first column to the 2400th column of the signal electrode.

In the case of the display screen in which the gradation phenomenon occurs in FIG. 6, in such a case, as shown in FIG. 4, the liquid crystal layer portions corresponding to the signal electrodes in the first to 2400 columns are displayed. If the luminance is corrected so as to increase sequentially, a uniform luminance distribution of the liquid crystal layer can be realized in the first to 2400th columns of the signal electrodes as shown in FIG.

Further, in the above embodiment, as the signal side driving circuit 2 with the serial mode, the voltage selected to be applied to the signal electrode in the serial mode is selected by the selection voltage V2 or V4 (either depending on the AC signal FR). Is determined) and the non-selection voltage V3 can be output by the shift data signal SYD, so that the power supply switching circuit for the correction voltage becomes unnecessary, and the circuit scale is reduced. Can be reduced and cost can be reduced.

It is to be noted that a general signal-side drive circuit in which the selection voltages V2 and V4 are switched by the shift data signal SYD without using such a signal-side drive circuit with a serial mode as the signal-side drive circuit 2 with a serial mode. Is used, in the power supply circuit section that outputs the selection voltage to the signal side driving circuit, the selection voltage V2 is used during the non-display period.
And V4 may be switched and output so as to be the non-selection voltage V3.

[0046]

According to the liquid crystal display device of the present invention, in the non-display period, the correction voltage is applied to each signal electrode which intersects one scanning electrode in order from one end to the other end. Are successively applied so as to be longer, so that it is possible to suppress the occurrence of the gradation phenomenon of the displayed image by a low-cost and small-sized circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a non-display period of the liquid crystal display device according to the embodiment of the present invention.

FIG. 3 is a timing chart showing a correction voltage application state during a non-display period of the liquid crystal display device according to the embodiment of the present invention.

FIG. 4 is a graph showing the relationship between the sum of the application time of the correction voltage to each signal electrode and the luminance of the liquid crystal layer.

FIG. 5 is a graph showing a luminance distribution of a liquid crystal layer when correction is performed on each signal electrode of the liquid crystal display device according to the embodiment of the present invention.

FIG. 6 is a graph showing a luminance distribution of a liquid crystal layer on each signal electrode of a conventional liquid crystal display device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 liquid crystal panel 2 signal-side drive circuit with serial mode 3 scan-side drive circuit 4 control unit 5 power supply circuit 6 line counter 7 gradation control signal generation circuit 8 correction data ROM 10 gradation correction circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623Y 642 642A F-term (Reference) 2H093 NA07 NA43 NANB23 NC11 NC21 NC27 NC28 NC49 NC65 ND05 ND09 ND15 5C006 AF13 AF46 AF51 AF73 BB12 BC03 BC12 BF03 BF08 FA18 FA22 FA37 5C080 AA10 BB05 DD05 EE28 FF12 JJ02 JJ04 JJ05

Claims (5)

[Claims] 1. A plurality of scanning electrodes to which a scanning voltage is applied, and a plurality of signal electrodes to which a scanning voltage is applied, and a plurality of signal electrodes to which a signal voltage is applied, respectively, are arranged with a liquid crystal layer interposed therebetween so as to be orthogonal to each scanning electrode. A liquid crystal display device having a scanning side driving circuit for applying a voltage to each scanning electrode, and a signal side driving circuit for applying a voltage to each signal electrode, wherein during a non-display period, from one end of each scanning electrode A liquid crystal display device, wherein a correction voltage is applied to each signal electrode, which intersects in order toward the other end, such that the application time of each signal electrode becomes longer sequentially. 2. The liquid crystal display device according to claim 1, wherein the increasing rate of the application time decreases as the application time of the correction voltage to each signal electrode increases. 3. The liquid crystal display device according to claim 1, wherein the rate of increase in the application time of the correction voltage to each of the signal electrodes is constant. 4. The liquid crystal display device according to claim 1, wherein the correction voltage is applied to each of a predetermined number of signal electrodes set in advance, and the number of signal electrodes to which the correction voltage is applied can be changed. 5. The liquid crystal display device according to claim 1, wherein the signal side driving circuit can output a selection voltage and a non-selection voltage according to shift data.