JP2002176144A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the whole semiconductor integrated circuit is miniaturized by arranging a capacitor effectively and the degree of freedom in circuit design is improved, and its manufacturing method. SOLUTION: This semiconductor device is provided with a first wiring layer positioned on a semiconductor substrate 10, a second wiring layer which is positioned on the same side as the first wiring layer and isolated from the first wiring layer, and a capacitor 1 arranged between a first wiring 2 belonging to the first wiring layer and a second wiring 3 belonging to the second wiring layer. The capacitor 1 is arranged in a crossing part of the first wiring and the second wiring, viewed from a plane, and has a dielectrics film 7 whose one surface is in contact with the first wiring 2 and the other surface is in contact with the second wiring 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, to a semiconductor integrated circuit, in which a miniaturized capacitor is formed between multi-layer wirings, and the degree of freedom of layout in circuit design is improved. The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which improve the quality and simplify the manufacturing process.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit using silicon,
Since it is easy to use a silicon compound, a capacitor provided in an integrated circuit has a structure in which polysilicon is used as an electrode, and a SiN film is used as a dielectric film (insulating film) between the electrodes. With such a capacitor,
A capacitor having a predetermined capacity could be formed with high reproducibility.

On the other hand, BST (Ba _x
A GaAs RF IC using a high dielectric substance such as Sr _1-x TiO ₃ ) has been proposed (IEICE Technical Report ED99-133, SDM99-107, ICD99-11).
5, p125: Daisuke Ueda) On-chip capacitors,
This has made it possible to reduce the power consumption and size of high-frequency wireless devices such as portable information terminals.

[0004]

The above-described conventional SiN
However, the capacitor using such a capacitor has a large capacitor area, restricting the degree of freedom in circuit layout in an integrated circuit, and has not been able to meet the demand for miniaturization and improvement in the degree of integration. FIG. 16 is a plan view showing a capacitor formed between a power supply line and a ground line of the semiconductor device. FIG. 17 is a sectional view taken along line XVII-XVII. Referring to FIGS. 16 and 17, a resistor 105 is connected to one terminal of a transistor 104 formed on a semiconductor substrate (not shown) via a wiring 106, and a power supply line 103 is connected to the resistor. Are connected by the wiring 106. The ground line 102 is connected to the other terminal side of the transistor 104 via a wiring 106. The capacitor 101 is formed on the isolation oxide film 111 on the semiconductor substrate 110. Power line 103
And ground line 102 are formed between interlayer insulating films 114 formed on the isolation oxide film. Capacitor 101 is connected to power supply line 103 and ground line 102 via electrodes 120 and 130. I have. Dielectric 107 constituting capacitor 101 is made of, for example, SiN, and has an electrode 130 connected to power supply line 103.
Each of the electrodes 120 connected to the ground line 102 uses an electrode made of polysilicon. An insulating film 115 is further coated on the upper electrode 130, and the height of the upper surface of the interlayer insulating film 114 is made uniform. Therefore, the conventional capacitor 101 is formed in a gap between the wirings when viewed in plan. When the capacitor 101 having a large occupied area is formed as described above, this portion is widely occupied by the capacitor, and the degree of freedom in layout in circuit design is significantly limited.
In addition, the formation of the capacitor 101 requires a very large number of steps, leading to an increase in the cost of the semiconductor integrated circuit.

In order to solve this problem, the above-mentioned BST
It is conceivable to reduce the size of the capacitor by using a high dielectric substance such as. However, even if a capacitor using a high dielectric material such as BST is manufactured, the reduction in the volume of the capacitor itself is not so large. If the miniaturized capacitor is used in the same arrangement as in the related art, the degree of freedom in circuit design does not increase so much. That is, unless an effective arrangement of the miniaturized capacitors is found and the miniaturization of the entire semiconductor device and the improvement of the degree of integration are not realized, the effect of the miniaturization of the capacitors alone will be limited. For this reason, how a capacitor using a high dielectric substance is used in a semiconductor integrated circuit can reduce the size and integration of the entire semiconductor device most effectively, thereby improving the degree of freedom in designing an integrated circuit. Or
Development continued. Naturally, in such a method of manufacturing a semiconductor device, it is desirable that the manufacturing process be simplified as compared with the conventional method.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which the size of the entire semiconductor integrated circuit is reduced and the degree of integration is improved by effectively arranging the miniaturized capacitors, and the degree of freedom in circuit design is improved. It is to provide a method.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate, a first wiring layer located on the semiconductor substrate, a second wiring layer located on the semiconductor substrate at a distance from the semiconductor substrate more than the first wiring layer, and a first wiring layer And a capacitor disposed between the first wiring belonging to the second wiring layer and the second wiring belonging to the second wiring layer, and the capacitor is provided at the intersection of the first wiring and the second wiring in plan view. And one side thereof is in contact with the first wiring, and
There is a dielectric film in which the surface on the other side is in contact with the wiring (claim 1).

In the semiconductor device of the present invention, the first wiring and the second wiring are arranged so as to be in contact with the dielectric film so as to sandwich the dielectric film, and each wiring also serves as an electrode of the capacitor. For this reason, it is not necessary to arrange the capacitors freely between the multi-layer wirings and secure a special space for forming the capacitors. As a result, a sufficient space can be provided, and the degree of freedom in circuit layout can be increased. Further, since the dielectric film can be formed directly on the first wiring, the number of steps for forming the capacitor can be greatly reduced as compared with the related art. In the above configuration, when the dielectric film is formed, for example, at the bottom of the hole,
It goes without saying that the second wiring includes a portion filling this hole.

The phrase "located above" includes both a case where it is located above and in contact with it and a case where it is located above with another object interposed therebetween. Further, when the dielectric film is a bent continuous film having a side wall portion, the side surface portion is included in the one side surface as long as the dielectric film is continuous with the “one side surface” of the film. The dielectric film may be a single layer made of a single material or a multi-layer in which a plurality of layers of different materials are integrated.

In the semiconductor device of the present invention, it is desirable that the dielectric film of the capacitor is substantially included in the intersection of the capacitors when viewed in plan (claim 2).

According to the above configuration, since the capacitors can be arranged in the wiring with a margin, the circuit layout can be simplified and the degree of freedom of the circuit layout can be further improved. Note that being substantially included means that a portion of about a margin may protrude. For example, when the dielectric film is formed in contact with the first wiring at the bottom of the hole formed in the interlayer insulating film, the dielectric film is formed along the edge of the opening of the hole on the upper surface of the interlayer insulating film from the side wall of the hole. Thus, the extent of protruding from the intersection falls within the scope of the present invention. In the above-described semiconductor device of the present invention, the width of the dielectric film in the width direction of the second wiring may extend beyond the width of the second wiring in plan view. That is,
Even if the dielectric film of the capacitor is not entirely covered with the second wiring, no problem occurs because the dielectric film is an insulator. However, if it is not covered by the second wiring,
For example, a hole formed in the insulating layer is left without being filled by the second wiring, and is filled when a later upper insulating layer is formed.
Furthermore, a capacitor whose dielectric film is not covered with the second wiring does not use the entire formed dielectric film as a capacitor, and can be said to be a capacitor having a useless portion. Since this is not preferable from the viewpoint of preventing the occurrence of unintended parasitic capacitors,
Should be kept to a minimum.

In addition, if only the first wiring and the second wiring can be prevented from coming into contact with each other and causing a short circuit, the dielectric film may be an insulating material and thus may protrude from the first wiring.

In the above-described semiconductor device of the present invention, in a predetermined case, the first wiring and the second wiring are the same as the first wiring layer and the second wiring layer to which they belong, except for the portion in contact with the dielectric film. And it is desirable not to have a detour (claim 3).

According to this structure, the capacitor is formed between the multi-layer wirings by a very simple method, so that the degree of freedom of the circuit layout can be improved and the size can be reduced.
By employing a structure that does not use a bypass, the manufacture of a semiconductor integrated circuit including a capacitor is greatly simplified, and a significant reduction in the number of manufacturing steps can be realized.

Note that the bypass wiring is a wiring that extends from a dielectric film of a capacitor in a direction perpendicular to the dielectric film and does not reach the wiring layer to which the wiring belongs at the shortest distance. A wiring that reaches a wiring layer to which the wiring belongs via a layer.

In the semiconductor device of the present invention, at least one of the first wiring and the second wiring is the same as the first wiring layer and the second wiring layer to which they belong, except for the portion in contact with the dielectric film. It may be desirable to have a part that does not belong to a layer and to have a detour (claim 4).

With the above configuration, it is possible to further improve the flexibility of circuit design and meet the demands of semiconductor devices for a wider range of applications.

In the semiconductor device of the present invention, for example, a plurality of capacitors can be arranged in parallel between the first wiring and the second wiring (claim 5).

According to the above configuration, a plurality of capacitors are provided.
The capacitance can be adjusted with high accuracy by connecting in parallel.

In the above semiconductor device of the present invention, the first wiring is provided in contact with the first insulating layer, and the second wiring is provided on the second insulating layer located farther from the semiconductor substrate than the first insulating layer. It is desirable to have a portion provided in contact with the layer and filling at least a hole formed in the second insulating layer (claim 6).

With the above structure, a capacitor can be provided between any wiring layers, and the space for the capacitor can be greatly reduced. In addition, the dielectric film of the capacitor needs to be formed, for example, over all the holes formed in the insulating layer of the first wiring so that the first wiring and the second wiring are not short-circuited. In order to reliably prevent the short circuit, the dielectric film is preferably provided on the side wall of the hole and also on the upper surface of the insulating layer at the edge of the hole. The at least one insulating layer serves as a base for the above-described short-circuit prevention structure.

In the semiconductor device of the present invention, it is preferable that the dielectric film has a portion covering the side wall of the hole formed in the insulating layer and the edge of the opening of the hole.

According to the above configuration, a short circuit between the first wiring and the second wiring can be more reliably prevented by the dielectric film. The portion of the dielectric film protruding from each wiring corresponds to, for example, a portion covering the edge of the opening.

In the semiconductor device of the present invention, it is preferable that the dielectric film includes a high dielectric film having a relative dielectric constant of 30 or more.

BST (Ba _x Sr _{1 -x} TiO ₃ ), ST
By using a high dielectric film such as O (SrTiO ₃ ) or Ta ₂ O _{5 having} a relative dielectric constant of 30 or more, the size of the capacitor can be reduced. By using miniaturized capacitors including the dielectric having a relative dielectric constant of 30 or less in the above arrangement, the degree of freedom in design layout can be increased, and the number of steps in the manufacturing process can be reduced. it can. In addition, by increasing the capacitance of the capacitor by using the dielectric, the impedance of the power supply line can be reduced in the bypass capacitor of the high-frequency circuit to reduce noise.

In the semiconductor device of the present invention, it is preferable that the first wiring and the second wiring are formed of a metal film.

By using the metal film of the wiring layer also for the electrodes of the capacitor, it is possible to contribute to the simplification of the production of the capacitor and the miniaturization of the capacitor, to create a margin of circuit space, and to improve the degree of freedom of the circuit layout. .

In the semiconductor device of the present invention, for example,
One of the first wiring and the second wiring is a power supply line, the other is a ground line, and the capacitor can be arranged as a bypass capacitor.

According to the above configuration, a miniaturized capacitor can be easily formed between the power supply line and the ground line, and a margin of circuit space can be created. In addition, by using a dielectric material having a high relative permittivity such as BST and increasing the capacitance, it is possible to sufficiently lower the impedance in the high-frequency circuit and reduce noise and the like.

In the semiconductor device of the present invention, one of the first wiring and the second wiring is electrically connected to one end of the resistor, and the other is connected to the first wiring and the second wiring. A capacitor different from the second wiring is electrically connected to the other end of the resistor, and the capacitor including the dielectric film and the resistor form a filter arranged in parallel with the different wiring. It is desirable (claim 11).

Since the area occupied by the filter is determined by the area of the resistor in a plan view, the size of the filter can be reduced as compared with the conventional filter which is determined by the area occupied by the capacitor.

In the semiconductor device of the present invention, more preferably, the resistor is provided at a position closer to the semiconductor substrate than the first wiring, and a lower portion of the first wiring is electrically connected to one end of the resistor. The second wiring is electrically connected to the other end of the resistor by a wiring different from the first wiring and the second wiring.

According to this configuration, the resistor can be provided at a position closer to the semiconductor substrate than the capacitor, so that a miniaturized filter can be manufactured more easily.

In the semiconductor device of the present invention, for example,
The first wiring is a terminal portion of a first circuit block formed on the semiconductor substrate, and the second wiring is a second circuit connected to the first circuit block formed on the semiconductor substrate. The capacitor, which is a terminal portion of the circuit block and includes a dielectric film, may be a capacitor for matching the impedance between the first circuit block and the second circuit block.

According to this configuration, no special wiring is required in the manufacture of the impedance matching section between the circuit blocks, so that the parasitic inductance can be eliminated. Further, the number of manufacturing steps for impedance matching of the interstage connection can be significantly reduced. Note that the elements constituting the circuit block may be transistors, resistors (R), capacitors (C), or coils (L: inductance).

In the semiconductor device of the present invention, for example,
The first circuit block is a first transistor, and
The wiring may be conductive to the drain of the first transistor, the second circuit block may be the second transistor, and the second wiring may be conductive to the gate of the second transistor.

With the above configuration, the interstage connection between the transistors can be formed very simply after impedance matching is achieved.

According to the method of manufacturing a semiconductor device of the present invention, there is provided a first interlayer insulating film forming step of forming a first interlayer insulating film on a semiconductor substrate, and a circuit in contact with the first interlayer insulating film. A first wiring layer forming step of forming a first wiring layer forming wiring, and a second interlayer insulating film forming a second interlayer insulating film on the first interlayer insulating film and the first wiring layer A film forming step. Further, this manufacturing method includes a step of forming a hole in the second interlayer insulating film so as to reach the first wiring belonging to the first wiring layer, and a step of forming a first portion of a portion exposed at the bottom of the hole. Forming a dielectric film so as to be in contact with the entire surface of the wiring, forming a second wiring layer in contact with the second interlayer insulating film, and forming a second wiring belonging to the second wiring layer And a second wiring layer forming step of arranging the second wiring layer in contact with the dielectric film.

With this configuration, a miniaturized capacitor can be easily formed freely between the multi-layer wirings with a small number of steps. For this reason, it becomes possible to manufacture a semiconductor device with an increased degree of freedom in wiring design at low cost.

The above-mentioned dielectric film may be a single layer composed of a single material or a multilayer in which a plurality of layers of different materials are integrated. In this case, it is desirable that the first wiring and the second wiring have at least some overlapping portions when viewed in plan.

In the method of manufacturing a semiconductor device according to the present invention,
The hole formed in the opening step is the first hole in a plan view.
It is desirable to have a size substantially included in the region of the first wiring in the wiring layer (claim 16).

According to the above configuration, the capacitor can be formed with more room between the multi-layer wirings, and the degree of freedom in layout can be improved. Note that being substantially included means that a margin may be protruded.

In the method of manufacturing a semiconductor device according to the present invention,
The dielectric film formed in the dielectric film forming step has a size and an arrangement not only in contact with the entire surface of the first wiring in the portion exposed at the bottom of the hole but also covering the side wall of the hole and the edge of the opening. It is desirable (claim 17).

With the above-described dielectric film, a short circuit between the first wiring and the second wiring can be reliably prevented, and a capacitor having a cross-sectional area of a hole can be formed.

In the method of manufacturing a semiconductor device according to the present invention,
In the dielectric film forming step, it is desirable to use a chemical vapor deposition (CVD) method for forming the dielectric film (claim 18).

The above-mentioned dielectric film is desirably manufactured by a method that can be formed on the bottom, the side wall, and the edge of the opening of the hole. That is, a manufacturing method is used in which component atoms, ions, molecules, and the like, which constitute the dielectric film, fly in a direction, and the dielectric film is not formed in the shadow of the unevenness. The CVD method is a desirable manufacturing method because the above atoms, ions, molecules, and the like do not have a large directionality. For example, the MOCVD (Metal Organic CVD) method is suitable for the above purpose because a dielectric film can be grown from a gas phase in contact with each of the above portions. The MOCVD method referred to here is MOVPE (Metal Organic V
apor Phase Epitaxy). Depending on the type of the dielectric film, a plasma CVD method or the like is also an object.

In the method of manufacturing a semiconductor device according to the present invention,
The second wiring formed in the second wiring layer forming step includes:
It is desirable to have a portion that fills the hole.
9).

According to this configuration, the upper electrode of the capacitor and the second wiring layer can be manufactured at the same opportunity, and the number of steps in manufacturing a semiconductor device can be reduced.

In the method of manufacturing a semiconductor device according to the present invention, in the first wiring layer forming step and the second wiring layer forming step, one of a vapor phase growth method (CVD method) and a sputtering method is used. It is preferable that the first wiring and the second wiring are formed by using (2).

The first and second wiring layers are formed of a metal film such as an Al film. For this reason, since the adjustment of the target is easy, the wiring layer can be efficiently formed by forming the wiring layer by sputtering at a high deposition rate. However, the sputtering method cannot easily form a film on a shadowed portion when viewed from the target. When the defect generated in this manner becomes a problem, it is possible to form a film to a corner of a hole formed in the interlayer insulating film by using a vapor deposition method (CVD method). Note that the first wiring layer and the second wiring layer do not need to be formed by the same method, and a method suitable for the first wiring and the second wiring also serving as electrodes of the capacitor can be employed.

[0051]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a sectional view taken along line II-II of the semiconductor device of FIG. FIG.
Is a circuit diagram of the semiconductor device. 1 to 3, a transistor 4 including a source / drain diffusion layer 12 and a gate electrode 13 is arranged in an active region sandwiched between isolation oxide films 11 on the surface of a silicon substrate 10, and a first interlayer insulating film is formed. The film 14 covers the transistor. A hole for forming a metal wiring connected to each part of the transistor is formed in the first interlayer insulating film 14, and the metal wiring 6 is arranged so as to fill the hole. The ground line 2 made of a metal film is disposed on the same layer as the metal wiring 6 on the first interlayer insulating film 14, and further covers the metal wiring layer 6 and the ground line 2 forming the first wiring layer. Thus, the second interlayer insulating film 15 is arranged. A hole reaching the upper surface of the ground line 2 is opened in the second interlayer insulating film 15 above the ground line 2, and a portion of the metal film which is the first wiring exposed at the bottom of the hole and a side surface of the hole The dielectric film 7 is arranged so as to be in contact with. The dielectric film 7 shown in FIG.
The side surface of the hole and the edge of the opening of the hole are covered. Power supply line 3 made of a metal film is arranged on second interlayer insulating film 15 so as to fill the hole covered with dielectric film 7.

A metal film such as aluminum can be used for the first wiring and the second wiring, and a dielectric having a high relative dielectric constant such as BST can be used for the dielectric film.

The capacitor 1 in the semiconductor device is formed on the first wiring 2 in the first wiring layer formed on the first interlayer insulating film 14 and on the second interlayer insulating film 15. It is formed between the second wiring 3 and the second wiring 3 in the second wiring layer. As shown in FIG. 1, a bypass capacitor is provided at the intersection of a ground line 2 made of a metal film and a power supply line 3 made of a metal film, as shown in FIG. Is arranged as. That is, since the capacitor is formed between the multilayer wirings, a very small occupied space is required. For this reason, the capacitor does not need to occupy a large space in the three-dimensionally formed semiconductor integrated circuit, so that the wiring layout is facilitated and the semiconductor chip can be downsized. In addition, by using a dielectric material having a high relative permittivity such as BST for the dielectric film 7 and increasing the capacitance of the capacitor, when used as a bypass capacitor of a high-frequency circuit, it is possible to lower the impedance and reduce noise and the like. Become. Further, the bypass capacitor can be manufactured by a manufacturing method which is significantly simplified as compared with a conventional manufacturing method.

(Embodiment 2) In Embodiment 2 of the present invention, a method of manufacturing the semiconductor device shown in Embodiment 1 will be described. FIG. 4 shows a CMOS (Complem) on a silicon substrate.
FIG. 4 is a cross-sectional view of a stage in which first wiring layers 6 and 2 made of a metal film are formed using a normal CMOS process used when forming an entary metal oxide semiconductor (entry metal oxide semiconductor). The ground line (first wiring) 2 in the first wiring layer is
First interlayer insulating film 14 together with other wiring 6 in the wiring layer
Formed in contact with Next, the second interlayer insulating film 15
Is deposited, and a hole (hole) 20 smaller than the line width is opened on the ground line 2 of the second interlayer insulating film (FIG. 5). Next, a dielectric BS which is an insulating film of the capacitor
A T (Ba _x Sr _1-x TiO ₃ ) film 7 is deposited by MOCVD at a deposition temperature of 450 ° C. and patterned so as to have a margin with respect to the opening of the hole 20 (FIG. 6). . Next, a second wiring layer made of a metal film is formed by a sputtering method, and is patterned so as to cover the dielectric film 7 (FIG. 7).

As described above, the relative dielectric constant of the formed BST film is about 80 to 200. BST with relative dielectric constant of 200
When the film is formed with a thickness of 100 nm, the area is 100 μm
^{When two} capacitors are formed, the capacitance is about 1.7 pF
Becomes For example, RF-CM driven at 2.5 GHz
The capacity required for the bypass capacitor of the power supply line in the OS circuit is 100 pF. In order to obtain the required capacitance, the above-mentioned capacitors may be arranged in a line of 60 pieces in a wiring width of 10.5 μm. A capacitor arranged between such multilayer wirings occupies a very small volume in a three-dimensionally formed semiconductor integrated circuit,
To that extent, the degree of freedom in circuit layout can be increased. In addition, capacitor formation is simplified, and the number of steps can be reduced.

(Embodiment 3) In Embodiment 3 of the present invention, the structure of a portion including a capacitor of a semiconductor device is the same as that of Embodiments 1 and 2, but a hole in an interlayer insulating film in which the capacitor is arranged is provided. The feature is that the formation of is efficiently performed. That is, the opening in the second interlayer insulating film for disposing the capacitor is made at the same opportunity as the opening of the via hole for making contact with the wiring formed under the second interlayer insulating film. In the second embodiment of the present invention, the opening in the second interlayer insulating film for forming the capacitor and the opening in the via hole are performed at different occasions. FIG. 8 shows that the ground line 2, the transistor electrode wiring 6, and the other wiring 8 in the same layer as these wirings are the first wiring.
FIG. 3 is a cross-sectional view showing a state formed on an interlayer insulating film 14 of FIG. The wiring of the other parts except the other wiring 8 has the same configuration as that of FIG.

Next, a second interlayer insulating film 15 is deposited from the state shown in FIG. 8, and a hole 20 is formed on the ground line 2 of the second interlayer insulating film 15 and a via hole is formed on the wiring 8. A hole 21 is opened (FIG. 9). Next, a dielectric film 7 constituting the capacitor 1 is deposited by the CVD method, and then the dielectric film 7 is patterned to form the hole 2
0 has a certain margin at the opening (see FIG. 1).
0). Next, a second wiring layer made of a metal film is formed by a sputtering method, and is patterned so as to cover the dielectric film 7 and the via hole 21 (FIG. 11).

By using the above-described method of manufacturing a semiconductor device, formation of a capacitor arranged between multilayer wirings of the semiconductor device can be further simplified, and the number of steps can be further reduced.

(Embodiment 4) In Embodiment 4 of the present invention, a case where a dielectric material having a high relative dielectric constant is used for a dielectric film constituting a capacitor and a case where a material having a normal relative dielectric constant is used are used. Two cases will be described. That is, STO or Ta ₂ O ₅ may be used instead of BST, or a dielectric (insulating film) such as SiO ₂ or SiN may be used for the dielectric film. In addition, the first and second wiring layers made of a metal film can be formed not by a sputtering method but by a CVD method. A layer can be formed.

According to the above configuration, it is possible to form a dielectric film constituting a small capacitor having a capacity suitable for the semiconductor device. In addition, the formation of a wiring layer made of a metal film requires C
By using the VD method, it is possible to completely cover the dielectric film with the metal film, including the bottom corner of the hole formed in the interlayer insulating film.

(Fifth Embodiment) A semiconductor device according to a fifth embodiment of the present invention is characterized in that a capacitor is arranged in a filter circuit of the semiconductor device. On the other hand, in the first to fourth embodiments, the capacitor is used as a bypass capacitor of the power supply line. FIG. 12 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention.
FIG. 13 is an equivalent circuit diagram of the filter unit in which the capacitor and the resistor arranged in FIG. 12 are arranged in parallel. In FIG. 12, an isolation oxide film 11 is formed on the surface of a semiconductor substrate 10, and a resistor made of a polysilicon layer 24 is formed on and in contact with the isolation oxide film 11. The first wiring 2 formed on and in contact with the first interlayer insulating film 14 is in contact with one end of the polysilicon layer 24 at a lower portion filling the hole. A second interlayer insulating film is arranged in contact with first wiring 2 and first interlayer insulating film 14, and dielectric film 7 is deposited in a hole reaching first wiring 2. The second wiring 3 is formed on the dielectric film 7. The capacitor 1 includes a dielectric film 7 and first and second wirings made of a metal film also serving as electrodes sandwiching the dielectric film 7. Also, the second wiring 3
Are connected to the other end of the polysilicon layer 24 by wirings 23 and 22 different from the first and second wirings. The arrangement of the capacitor 1 and the resistor 24 is determined by the wirings 2, 22, 2
3 and a capacitor and a resistor are arranged in parallel.

As described above, by forming the capacitors constituting the filter circuit only between the multilayer wirings,
Since the capacitor is formed between the multi-layer wirings, the circuit space can be largely saved, and the degree of freedom in circuit design layout can be increased. Further, the number of steps for manufacturing the filter circuit can be significantly reduced.

(Embodiment 6) Embodiment 6 of the present invention is characterized in that a capacitor is used for impedance matching between circuit blocks. FIG. 14 is a cross-sectional view showing a semiconductor device according to the sixth embodiment having a capacitor for impedance matching between circuit blocks. Also,
FIG. 15 is a diagram showing the circuit configuration. In FIG. 14, two circuit blocks are both transistors 31,
32. The first transistor 31
It has a source / drain diffusion layer 12a, a gate electrode 13a, and a gate wiring 6a. The second transistor 32 includes a source / drain diffusion layer 12b, a gate electrode 1
3b and a gate wiring 6b. Transistor 31
The wiring 2a from the source / drain 12a corresponds to the first wiring in the capacitor, and the dielectric film 7 is formed thereon. Conductive layer 3 is arranged in contact with dielectric film 7, and conductive layer 3 is electrically connected to gate line 6b of transistor 32. In the above configuration, the transistor (amplifier) 31 and the transistor (amplifier) 32 are connected between the stages, and the capacitor (C) 1 for impedance matching is arranged at the connection between the stages.

As described above, by forming the impedance matching capacitor at the inter-stage connection between the circuit blocks only between the multilayer wirings, the circuit space can be largely saved, and the layout of the circuit design can be reduced. The degree of freedom can be increased. Further, the number of manufacturing steps of the inter-stage connection portion can be greatly reduced.

Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Not limited. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

[0067]

By using the semiconductor device and the method of manufacturing the same according to the present invention, a capacitor can be limitedly arranged between multilayer wirings. Therefore, the degree of freedom of the circuit layout of the three-dimensionally formed semiconductor integrated circuit can be greatly improved. In addition, by applying the capacitor in the semiconductor device to the bypass capacitor of the power supply line, the impedance of the power supply line can be reduced, and the influence of external noise and the like can be suppressed. Further, by using the capacitor of the semiconductor device, the number of steps in the manufacturing process can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II of the semiconductor device of FIG.

FIG. 3 is an equivalent circuit diagram of the semiconductor according to the first embodiment of the present invention.

FIG. 4 is a diagram for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention, which is a cross-sectional view at a stage where a first wiring layer made of a metal film is formed.

FIG. 5 is a cross-sectional view showing a state where a second interlayer insulating film is formed following the state of FIG. 4 and holes are formed in the second interlayer insulating film on the first wiring.

FIG. 6 is a cross-sectional view showing a state where a dielectric film forming a capacitor is formed in the hole, following the state of FIG. 5;

FIG. 7 is a cross-sectional view showing a state where a second wiring made of a metal film is formed on the hole covered with the dielectric film and a second interlayer insulating film, following the state of FIG.

FIG. 8 is a diagram for illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention, which is a cross-sectional view at a stage where a first wiring layer including another wiring portion made of a metal film is formed. is there.

FIG. 9 shows another wiring portion and a first wiring portion following the state shown in FIG. 8;
FIG. 10 is a cross-sectional view of a stage where holes are opened in a second interlayer insulating film above the wiring layer of FIG.

FIG. 10 is a cross-sectional view showing a state where a dielectric film covering only holes on the first wiring layer is formed following the state of FIG. 9;

FIG. 11 is a cross-sectional view showing a state where a second wiring made of a metal film is formed following the state shown in FIG. 10;

FIG. 12 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

13 is an equivalent circuit diagram of a filter unit of the semiconductor device shown in FIG.

FIG. 14 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

15 is an equivalent circuit diagram of an interstage connection portion of the semiconductor device shown in FIG.

FIG. 16 is a schematic plan view showing a semiconductor device having a conventional arrangement of capacitors.

17 is a sectional view taken along line XVII-XVII in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Capacitor, 2, 2a 1st wiring (ground line), 3rd wiring (power supply line), 4 transistor, 5 resistance, 6 wiring, 6a, 6b Gate wiring, 7
Dielectric film of capacitor, 8 wiring on second interlayer insulating film, 10 silicon (semiconductor) substrate, 11 isolation oxide film, 12, 12a, 12b source / drain diffusion layer,
13, 13a, 13b Gate electrode, 14 First interlayer insulating film, 15 Second interlayer insulating film, 20 Hole on first wiring, 21 Via hole, 22, 23 Wiring, 24
Polysilicon layer (resistor), 31, 32 Transistor.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akihiko Furukawa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5F033 HH08 JJ01 JJ08 KK01 KK08 PP06 PP15 QQ09 QQ37 RR01 RR03 RR04 RR06 SS11 VV09 VV10 XX00 XX33 5F038 AC02 AC15 AC18 AR09 BH19 CD02 CD03 DF01 EZ14 EZ20

Claims (20)

[Claims] A first wiring layer located on the semiconductor substrate; and a second wiring located on the semiconductor substrate at a distance from the semiconductor substrate more than the first wiring layer. And a capacitor disposed between a first wiring belonging to the first wiring layer and a second wiring belonging to the second wiring layer. 1st wiring and 2nd
A semiconductor device having a dielectric film located at an intersection with a wiring, one surface of which is in contact with the first wiring, and the other surface of which is in contact with the second wiring. 2. The semiconductor device according to claim 1, wherein the dielectric film of said capacitor is substantially included in an intersection thereof when viewed in plan. 3. The first wiring and the second wiring, except for a portion in contact with the dielectric film, wherein the first wiring and the second wiring belong to the first wiring.
3. The semiconductor device according to claim 1, wherein the semiconductor device belongs to the same layer as the first wiring layer and the second wiring layer and has no detour. 4. A portion that does not belong to the same layer as the first wiring layer and the second wiring layer to which each of the first wiring and the second wiring belongs except for a portion in contact with the dielectric film. The semiconductor device according to claim 1, further comprising: a detour. 5. The capacitor according to claim 1, wherein a plurality of said capacitors are arranged in parallel between said first wiring and said second wiring.
5. The semiconductor device according to any one of 4. 6. The first wiring is provided in contact with a first insulating layer, and the second wiring is provided on a second insulating layer located farther from the semiconductor substrate than the first insulating layer. The semiconductor device according to any one of claims 1 to 5, further comprising a portion provided in contact with the upper portion and filling at least a hole formed in the second insulating layer. 7. The semiconductor device according to claim 6, wherein said dielectric film has a portion covering a side wall of a hole formed in said second insulating layer and an edge of an opening of said hole. 8. The semiconductor device according to claim 1, wherein said dielectric film includes a high dielectric film having a relative dielectric constant of 30 or more. 9. The semiconductor device according to claim 1, wherein said first wiring and said second wiring are formed of a metal film. 10. The device according to claim 1, wherein one of the first wiring and the second wiring is a power supply line, the other is a ground line, and the capacitor is arranged as a bypass capacitor. Semiconductor device. 11. A resistor having a resistor, and one end of the resistor,
One of the first wiring and the second wiring is electrically connected, and the other is electrically connected to the other end of the resistor by a wiring different from the first wiring and the second wiring, A capacitor including a dielectric film and the resistor,
10. The semiconductor device according to claim 1, wherein a filter arranged in parallel with said different wiring is formed. 12. The semiconductor device according to claim 1, further comprising: a resistor located closer to the semiconductor substrate than the first wiring, a lower portion of the first wiring being electrically connected to one end of the resistor, and the second wiring being connected to the second wiring. The semiconductor device according to claim 11, wherein the semiconductor device is electrically connected to the other end of the resistor by a wiring different from the first wiring and the second wiring. 13. The first wiring is a terminal portion of a first circuit block formed on the semiconductor substrate, and the second wiring is formed on the semiconductor substrate.
A terminal portion of a second circuit block connected to the first circuit block, wherein the capacitor including the dielectric film is connected to the first circuit block.
The semiconductor device according to claim 1, wherein the semiconductor device is a capacitor for matching impedance between the circuit block of (1) and the second circuit block. 14. The first circuit block is a first transistor, the first wiring is connected to a drain of the first transistor, and the second circuit block is a second transistor.
14. The semiconductor device according to claim 13, wherein said second wiring is electrically connected to a gate of said second transistor. 15. A first interlayer insulating film forming step of forming a first interlayer insulating film on a semiconductor substrate, and a first layer forming a circuit wiring in contact with the first interlayer insulating film. A first wiring layer forming step of forming a wiring layer; a second interlayer insulating film forming step of forming a second interlayer insulating film on the first interlayer insulating film and the first wiring layer; In order to reach the first wiring belonging to the first wiring layer,
An opening step of making a hole in the second interlayer insulating film; a dielectric film forming step of forming a dielectric film so as to be in contact with the entire surface of the first wiring at a portion exposed at the bottom of the hole; A second wiring layer forming step of forming a second wiring layer in contact with the second interlayer insulating film, and arranging a second wiring belonging to the second wiring layer so as to be in contact with the dielectric film; A method for manufacturing a semiconductor device, comprising: 16. The hole according to claim 15, wherein the hole formed in the opening step has a size substantially included in a region of the first wiring in the first wiring layer when viewed in plan. Of manufacturing a semiconductor device. 17. The dielectric film formed in the dielectric film forming step is not only in contact with the entire surface of the first wiring in a portion exposed at the bottom of the hole, but also in contact with the side wall of the hole and the edge of the opening. 15 or 1 having a size and an arrangement covering
7. The method for manufacturing a semiconductor device according to item 6. 18. The method according to claim 15, wherein in the step of forming the dielectric film, a vapor deposition method is used to form the dielectric film.
18. The method for manufacturing a semiconductor device according to any one of items 17. 19. The method of manufacturing a semiconductor device according to claim 15, wherein the second wiring formed in the second wiring layer forming step is formed so as to fill the hole. 20. The first wiring layer forming step and the second wiring layer forming step.
20. The semiconductor device according to claim 15, wherein in the wiring layer forming step, the first wiring and the second wiring are formed by using one of a vapor deposition method and a sputtering method. Manufacturing method.