JP2002176075A - Heat sink, manufacturing method thereof, semiconductor package and manufacturing method thereof - Google Patents
Heat sink, manufacturing method thereof, semiconductor package and manufacturing method thereofInfo
- Publication number
- JP2002176075A JP2002176075A JP2000375520A JP2000375520A JP2002176075A JP 2002176075 A JP2002176075 A JP 2002176075A JP 2000375520 A JP2000375520 A JP 2000375520A JP 2000375520 A JP2000375520 A JP 2000375520A JP 2002176075 A JP2002176075 A JP 2002176075A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor package
- substrate
- heat sink
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する利用分野】本発明は、半導体パッケージ
の半導体素子に近接して設けられ、当該半導体素子より
生じた熱を外部へ放散させる放熱板及びその製造方法並
びに放熱板を備えた半導体パッケージ及びその製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat sink provided near a semiconductor element of a semiconductor package for dissipating heat generated by the semiconductor element to the outside, a method of manufacturing the same, a semiconductor package having the heat sink, and a method of manufacturing the same. It relates to the manufacturing method.
【０００２】[0002]
【従来の技術】近年、システムＬＳＩ、ＭＣＭなどの半
導体装置には、種々の半導体パッケージが高集積化、高
密度実装化して基板実装されている。半導体パッケージ
には、例えばＢＧＡ（Ｂａｌｌ・Ｇｒｉｄ・Ａｒｒａ
ｙ）タイプのように表面実装するものや、ＣＳＰ（Ｃｈ
ｉｐ・Ｓｉｚｅ・Ｐａｃｋａｇｅ）タイプのようにベア
チップ実装するものなどがある。これらの半導体パッケ
ージのうち、高出力性能を有するＬＳＩやＭＰＵなどに
は、熱放散性の高い金属板（例えば銅、銅合金）よりな
る放熱板（ヒートシンク）を接着などにより取り付けら
れることが多い。2. Description of the Related Art In recent years, various semiconductor packages are mounted on a semiconductor device such as a system LSI and an MCM in a highly integrated and high-density package. The semiconductor package includes, for example, BGA (Ball, Grid, Arra).
y) type or surface-mounting type such as CSP (Ch
There is a type mounted on a bare chip such as an IP / Size / Package type. Of these semiconductor packages, a heat sink (heat sink) made of a metal plate having high heat dissipation (for example, copper or copper alloy) is often attached to an LSI or MPU having high output performance by bonding or the like.
【０００３】このように放熱板を取り付けた半導体パッ
ケージを基板実装する場合、当該実装位置や向きを視認
できるマーク（例えば１番ピンマーク）が必要となる。
外面に放熱板（ヒートシンク）が設けられた半導体パッ
ケージの場合には、該放熱板上の所定部位にマークを付
与することを要する。この放熱板にマークを付与するた
めの方法としては、従来プリント印刷、ザグリ加工など
が行われていた。[0003] When a semiconductor package to which a heat sink is attached is mounted on a substrate, a mark (for example, a first pin mark) that allows the mounting position and direction to be visually recognized is required.
In the case of a semiconductor package provided with a heat sink (heat sink) on the outer surface, it is necessary to add a mark to a predetermined portion on the heat sink. Conventionally, print printing, counterboring, and the like have been performed as a method for providing a mark on the heat sink.
【０００４】以下に半導体パッケージの具体例について
図４及び図５を参照して説明する。尚、ここでは、キャ
ビティ孔が形成されたプリント配線板（樹脂基板）５２
に、放熱板５３を貼り合わせてキャビティ凹部が形成さ
れたタイプの半導体パッケージ５１を用いて説明する。
キャビティ凹部の底部には半導体素子（ＩＣチップ）５
４が搭載されており、当該半導体素子５４のパッド部と
プリント配線板５２のパッド部とがワイヤボンディング
により電気的に接続されている。キャビティ凹部は封止
樹脂５５により封止されており、プリント配線板５２の
端子部にははんだボール５６が接合されてなる。A specific example of a semiconductor package will be described below with reference to FIGS. Here, a printed wiring board (resin substrate) 52 having a cavity hole formed therein is used here.
Next, a description will be given using a semiconductor package 51 of a type in which a cavity recess is formed by bonding a heat sink 53.
A semiconductor element (IC chip) 5 is provided at the bottom of the cavity concave portion.
4 are mounted, and the pad portion of the semiconductor element 54 and the pad portion of the printed wiring board 52 are electrically connected by wire bonding. The cavity recess is sealed with a sealing resin 55, and a solder ball 56 is joined to a terminal portion of the printed wiring board 52.
【０００５】図４は、放熱板５３の所定部位（例えば１
番ピン位置）に印刷マーク５７が形成されている。印刷
マーク５７は、インクの耐熱性が低いことから、最終工
程で１つずつ印刷される。図５は放熱板５３の所定部位
（例えば１番ピン位置）にザグリ加工を施してへこみマ
ーク５８が形成されている。へこみマーク５８の識別に
は５〜１０μｍ程度のへこみが必要となる。FIG. 4 shows a predetermined portion (for example, 1) of the heat sink 53.
A print mark 57 is formed at the (number pin position). The print marks 57 are printed one by one in the final step because the heat resistance of the ink is low. In FIG. 5, a dent mark 58 is formed by performing a counterboring process on a predetermined portion (for example, the position of the first pin) of the heat sink 53. In order to identify the dent mark 58, a dent of about 5 to 10 μm is required.
【０００６】[0006]
【発明が解決しようとする課題】図４に示す放熱板５３
に印刷マーク５７を印刷する場合には、半導体パッケー
ジ製造工程の最終工程において１つずつ印刷されるため
作業効率が低い上に、印刷設備を設ける必要があるため
製造コストも高くなる。また、パッケージ製造工程にお
いて印刷マーク５７が付与されていないため、パッケー
ジの向きが特定できないため不良品を発生させやすく、
歩留まりが低下する。図５に示す放熱板５３にへこみマ
ーク５８を形成する場合には、識別可能な大きさのへこ
みを形成するため、ＮＣドリルやエンドミルなどで放熱
板５３に加工を施すとしても、放熱板５３がプリント配
線板（樹脂基板）５２に実装状態では部分的な加圧加工
は困難であり、マトリクス状に形成された放熱板５３の
状態でザグリ加工を施す場合にも、パッケージサイズが
小さい場合には、識別できる大きさのへこみを形成し難
いという課題があった。また印刷マーク５７の厚さやへ
こみマーク５８を形成する際のザグリ加工により、放熱
板５３の高さがばらつき易いため、半導体パッケージを
基板実装する際に取扱い難く、実装位置精度や姿勢精度
にばらつきが生ずるおそれがあった。The heat sink 53 shown in FIG.
When the print marks 57 are printed in the final step of the semiconductor package manufacturing process, the print efficiency is low because the print marks 57 are printed one by one, and the manufacturing cost is also high because a printing facility must be provided. In addition, since the print mark 57 is not provided in the package manufacturing process, the orientation of the package cannot be specified, so that a defective product is easily generated,
Yield decreases. When the dent mark 58 is formed on the heat radiating plate 53 shown in FIG. 5, even if the heat radiating plate 53 is processed by an NC drill or an end mill to form a dent having a recognizable size, When the package is small, it is difficult to perform a partial pressurizing process when the package is mounted on the printed wiring board (resin substrate) 52. However, there is a problem that it is difficult to form a dent having a size that can be identified. In addition, the height of the heat sink 53 tends to fluctuate due to the counterbore processing when forming the thickness of the printing mark 57 and the dent mark 58, so that it is difficult to handle the semiconductor package when mounting it on a substrate, and the mounting position accuracy and posture accuracy vary. Was likely to occur.
【０００７】本発明の目的は、上記従来技術の課題を解
決し、耐熱性を有するマークを簡易かつ効率的に製造で
き、高さのばらつきも生じ難い放熱板及びその製造方法
を提供し、該放熱板を備えることにより、生産性を高
め、実装精度の高めた半導体パッケージ及びその製造方
法を提供することにある。An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a heat sink and a method of manufacturing the same, which can easily and efficiently manufacture a heat-resistant mark and hardly cause a variation in height. It is an object of the present invention to provide a semiconductor package having a heat sink, which has improved productivity and mounting accuracy, and a method of manufacturing the same.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するた
め、本発明は次の構成を備える。すなわち、半導体パッ
ケージの半導体素子に近接して設けられ、当該半導体素
子より生じた熱を外部へ放散させる放熱板においては、
銅又は銅合金よりなる金属板の所定部位に、半導体パッ
ケージを基板実装する際の指標となるマークが黒色酸化
処理法により形成されていることを特徴とする。具体的
には、金属板の所定部位に、金属酸化膜によるマークが
形成されており、該マークを除く部位は金属めっき皮膜
で覆われていることを特徴とする。To solve the above-mentioned problems, the present invention has the following arrangement. That is, in a radiator plate that is provided close to a semiconductor element of a semiconductor package and dissipates heat generated by the semiconductor element to the outside,
A mark serving as an index when a semiconductor package is mounted on a substrate is formed on a predetermined portion of a metal plate made of copper or a copper alloy by a black oxidation treatment method. Specifically, a mark made of a metal oxide film is formed on a predetermined portion of the metal plate, and a portion other than the mark is covered with a metal plating film.
【０００９】また、半導体パッケージの半導体素子に近
接して設けられ、当該半導体素子より生じた熱を外部へ
放散させる放熱板の製造方法においては、銅又は銅合金
よりなる金属板の一方の面に、所定部位にマスクを形成
する工程と、金属板のマスクで覆われた部位以外の露出
面を金属めっき皮膜で覆う工程と、金属板よりマスクを
剥離した後酸化処理液に浸漬させて、露出面上に金属酸
化膜によるマークを形成する工程とを含むことを特徴と
する。Further, in a method of manufacturing a heat sink provided near a semiconductor element of a semiconductor package and dissipating heat generated from the semiconductor element to the outside, the method of manufacturing a heat sink according to the present invention may be applied to one surface of a metal plate made of copper or a copper alloy. Forming a mask on a predetermined portion, covering the exposed surface of the metal plate other than the portion covered with the mask with a metal plating film, exposing the mask from the metal plate, immersing the mask in an oxidizing solution, Forming a mark with a metal oxide film on the surface.
【００１０】また、半導体パッケージにおいては、放熱
板が基板の一方の面に貼り合わされてキャビティ凹部が
形成されていることを特徴とする。また、他の半導体パ
ッケージにおいては、放熱板が、基板上にフリップチッ
プ接続された半導体素子及び該半導体素子の周囲に設け
られた補強材に貼り合わされていることを特徴とする。The semiconductor package is characterized in that a heat sink is bonded to one surface of the substrate to form a cavity recess. Further, another semiconductor package is characterized in that a heat sink is bonded to a semiconductor element which is flip-chip connected on a substrate and a reinforcing material provided around the semiconductor element.
【００１１】また、半導体パッケージの製造方法として
は、前述した製造方法により製造された放熱板を、基板
の一方の面に貼り合わせてキャビティ凹部を形成する工
程と、キャビティ凹部に前記半導体素子を搭載して該半
導体素子と前記基板とを電気的に接続する工程と、半導
体素子を収容するキャビティ凹部を樹脂封止する工程
と、基板の他方の面に端子を形成する工程とを含むこと
を特徴とする。また、他の半導体パッケージの製造方法
としては、基板の一方の面に半導体素子をフリップチッ
プ接続する工程と、フリップチップ接続された半導体素
子をアンダーフィルモールドする工程と、半導体素子の
周囲の基板上に補強材を設ける工程と、前述した製造方
法により製造された放熱板を、半導体素子及び補強材に
貼り合わせる工程と、基板の他方の面に端子を形成する
工程とを含むことを特徴とする。Further, as a method of manufacturing a semiconductor package, a heat sink produced by the above-described manufacturing method is bonded to one surface of a substrate to form a cavity, and the semiconductor element is mounted in the cavity. Electrically connecting the semiconductor element and the substrate, resin sealing a cavity recess accommodating the semiconductor element, and forming a terminal on the other surface of the substrate. And Another method of manufacturing a semiconductor package includes a step of flip-chip connecting a semiconductor element to one surface of a substrate, a step of underfill molding the flip-chip-connected semiconductor element, and a step of And a step of bonding a heat sink manufactured by the above-described manufacturing method to the semiconductor element and the reinforcing material, and a step of forming a terminal on the other surface of the substrate. .
【００１２】[0012]
【発明の実施の形態】以下、本発明の好適な実施の形態
について添付図面に基づいて詳細に説明する。図１
（ａ）（ｂ）及び 図２（ａ）（ｂ）は半導体パッケー
ジの上視図及び断面説明図、図３は放熱板の製造工程を
示す説明図である。先ず、半導体パッケージの一例につ
いて、図１及び図２を参照して説明する。図１（ａ）
（ｂ）に示す半導体パッケージ１は、放熱板２をキャビ
ティ孔が形成されたプリント配線板（樹脂基板）３の一
方の面に貼り合わせてキャビティ凹部４が形成されてい
る。このキャビティ凹部４の底部には半導体素子（ＩＣ
チップ）５が搭載されている。半導体素子５のパッド部
とプリント配線板３のパッド部とは、ワイヤボンディン
グにより電気的に接続されている。キャビティ凹部４
は、封止樹脂６により封止された後、基板端子部にはん
だボール７が接合されてなる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG.
2A and 2B are a top view and a sectional explanatory view of a semiconductor package, and FIG. 3 is an explanatory view showing a manufacturing process of a heat sink. First, an example of a semiconductor package will be described with reference to FIGS. FIG. 1 (a)
In the semiconductor package 1 shown in FIG. 2B, a cavity recess 4 is formed by bonding a heat sink 2 to one surface of a printed wiring board (resin substrate) 3 having a cavity hole. A semiconductor element (IC)
Chip) 5 is mounted. The pad portion of the semiconductor element 5 and the pad portion of the printed wiring board 3 are electrically connected by wire bonding. Cavity recess 4
Is formed by joining a solder ball 7 to a substrate terminal portion after sealing with a sealing resin 6.
【００１３】図２（ａ）（ｂ）に示す半導体パッケージ
１は、プリント配線板（樹脂基板）３のランド部が形成
された一方の面に半導体素子（ＩＣチップ）５がフリッ
プチップ接続されている。この半導体素子５はアンダー
フィルモールドされて、半導体素子−プリント配線板間
の隙間が封止されている。また、半導体素子５の周囲に
は補強材（スティッフナー）８が設けられている。放熱
板２は半導体素子５及び補強材８に貼り合わされてい
る。また、プリント配線板３の他方の面にはランド部が
形成されており、はんだボール７が接合されている。A semiconductor package 1 shown in FIGS. 2A and 2B has a semiconductor element (IC chip) 5 flip-chip connected to one surface of a printed wiring board (resin substrate) 3 on which a land is formed. I have. The semiconductor element 5 is underfill-molded to seal a gap between the semiconductor element and the printed wiring board. A reinforcing material (stiffener) 8 is provided around the semiconductor element 5. The heat sink 2 is bonded to the semiconductor element 5 and the reinforcing member 8. Further, a land portion is formed on the other surface of the printed wiring board 3, and a solder ball 7 is joined thereto.
【００１４】図１（ａ）及び図２（ａ）において、放熱
板２は半導体素子５より生じた熱を外部へ放散させるも
ので、銅又は銅合金よりなる金属板の所定部位（例えば
１番ピン位置）に、半導体パッケージ１を基板実装する
際の指標となるマーク９が黒色酸化処理法により形成さ
れている。具体的には、金属板の所定部位（例えば１番
ピン位置）に、厚さ２〜３μｍ程度の金属酸化膜（黒色
酸化銅膜、ブラックオキサイド）によるマーク９が形成
されており、該マーク９を除く部位は金属めっき皮膜
（例えばニッケルめっき皮膜）で覆われている。このマ
ーク９は、金属酸化膜により形成されているため、耐熱
性がありしかも極めて薄いため取扱い性に影響を与える
ことがなく、色も鮮明で放熱板２の他の部位と識別し易
い。In FIG. 1A and FIG. 2A, a heat radiating plate 2 is for dissipating heat generated from a semiconductor element 5 to the outside, and is provided at a predetermined portion (for example, No. 1) of a metal plate made of copper or a copper alloy. A mark 9 serving as an index when the semiconductor package 1 is mounted on a substrate is formed at a (pin position) by a black oxidation treatment method. Specifically, a mark 9 made of a metal oxide film (black copper oxide film, black oxide) having a thickness of about 2 to 3 μm is formed at a predetermined portion (for example, the position of the first pin) of the metal plate. Are covered with a metal plating film (for example, a nickel plating film). Since the mark 9 is formed of a metal oxide film, it has heat resistance and is extremely thin, so that it does not affect handling properties, and has a clear color and can be easily distinguished from other parts of the heat sink 2.
【００１５】ここで、放熱板２の製造工程について図３
を参照して説明する。厚さ０．２５ｍｍ程度の銅又は銅
合金よりなる金属板１０には、パッケージサイズに応じ
た放熱板となるエリアがマトリクス状に形成されてい
る。この金属板１０の一方の面には、各エリア内の所定
部位（１番ピンに相当する位置）にマスクを形成する。
具体的には、各エリア内の所定部位（１番ピンに相当す
る位置）を、φ２．０ｍｍ程度の耐薬品性のあるマスク
１１により覆う。マスク１１としては、例えばインクを
塗布したりフィルムを貼着したりする。Here, the manufacturing process of the heat sink 2 will be described with reference to FIG.
This will be described with reference to FIG. On a metal plate 10 made of copper or a copper alloy having a thickness of about 0.25 mm, areas serving as heat sinks corresponding to package sizes are formed in a matrix. On one surface of the metal plate 10, a mask is formed at a predetermined portion (a position corresponding to the first pin) in each area.
Specifically, a predetermined portion (a position corresponding to the 1st pin) in each area is covered with a chemically resistant mask 11 of about φ2.0 mm. As the mask 11, for example, ink is applied or a film is attached.
【００１６】次に、金属板１０めっき槽に浸漬させて、
マスク１１で覆われた部位以外の露出面に金属めっき皮
膜（ニッケルめっき皮膜）１２で覆う。次に、金属板１
０よりマスク１１を剥離した後、酸化処理液（黒化処理
液）に浸漬させて、金属板１０の露出面上に金属酸化膜
によるマーク９を形成する。この後、金属板１０を切断
線１３に沿ってダイシングして放熱板２が個片に分離さ
れる。尚、ダイシングは、マーク９が形成された金属板
１０を半導体パッケージにマウントしてから行っても良
い。このように、金属酸化膜によるマーク９が簡易な方
法で一括して形成できるので、生産性が良く、しかも低
コストで量産できる。Next, the metal plate 10 is immersed in a plating bath,
The exposed surface other than the portion covered with the mask 11 is covered with a metal plating film (nickel plating film) 12. Next, the metal plate 1
After removing the mask 11 from 0, the mask 9 is immersed in an oxidation treatment liquid (blackening treatment liquid) to form a mark 9 of a metal oxide film on the exposed surface of the metal plate 10. Thereafter, the metal plate 10 is diced along the cutting line 13 to separate the heat sink 2 into individual pieces. The dicing may be performed after the metal plate 10 on which the mark 9 is formed is mounted on a semiconductor package. As described above, since the marks 9 made of the metal oxide film can be collectively formed by a simple method, the productivity is good and mass production can be performed at low cost.
【００１７】次に、図１（ａ）（ｂ）の半導体パッケー
ジ１の製造方法について説明する。前述した製造方法に
より製造された放熱板２を、プリント配線板３の一方の
面に貼り合わせてキャビティ凹部４を形成する。次にキ
ャビティ凹部４の底部に半導体素子５を搭載し、該半導
体素子５とプリント配線板３とをワイヤボンディングに
より電気的に接続する。次に、半導体素子５を収容する
キャビティ凹部４を封止樹脂６により封止する最後に、
プリント配線板３の他方の面に形成されたパッド部には
んだボール７を搭載してリフローすることにより接合
し、半導体パッケージ１が形成される。Next, a method of manufacturing the semiconductor package 1 shown in FIGS. 1A and 1B will be described. The heat sink 2 manufactured by the above-described manufacturing method is bonded to one surface of the printed wiring board 3 to form the cavity recess 4. Next, the semiconductor element 5 is mounted on the bottom of the cavity recess 4, and the semiconductor element 5 and the printed wiring board 3 are electrically connected by wire bonding. Next, finally, the cavity concave portion 4 accommodating the semiconductor element 5 is sealed with the sealing resin 6.
The semiconductor package 1 is formed by mounting the solder balls 7 on the pad portions formed on the other surface of the printed wiring board 3 and performing reflow to join them.
【００１８】次に、図２（ａ）（ｂ）の半導体パッケー
ジ１の製造方法について説明する。プリント配線板３の
一方の面に形成されたパッド部に、金属バンプによるチ
ップ接続端子が形成された半導体素子５をフリップチッ
プ接続する。チップ接続端子は、はんだボール、はんだ
バンプなど様々なものが用いられる。次に、フリップチ
ップ接続された半導体素子５をアンダーフィルモールド
する。即ち、半導体素子−プリント配線板間の隙間に封
止樹脂６が充填されて封止される。この封止樹脂６は、
ポッティング或いはトランスファ成形などにより樹脂封
止される。Next, a method of manufacturing the semiconductor package 1 shown in FIGS. 2A and 2B will be described. A semiconductor element 5 having chip connection terminals formed by metal bumps is flip-chip connected to a pad portion formed on one surface of the printed wiring board 3. Various types of chip connection terminals such as solder balls and solder bumps are used. Next, the semiconductor element 5 that has been flip-chip connected is underfill-molded. That is, the gap between the semiconductor element and the printed wiring board is filled with the sealing resin 6 and sealed. This sealing resin 6
Resin sealing is performed by potting or transfer molding.
【００１９】次に、半導体素子５の周囲のプリント配線
板３上に補強材８を接着などにより設ける。そして、前
述した製造方法により製造された放熱板２を、半導体素
子５及び補強材８に貼り合わせる。最後に、プリント配
線板３の他方の面に形成されたパッド部にはんだボール
７を搭載してリフローすることにより接合し、半導体パ
ッケージ１が形成される。Next, a reinforcing material 8 is provided on the printed wiring board 3 around the semiconductor element 5 by bonding or the like. Then, the heat sink 2 manufactured by the above-described manufacturing method is bonded to the semiconductor element 5 and the reinforcing member 8. Finally, the solder balls 7 are mounted on the pad portions formed on the other surface of the printed wiring board 3 and are joined by reflowing to form the semiconductor package 1.
【００２０】上記構成によれば、放熱板２には、所定部
位（例えば１番ピン位置）にマーク９が金属酸化膜によ
り形成されているため、耐熱性がありしかも極めて薄く
形成でき、しかも鮮明に形成できる。また、マーク９は
簡易な方法で一括して形成できるので、生産性が良く、
しかも低コストで量産できる。また、上記放熱板２を備
えた半導体パッケージ１においては、マーク９に耐熱性
があるため、パッケージ製造工程でマーク９が形成され
た放熱板２を用いて半導体パッケージ１を製造できるの
で、使い勝手が良くしかも半導体パッケージ１の向きを
視認しながら製造したり基板実装することができる。ま
た、マーク９は極めて薄く形成できるので、半導体パッ
ケージ１を基板実装する際の取扱性が良く、実装位置精
度や高さ精度も向上させることができる。According to the above configuration, since the mark 9 is formed of a metal oxide film at a predetermined position (for example, the position of the first pin) on the heat sink 2, it is heat-resistant and can be formed extremely thinly, and is sharp. Can be formed. Further, since the marks 9 can be collectively formed by a simple method, the productivity is good,
In addition, mass production can be performed at low cost. Further, in the semiconductor package 1 provided with the heat radiating plate 2, since the mark 9 has heat resistance, the semiconductor package 1 can be manufactured by using the heat radiating plate 2 on which the mark 9 is formed in the package manufacturing process, so that the usability is improved. In addition, the semiconductor package 1 can be manufactured or mounted on a board while visually confirming the direction of the semiconductor package 1. Further, since the mark 9 can be formed extremely thin, the handleability when mounting the semiconductor package 1 on a substrate is good, and the mounting position accuracy and height accuracy can be improved.
【００２１】以上、本発明の好適な実施例を挙げて説明
したが、本発明は上記各実施例に限定されるものでな
く、放熱板２の材料、マーク９を形成する際のマスク１
１の材料や形成方法、金属めっき皮膜１２の材料などは
他の方法、材料であっても良い等、発明の精神を逸脱し
ない範囲内で多くの改変を施し得ることはもちろんであ
る。Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, but is not limited to the above-described embodiments.
Of course, many modifications can be made without departing from the spirit of the invention, such as the first material, the forming method, and the material of the metal plating film 12 may be other methods and materials.
【００２２】[0022]
【発明の効果】本発明の放熱板及びその製造方法によれ
ば、放熱板には、所定部位（例えば１番ピン位置）にマ
ークが金属酸化膜により形成されているため、耐熱性が
ありしかも極めて薄く形成でき、しかも鮮明に形成でき
る。また、マークは簡易な方法で一括して形成できるの
で、生産性が良く、しかも低コストで量産できる。ま
た、放熱板を用いた半導体パッケージ及びその製造方法
によれば、マークに耐熱性があるため、パッケージ製造
工程でマークが形成された放熱板を用いて半導体パッケ
ージを製造できるので、使い勝手が良くしかも半導体パ
ッケージ１の向きを視認しながら製造したり基板実装す
ることができる。また、マークは極めて薄く形成できる
ので、半導体パッケージを基板実装する際の取扱性が良
く、実装位置精度や高さ精度も向上させることができ
る。According to the heat radiating plate and the method of manufacturing the same according to the present invention, the heat radiating plate has heat resistance since the mark is formed by a metal oxide film at a predetermined portion (for example, the position of the first pin). It can be formed extremely thin and can be formed clearly. Further, since the marks can be collectively formed by a simple method, mass production can be performed with good productivity and at low cost. Further, according to the semiconductor package using the heat sink and the manufacturing method thereof, since the mark has heat resistance, the semiconductor package can be manufactured using the heat sink on which the mark is formed in the package manufacturing process. The semiconductor package 1 can be manufactured or mounted on a board while visually confirming the direction of the semiconductor package 1. Further, since the mark can be formed extremely thin, the handleability when mounting the semiconductor package on the substrate is good, and the mounting position accuracy and height accuracy can be improved.
【図１】半導体パッケージの上視図及び断面説明図であ
る。FIG. 1 is a top view and a sectional explanatory view of a semiconductor package.
【図２】半導体パッケージの上視図及び断面説明図であ
る。FIG. 2 is a top view and a cross-sectional explanatory view of a semiconductor package.
【図３】放熱板の製造工程を示す説明図である。FIG. 3 is an explanatory view showing a manufacturing process of the heat sink.
【図４】従来の半導体パッケージの上視図及び断面説明
図である。FIG. 4 is a top view and a cross-sectional explanatory view of a conventional semiconductor package.
【図５】従来の半導体パッケージの上視図及び断面説明
図である。FIG. 5 is a top view and a sectional explanatory view of a conventional semiconductor package.
【符号の説明】 １ 半導体パッケージ ２ 放熱板 ３ プリント配線板 ４ キャビティ凹部 ５ 半導体素子 ６ 封止樹脂 ７ はんだボール ８ 補強材 ９ マーク １０ 金属板 １１ マスク １２ 金属めっき皮膜 １３ 切断線[Description of Signs] 1 Semiconductor package 2 Heat sink 3 Printed wiring board 4 Cavity recess 5 Semiconductor element 6 Sealing resin 7 Solder ball 8 Reinforcement 9 Mark 10 Metal plate 11 Mask 12 Metal plating film 13 Cutting line
───────────────────────────────────────────────────── フロントページの続き (72)発明者 加藤 洋二 長野県茅野市塚原１−８−37 株式会社イ ースタン内 Ｆターム(参考） 5F036 AA01 BB08 BC05 BD01 BE09 5F044 KK05 KK21 RR10 ────────────────────────────────────────────────── ─── Continued on front page (72) Inventor Yoji Kato 1-8-37 Tsukahara, Chino-shi, Nagano F-term in Eastern Co., Ltd. (Reference) 5F036 AA01 BB08 BC05 BD01 BE09 5F044 KK05 KK21 RR10
Claims (7)
て設けられ、当該半導体素子より生じた熱を外部へ放散
させる放熱板において、 銅又は銅合金よりなる金属板の所定部位に、前記半導体
パッケージを基板実装する際の指標となるマークが黒色
酸化処理法により形成されていることを特徴とする放熱
板。1. A heat radiating plate provided close to a semiconductor element of a semiconductor package and dissipating heat generated by the semiconductor element to the outside, wherein the semiconductor package is mounted on a predetermined portion of a metal plate made of copper or a copper alloy. A heat radiating plate, wherein marks serving as indices for mounting on a substrate are formed by a black oxidation treatment method.
によるマークが形成されており、該マークを除く部位は
金属めっき皮膜で覆われていることを特徴とする請求項
１記載の放熱板。2. The heat radiation according to claim 1, wherein a mark made of a metal oxide film is formed at a predetermined portion of the metal plate, and a portion other than the mark is covered with a metal plating film. Board.
一方の面に貼り合わされたキャビティ凹部が形成されて
いることを特徴とする半導体パッケージ。3. A semiconductor package, wherein the heat sink according to claim 1 or 2 is formed with a cavity concave portion bonded to one surface of a substrate.
にフリップチップ接続された半導体素子及び該半導体素
子の周囲に設けられた補強材に貼り合わされていること
を特徴とする半導体パッケージ。4. A semiconductor package, wherein the heat sink according to claim 1 or 2 is bonded to a semiconductor element which is flip-chip connected on a substrate and a reinforcing member provided around the semiconductor element. .
て設けられ、当該半導体素子より生じた熱を外部へ放散
させる放熱板の製造方法において、 銅又は銅合金よりなる金属板の一方の面に、所定部位に
マスクを形成する工程と、 前記金属板のマスクで覆われた部位以外の露出面を金属
めっき皮膜で覆う工程と、 前記金属板より前記マスクを剥離した後酸化処理液に浸
漬させて、露出面上に金属酸化膜によるマークを形成す
る工程とを含むことを特徴とする放熱板の製造方法。5. A method of manufacturing a radiator plate provided close to a semiconductor element of a semiconductor package and dissipating heat generated from the semiconductor element to the outside, wherein one side of a metal plate made of copper or a copper alloy is Forming a mask on a predetermined portion, covering the exposed surface of the metal plate other than the portion covered with the mask with a metal plating film, and removing the mask from the metal plate and then immersing the mask in an oxidation treatment solution. Forming a mark of a metal oxide film on the exposed surface.
された放熱板を、基板の一方の面に貼り合わせてキャビ
ティ凹部を形成する工程と、 前記キャビティ凹部に前記半導体素子を搭載して該半導
体素子と前記基板とを電気的に接続する工程と、 前記半導体素子を収容するキャビティ凹部を樹脂封止す
る工程と、 前記基板の他方の面に端子を形成する工程とを含むこと
を特徴とする半導体パッケージの製造方法。6. A step of bonding a heat sink manufactured by the manufacturing method according to claim 4 to one surface of a substrate to form a cavity recess, and mounting the semiconductor element in the cavity recess. Electrically connecting the semiconductor element and the substrate, resin sealing a cavity recess accommodating the semiconductor element, and forming a terminal on the other surface of the substrate. Semiconductor package manufacturing method.
チップ接続する工程と、 前記フリップチップ接続された半導体素子をアンダーフ
ィルモールドする工程と、 前記半導体素子の周囲の基板上に補強材を設ける工程
と、 前記請求項４記載の製造方法により製造された放熱板
を、前記半導体素子及び補強材に貼り合わせる工程と、 前記基板の他方の面に端子を形成する工程とを含むこと
を特徴とする半導体パッケージの製造方法。7. A step of flip-chip connecting a semiconductor element to one surface of a substrate, a step of underfill molding the flip-chip connected semiconductor element, and providing a reinforcing material on the substrate around the semiconductor element. A step of bonding a heat sink manufactured by the manufacturing method according to claim 4 to the semiconductor element and the reinforcing material; and a step of forming a terminal on the other surface of the substrate. Semiconductor package manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000375520A JP3602052B2 (en) | 2000-12-11 | 2000-12-11 | Heat sink and method of manufacturing the same, semiconductor package and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000375520A JP3602052B2 (en) | 2000-12-11 | 2000-12-11 | Heat sink and method of manufacturing the same, semiconductor package and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002176075A true JP2002176075A (en) | 2002-06-21 |
| JP3602052B2 JP3602052B2 (en) | 2004-12-15 |
Family
ID=18844524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000375520A Expired - Fee Related JP3602052B2 (en) | 2000-12-11 | 2000-12-11 | Heat sink and method of manufacturing the same, semiconductor package and method of manufacturing the same |
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| Country | Link |
|---|---|
| JP (1) | JP3602052B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002190555A (en) * | 2000-12-20 | 2002-07-05 | Ibiden Co Ltd | Heat sink assembly and heat sink |
| JP2006294714A (en) * | 2005-04-07 | 2006-10-26 | Hitachi Kokusai Electric Inc | Heat sink of pa module |
-
2000
- 2000-12-11 JP JP2000375520A patent/JP3602052B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002190555A (en) * | 2000-12-20 | 2002-07-05 | Ibiden Co Ltd | Heat sink assembly and heat sink |
| JP2006294714A (en) * | 2005-04-07 | 2006-10-26 | Hitachi Kokusai Electric Inc | Heat sink of pa module |
| JP4584757B2 (en) * | 2005-04-07 | 2010-11-24 | 株式会社日立国際電気 | PA module heat sink |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3602052B2 (en) | 2004-12-15 |
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