JP2002175969A - Method of testing pattern and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of testing a pattern which can improve simulation accuracy of a layout pattern for an actual product. SOLUTION: Using an exposure mask form, based on a prescribed pattern data, a test pattern is formed on different bases on a semi conductor substrate (S10-S12). A light intensity pattern is formed by optical simulation using the pattern data (S13), and a model for specifying the quantity of corrections correlated with the difference in size between the light intensity pattern and the test pattern is developed (S14, S15). The developed model is applied to the optical simulation, using the layout design pattern data of a semiconductor integrated circuit to form a light intensity pattern (S21, S22, S23). By modeling the influence due to the bases to be formed with a pattern, such as etching rate, which has not been taken into consideration in the conventional optical simulation, such an influence can be reflected on the optical simulation result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of verifying a pattern of an exposure mask (photomask) of a semiconductor integrated circuit or a completed pattern on a wafer, and a data processing system for providing a service through a network. For example, the present invention relates to a technique effective when applied to an optical simulation performed when forming a mask pattern based on layout design pattern data of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art With the miniaturization of a semiconductor integrated circuit process, when an attempt is made to form a pattern having a width smaller than the wavelength of light, the pattern shape actually formed with respect to the pattern of an exposure mask is deformed, and a partial pattern is formed. It becomes thinner and thicker. To form a desired pattern, it is desirable to evaluate a pattern actually formed by the mask pattern in advance by simulation. Therefore, as an experimental model, typical test patterns such as isolated lines, line spaces, and line ends are prepared in variations of various dimensions. After the necessary wafer processing, such as transfer or etching, using the mask of the test pattern, the dimensions of a prescribed portion such as the pattern width are measured. A model (model equation) for extracting a difference between the measured value and the pattern dimension based on the result of the optical simulation based on the test pattern data as a correction value for the pattern based on the simulation result is extracted. At the time of an actual simulation for a layout pattern or a mask pattern, a result corrected by the model is output as a result obtained by the optical simulation.

[0003]

However, the test pattern used for the model creation takes into account the pattern shape and processing only on a single layer, and does not include effects such as the influence of a base. In short, a test pattern is formed as a single-layer film on a mirror wafer or a uniform multilayer film, which is different from a pattern on a semiconductor integrated circuit having a multilayer structure whose structure differs depending on an actual region. As described above, the current model is premised on a single layer, and is usually created as a single layer film on a uniform film quality. Therefore, an actual product partially differs from the result of the optical simulation.

[0004] Therefore, the above-mentioned simulation has a reduced reliability, and can be used only for an auxiliary purpose in generating pattern data of an exposure mask and verifying proximity effect correction. As an actual countermeasure against this, it is inevitable that the error is used as a margin to loosen the used dimension rule. Further, if a process countermeasure is taken to reduce this error, the overall optimization of the process technology will be insufficient.

Therefore, the present inventor has found that it is useful to generate the model in consideration of the influence of the base on which the pattern is formed, for example, the influence of the base on the etching rate, the reflectance, and the step. In this case, it is further necessary to create a model for each base from various effects such as etching rate / reflectance / step, and measurement of about 200 points per model is required. The present inventor has found that it is necessary for a manufacturer of a semiconductor integrated circuit to increase the efficiency by dividing the measurement and generation of a model into specialized tasks or specialized tasks.

Further, considering the influence of the background, a mask shift or the like also affects the pattern at a boundary portion where the background is different. It has been clarified by the present inventor that the selection must be made in consideration of the above.

An object of the present invention is to provide a pattern verification method capable of improving the simulation accuracy of a layout pattern for an actual product.

Another object of the present invention is to provide a data processing system capable of efficiently creating and measuring a correction model used for optical simulation of a layout pattern using a network.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] The pattern verification method according to the present invention
A first step of forming test patterns (multi-layer test patterns) on different bases on a semiconductor substrate using an exposure mask formed based on predetermined pattern data, and forming a light intensity pattern by optical simulation using the pattern data A second step of generating a model defining a correction amount (light intensity or dimensional correction amount) correlating to a dimensional difference of the light intensity pattern with respect to the test pattern; and a layout design pattern of the semiconductor integrated circuit. Applying the model to an optical simulation using the data to form a light intensity pattern.

In the first step, a model is conventionally created using the same test pattern for different bases of a semiconductor integrated circuit, but a test pattern taking into account the difference in the vertical structure of each base layer is used. I do. For example, in the case of a gate layer, a region above the N-type semiconductor region (N +) and a region
Since the etching rate is different on +), separate test patterns are formed on N + and P + even if the pattern dimensions are the same.

In the fourth step, when executing the optical simulation, a corresponding model is selected and used in consideration of the actual layout state of the base of the simulation target layer.

According to the above verification method, the influence of the base on which the pattern is formed, such as the etching rate, which was not taken into account in the conventional optical simulation, is reflected in the optical simulation result using the above-described model based on the multilayer test pattern. Therefore, the simulation accuracy of the layout pattern for the actual product can be improved.

[0015] As an effect due to the difference between the bases, the effect that can be directly optically corrected such as reflection (shift of exposure intensity) and the step (defocus) is separated from other effects such as an etching rate. For the items that can be directly corrected by the effect, the model is created by calculating in advance by optical simulation from the reflectance, step height without finding from the test pattern, or the model is unnecessary by calculating each time by optical simulation. It is possible to

In the fourth step, the model is not mechanically switched at the boundary portion at the boundary portion where the base is different, but the worst value of the model (the model with a large amount of dimensional correction) and the best A value (a model with a small amount of dimensional correction), an average value of the best value and the worst value, a continuous function obtained by linearly approximating the best value and the worst value, and the like can be selected according to the use of the simulation. For example, when performing the automatic correction by the proximity effect correction based on the optical simulation result, it is uncertain which model area is to be manufactured at the time of manufacture, reflecting other errors such as mask shift,
It is not desirable to use the worst value because of the possibility of overcorrection. Conversely, when the optical simulation is used for pattern verification, the worst value may be needed.
This boundary processing further improves the simulation accuracy of the layout pattern.

At the boundary, if high-precision modeling is not possible due to a change in film thickness due to a step, halation, or the like, graphic processing such as quantitative dimension shift can also be applied.

[2] In the pattern verification method using the above-described model, since a large number of test patterns are formed on different bases, a great deal of labor is required for measuring the formed test patterns. For semiconductor integrated circuit manufacturers, if they are concerned about insufficient power of process engineers due to the measurement effort, it is desirable to outsource them or to specialize them. At this time, it is possible to quantify the process influence required for high-precision simulation, such as an etching rate, by using a model in advance, so that a model other than a process engineer can create the model. As described above, by improving the accuracy / reliability of the simulation by the pattern verification method using the model, making the correction model creation non-process engineer, etc., the semiconductor integrated circuit manufacturing process, the model creation, and the mask pattern creation. It is possible to divide the simulation according to (1) or from the semiconductor maker to other specialized tasks, and it is expected that there will be no problem.

The following data processing system, which focuses on this point of view, provides a mechanism that enables the creation and measurement of a model used for an optical simulation of a layout pattern to be performed in a division of labor and efficiently using a network.

A. The data processing system has an information processing device connectable to a network. The information processing device, in response to a predetermined request via a network, a process of transmitting predetermined pattern data for forming a test pattern on a different base on a semiconductor substrate to the request source via the network, The process of obtaining a light intensity pattern by an optical simulation using the pattern data, and the difference in size of the light intensity pattern with respect to a test pattern on a test wafer manufactured by the requester using an exposure mask based on the transmitted pattern data. And a process of generating a model that defines a correlated correction amount. This data processing system assumes a case where the provision of pattern data and the creation of a model are separated or specialized by a semiconductor manufacturer, and the division or the specialized company includes the information processing device.

B. A data processing system according to another aspect has an information processing device connectable to a network.
The information processing apparatus is manufactured using a process of obtaining a light intensity pattern by optical simulation using predetermined pattern data for forming test patterns on different bases on a semiconductor substrate, and an exposure mask based on the pattern data. A process of generating a model that defines a correction amount correlating to a dimensional difference of the light intensity pattern with respect to a test pattern on a test wafer, and transmitting the data of the generated model to a manufacturer of the test wafer via the network. Processing is enabled. In this data processing system, it is assumed that the creation and provision of the model is to be separated or specialized by a semiconductor manufacturer, and the division or dedicated company has the information processing device.

C. A) above. And b. The information processing system according to the aspect in which the information processing apparatus is combined has an information processing apparatus connectable to a network. The information processing apparatus includes: a process for obtaining a light intensity pattern by optical simulation using predetermined pattern data for forming a test pattern on a different base on a semiconductor substrate; and a semiconductor device in response to a predetermined request via a network. A process of transmitting predetermined pattern data for forming a test pattern on a different base on the substrate to the request source via the network; and a test manufactured by the request source using an exposure mask based on the transmitted pattern data. A process of generating a model that defines a correction amount correlated with a dimensional difference of the light intensity pattern with respect to a test pattern on a wafer, and a process of transmitting data of the generated model to the request source via a network, Enabled.

[3] A data processing system from the viewpoint of dividing the creation of models and the creation of mask pattern data into divisions of work for manufacturers of semiconductor integrated circuits is a first information processing apparatus and a second information connectable to a network. It has a processing device. The first information processing apparatus includes a process of obtaining a light intensity pattern by an optical simulation using predetermined pattern data for forming a test pattern on a different base on a semiconductor substrate, and a process of manufacturing using an exposure mask based on the pattern data. Generating a model that defines a correction amount that correlates to a dimensional difference of the light intensity pattern with respect to the test pattern on the test wafer, and transmitting the generated model to a manufacturer of the test wafer via the network. Processing is enabled. The second information processing device receives the model and a layout design pattern data of a semiconductor integrated circuit from a manufacturer of the test wafer via the network, and applies the model to an optical simulation using the received layout design pattern data. Then, a light intensity pattern is generated, and data of a mask pattern evaluated using the generated light intensity pattern is generated, and this can be transmitted to a manufacturer of the test wafer via the network.

The second information processing apparatus may add an effect by proximity effect correction to the simulation of the mask pattern.

With respect to the processing of the boundary part, the second information processing apparatus can select from a plurality of types having different correction amounts for the model as the model applied to the boundary part having a different background. When determining the correction amount of the proximity effect correction from the simulation result of the mask pattern to which the model is applied, selecting a model that minimizes the proximity effect correction, and using the simulation result of the mask pattern to which the model is applied for verification of the mask pattern May select a model that maximizes the correction amount.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION << Single-Layer Test Pattern >> A model generated using a multi-layer test pattern is used for correcting an optical simulation result by the pattern verification method according to the present invention. First, a conventional single-phase test pattern to be compared with a multilayer test pattern will be described.

FIG. 2 shows an example of a single-layer test pattern. The single-layer test pattern is formed of a plurality of isolated lines having different widths formed on a mirror wafer (a single wafer having no horizontal partitioned area such as a well or a vertical stacked area formed on a single-crystal silicon wafer). 2A to 2C, parallel lines 3A to 3E having different widths and intervals, 4A to 4E, 5
A to 5E, etc., which are composed of a single-layer film or a uniform multilayer film on a silicon wafer, taking into account the underlying laminated structure of semiconductor regions, insulating layers, wiring layers, etc. in an actual multilayer semiconductor integrated circuit. Absent. The width of the test pattern formed on the wafer is measured.

FIG. 3 illustrates a processing procedure of a pattern verification method using a model generated using a single-layer test pattern. A test pattern mask is generated using the single-layer test pattern data (S1), and using this, a test wafer having the single-layer test pattern is generated by performing exposure and etching on a uniform film quality, for example, a mirror wafer. (S2). With respect to each test pattern actually formed on the test wafer, its width dimension and the like are measured at many places (S3). Further, a light intensity pattern is generated by optical simulation using the test pattern data (S4). This light intensity pattern is a pattern specified by a light intensity distribution when it is assumed that a photomask having a shape specified by the test pattern data is used and the pattern is imaged on a wafer. A difference between the test pattern and the light intensity pattern is extracted (S5), and a model is generated that uses the difference as a correction amount suitable for the parameters of the optical simulation (S6). The model has a light intensity pattern correction amount to be corrected according to the shape or size of the test pattern.

In the verification using the layout pattern data of the semiconductor integrated circuit, an optical simulation using the layout pattern data is performed (S7), and the light intensity pattern obtained by the simulation is corrected using the model (S8). As a result, a layout pattern corrected with the range based on the experimental model defined by the single-layer test pattern as a limit can be obtained as a light intensity pattern. The pattern of the photomask or the proximity effect correction will be verified with reference to this light intensity pattern. However, since the light intensity pattern obtained through step S8 is based on a single-layer test pattern,
In many cases, the generated pattern is separated from the generated pattern in an actual semiconductor integrated circuit having a multilayer structure.

<< Multilayer Test Pattern >> FIG. 4 exemplifies the difference of the base in a multilayer structure such as an actual semiconductor integrated circuit. For example, polysilicon wiring pattern 1
Focusing on 0 and 11, p-type semiconductor substrate (Psub field region) 12, N + semiconductor region (Psub active region) 13, n-type well region (Nwell region) 1
4, P + semiconductor region (Nwell active region) 15
As described above, the reflectance from the base differs depending on the difference between the bases. Further, an N + semiconductor region (Psub active region)
12, 13, an n-type well region (Nwell region) 14,
As in the case of the P + semiconductor region (Nwell active region) 15, the etching rate of the upper layer pattern is different depending on the impurity concentration and the conductivity type of the base. As shown in FIG. 4, in a multilayer structure of a semiconductor integrated circuit, the reflectivity and the etching rate are different depending on the underlying structure. Therefore, a multilayer test pattern is used to obtain an experimental model for considering the difference. .

FIG. 5 illustrates a multi-layer test pattern corresponding to the single-layer test pattern of FIG. The example of FIG. 5 has only layers with different processing dimensions in etching, and the effects of reflection and defocus caused by the difference in the thickness of the oxide film and the nitride film as the underlayer and the difference in the film thickness do not use the test pattern. It is determined in advance by optical simulation. That is, the Psub active region (N + layer) 1 formed in the Psub field region 12 is used as a base region for making a difference in processing dimension in etching.
3 and an Nwell active region (P + layer) 15 formed in the Nwell region 14. In the Psub active region (N + layer) 13, a plurality of isolated lines 16A to 16A having different widths are formed, for example, as polysilicon layers.
C, parallel lines 17A to 17E and 18 having different widths and intervals
A-18E and 19A-19E are formed. Nwell
In the active region (P + layer) 15, for example, as a polysilicon layer, a plurality of isolated lines 20 having different widths are provided.
A to 20C, parallel lines 21A to 21 having different widths and intervals
E, 22A to 22E and 23A to 23E are formed. The multilayer test pattern is actually formed as a test wafer based on test pattern data.

FIG. 6 shows another example of a multilayer test pattern corresponding to the single-layer test pattern of FIG. The example of FIG. 6 differs from that of FIG. 5 in that the test pattern takes into account the difference in the processing dimensions due to etching and the difference due to the difference in the reflection due to the difference in the oxide film and nitride film as the underlayer and the difference in the film thickness. Different. In this case, the portion for examining the effect of reflection can simplify the dimension measurement points for the pattern. It is also possible to examine the effect of a boundary portion extending over a plurality of regions described later by preparing a dedicated test pattern for that purpose.

In the example of FIG. 6, the Psub field region 12, the Psub active region (N + layer) 13, and the N
well region 14, Nwell active region (P +
Layer) 15. Psub active area (N + layer) 1
A test pattern similar to that shown in FIG. 5 is formed in 3 and the Nwell active area (P + layer) 15. In the Psub field region 12, for example, as a polysilicon layer, a plurality of isolated lines 24A to 24C having different widths, and parallel lines 25A to 25E and 26A to 26 having different widths and intervals are provided.
E, 27A to 27E are formed. Nwell area 14
For example, as a polysilicon layer, a plurality of isolated lines 28A to 28C having different widths, and parallel lines 29A to 29E, 30A to 30E, 31A to 3E having different widths and intervals are provided.
1E is formed. The multilayer test pattern is actually formed as a test wafer based on test pattern data.

<< Pattern Verification Method >> FIG. 1 exemplifies a flowchart of a pattern verification method from generation of a polyphase test pattern to optical simulation using a model. First, a test pattern mask (exposure mask) is generated based on the predetermined multi-phase test pattern data (S
10), wafer processing such as exposure and etching is performed on the semiconductor wafer by using this (S11), and the above-mentioned steps S10 and S1 are performed for the required number of layers of the multilayer test pattern.
1 is repeated to generate a test wafer having a multilayer test pattern. The dimensions of the test pattern formed on the test wafer are measured at multiple locations with respect to the width of the isolated line, the line width of the parallel line, and the like (S12). A light intensity pattern is generated by optical simulation using the multilayer test pattern data (S1).
3). This light intensity pattern is a pattern specified by the light intensity distribution when it is assumed that a photomask having a shape specified by the multilayer test pattern data is used and the pattern is imaged on the wafer. A difference between the multi-layer test pattern (measured value) and the light intensity pattern is extracted (S14), and a model is generated that uses the difference as a correction amount suitable for the parameters of the optical simulation (S15). The model has the correction amount of the light intensity pattern to be corrected according to the shape or size of the test pattern and the state of the base on which the test pattern is formed. The multi-layer test pattern assumed here has only the underlayer which makes the processing dimensions different in the etching as described with reference to FIG. Shall not be considered. The models generated here are M1 to Mn. For example, the models M1 to Mn have data specifying the pattern width and the underlying structure, and defining the amount of correction for correcting the shape of the pattern to be thick or thin.

The influence of the reflection corresponding to the difference between the bases is determined in advance by an optical simulation without using a test pattern as an experimental model. That is, a light intensity pattern is generated by an optical simulation using the multilayer test pattern data (S16), and this light intensity pattern is caused by a difference in an oxide film, a nitride film, etc. as a base layer or a difference in film thickness. The influence of the reflection and the influence of the height of the step are corrected (S17), and the correction by the model is performed (S18). The difference between the light intensity pattern obtained by performing these corrections and the light intensity pattern obtained in step S16 is extracted (S19), and a model is generated in which the difference is used as a correction amount suitable for the parameters of the optical simulation (step S19). S15). This model Mn + 1 to Mm
Specifies the dimensions of the pattern and the structure of the underlayer, along with the correction amount corresponding to the state of the underlayer that makes the etching rate different,
It also has a correction amount corresponding to the influence of the reflection and the step of the underlayer.

In verification of layout design pattern data of a semiconductor integrated circuit, layout pattern data is used.
An optical simulation is performed for each layer defined by the individual mask patterns to be simulated (S
21) Obtain a light intensity pattern. A model corresponding to the light intensity pattern obtained for each layer is selected (S22). For example, when a light intensity pattern corresponding to a mask pattern that defines a first polysilicon wiring layer is to be simulated, the state of the base of the polysilicon wiring layer is recognized with reference to layout design pattern data. Select the model corresponding to. Naturally the first
If the underlayer of the first polysilicon wiring layer is not uniform, a plurality of optimal models will be selected according to the difference in the underlayer. The corresponding light intensity pattern is corrected according to the selected model (S23). The model to be selected is selected from models M1 to Mn, or
Whether to select from 1 + 1 to Mm depends on the contents of the simulation in step S21. In short, the influence of the reflection and the step caused by the difference between the oxide film and the nitride film as the underlayer and the difference in the film thickness is essentially a factor that can be optically corrected, and therefore is considered each time in the light simulation (S21). Then, the model may be optimally selected from M1 to Mn. However, for each optical simulation, calculations must be performed each time taking into account the effects of reflection and steps corresponding to the state of the base, so that the results cannot be universally reused. May be. That is, if a necessary model is selected from the models Mn + 1 to Mm, calculation of reflection, steps, and the like can be simplified during optical simulation.

Boundary processing is performed on a boundary portion having a different background, that is, a boundary portion of a region to which the applied model is different (S24). The boundary portion is affected not only by the difference between the bases of both regions but also by the misalignment of the mask. Therefore, in consideration of this, it may be desirable to perform correction by applying a model different from that of the other part even if the background is the same in the boundary part.
For example, as shown in FIG. 7 exemplifying a correction method in a boundary region, in a boundary portion having different backgrounds, the model is not switched discontinuously, but the worst value of the model in both regions of the boundary (the amount of dimensional correction) Is the largest model), the best value (the model with small dimension correction), the average of the best and worst values,
A continuous function or the like in which the best value and the worst value are linearly approximated can be selected according to the use of the simulation. In FIG. 8 showing a specific example, it is assumed that the completed pattern is as shown in (B) with respect to the design pattern shown in (A). At this time, if automatic correction by the proximity effect correction (OPC) is performed on the boundary region 30 based on the optical simulation result, other errors such as mask shift are reflected, and there is a possibility of excessive correction. It is not desirable to use the worst value, and it is better to use the best value as in (C). Conversely, when the optical simulation is used for pattern verification, it is preferable to adopt the worst value as shown in FIG.

According to the pattern verification method using the model generated by using the above-described multilayer test pattern, the influence of the base on which the pattern is formed, such as the etching rate, which was not considered in the conventional optical simulation, is considered. Since it can be modeled by a model and reflected on an optical simulation result, the simulation accuracy of a layout pattern for an actual product can be improved.

By employing the boundary processing, the simulation accuracy of the layout pattern can be further improved.

In the case of a boundary portion, when high-precision modeling is impossible due to a change in film thickness due to a step, halation, or the like, graphic processing such as quantitative dimension shift can also be applied.

<< Data Processing System >> In the pattern verification method using the model as described with reference to FIG. 1, a large number of test patterns are formed on different bases.
A great deal of labor is required for measuring the formed test pattern. For semiconductor integrated circuit manufacturers,
If the power of the process engineer is concerned due to the labor of the measurement, it is desirable to outsource them or to specialize them to others. At this time, it is possible to quantify the process influence required for high-precision simulation, such as an etching rate, by using a model in advance, so that a model other than a process engineer can create the model. Since the accuracy and reliability of the simulation can be improved by the pattern verification method using the model, and the non-process engineer of the correction model can be created, the manufacturing process of the semiconductor integrated circuit and the creation of the model In addition, it is essentially possible to divide the simulation and the simulation related to the mask pattern creation from one another, or to specialize the simulation from a semiconductor manufacturer to another, and it is considered that there is no problem.

FIG. 9 illustrates a data processing system focusing on this point of view. This data processing system provides a mechanism that enables the creation and measurement of a model used for an optical simulation of a layout pattern to be divided and efficiently performed using a network. 40 ~
Reference numeral 42 denotes a manufacturer of the semiconductor integrated circuit. Reference numeral 50 denotes a mask maker of a semiconductor integrated circuit. The semiconductor integrated circuit manufacturers 40 to 42 have a third information processing device 31 including a computer 43, a storage unit 44, and a communication unit 45. The semiconductor integrated circuit mask maker 50
It has a first information processing device 32 having a computer 51, a storage unit 52 and a communication unit 53, and a second information processing device 33 having a computer 55, a storage unit 56 and a communication unit 57. The respective data processing devices 3
1, 32 and 33 are networks 34 such as the Internet.
Are connected to each other so as to be able to communicate information. The information processing devices 31, 32, and 33 are configured by computer devices such as workstations and personal computers.

FIG. 10 exemplifies a data processing procedure when a semiconductor integrated circuit manufacturer separates the mask maker from the production of the model by using the data processing system of FIG. . The mask maker 50 undertakes contracting for model production and contracting for mask production involving OPC processing. Semiconductor integrated circuit manufacturers are positioned as users for mask manufacturers. The first information processing device 32 in FIG. 9 mainly performs data processing for model production. The second information processing device 33 in FIG. 9 mainly performs data processing related to mask manufacturing accompanied by OPC processing.

The mask maker 50 has the above-mentioned multilayer test pattern data and the like in the storage unit 52. After designing the layout pattern, the semiconductor integrated circuit manufacturer 40 requests the photomask (exposure mask) based on the layout pattern from the mask manufacturer 50 to undertake production of the photomask. Mask maker 5 who received the request
Reference numeral 0 denotes multi-layer test pattern data or data of a test mask for manufacturing a test wafer using the multi-layer pattern data from the information processing device 32 to the information processing device 31 of the semiconductor integrated circuit maker 40 via the net arc 34. (T1). Semiconductor integrated circuit maker 40
Generates a test wafer having a test pattern using the test pattern data or the test mask data (U1). The generated testway reflects the accuracy of the manufacturing apparatus and the quality of the manufacturing technology of the semiconductor integrated circuit manufacturer. In short, even if a test wafer is manufactured using the same multi-layer test pattern data, the shape and size of the test pattern formed thereon will show values unique to the manufacturer. Incidentally, the semiconductor integrated circuit manufacturer 40 may receive the test pattern mask directly from the mask manufacturer 50 to produce the test wafer.

The mask maker 50 obtains a test wafer from the semiconductor integrated circuit maker 40 (T2).
For the test wafer, its reflectivity and step height are measured (M1), and the dimensions of the test pattern are measured (M2). The first information processing device 32 of the mask maker 50 obtains a light intensity pattern by an optical simulation using the multi-layer test pattern data, and correlates with a dimensional difference of the light intensity pattern with respect to the obtained test pattern on the test wafer. The model defining the correction amount to be performed is generated (M3). The generated model is transmitted from the first information processing device 32 to the information processing device 31 of the semiconductor integrated circuit manufacturer 40 that is the manufacturer of the test wafer via the network 34 (T3).

The semiconductor integrated circuit maker 40 confirms the contents of the model by the information processing device 31 using the received model, or performs an optical simulation of the layout using the model (U2). The accuracy information and the correction model required for the photomask are transmitted from the third information processing device 31 of the semiconductor integrated circuit manufacturer 40 to the second information processing device 33 via the network 34 in consideration of the result and the like. (T4).

The second information processing device 33 determines an OPC rule based on the model and accuracy information received from the test wafer manufacturer via the network 34 (O1). This rule includes the contents of the boundary processing related to the application of the model at the boundary. The second information processing device 33 transmits the layout pattern data of the semiconductor integrated circuit contracted to produce the mask from the third information processing device 31 of the semiconductor integrated circuit manufacturer 40 to the network 34.
(T5), an optical simulation is performed on the layout pattern according to the model and the OPC rules, and a proximity effect correction on the layout pattern and a verification on the photomask pattern are performed (O2). After this, the second information processing device 33 generates EB (electron beam) drawing data that defines the mask pattern (O3), and a photomask is manufactured using the EB drawing data. The manufactured photomask is transferred to the semiconductor integrated circuit maker 40 (T6).

As a result, the semiconductor integrated circuit maker 40 as a user can focus on wafer preparation and confirmation, layout design, and the like, which are specialized fields, and the mask maker 50 as a contractor can produce a model regardless of the user. And the production of masks can be specialized. As described above, by specializing in model creation and simulation execution, the process development cost and the number of steps for the semiconductor integrated circuit manufacturer 40 are reduced, and the development efficiency of the semiconductor integrated circuit can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, the predetermined pattern data for forming a test pattern on different bases on a semiconductor substrate is not limited to multilayer pattern data, but may be pattern data of a test mask formed based on the pattern data. In addition, the test pattern is not limited to the rectangular isolated line and the parallel line, and may be a pattern having another shape such as a bent pattern. Further, the difference of the base to be considered in the generation of the multi-layer test pattern is not limited to the difference in the etching rate and the reflectance based on the difference in the substrate region, the P + region, the N + region, the well region, and the like. Other states may be noted. The creation and provision of the model is not limited to the responsibility of the mask maker of the semiconductor integrated circuit, but may be divided into other fields or specialized.

[0051]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the influence of the base on which the pattern is formed, such as the etching rate, which was not taken into consideration in the conventional optical simulation, can be reflected in the optical simulation result by the model using the multilayer test pattern. The simulation accuracy of the layout pattern for the actual product can be improved.

By efficiently creating and measuring a correction model used for optical simulation of a layout pattern using a network, a semiconductor integrated circuit maker as a user, for example, can create and confirm a wafer in a specialized field. And a focus on layout design, etc., so that a mask manufacturer or the like as a contractor can perform specialized tasks for model production and mask production regardless of the type of user. As described above, the division or specialization of model creation and simulation execution reduces the process development cost and man-hour for the semiconductor integrated circuit manufacturer, and improves the development efficiency of the semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a pattern verification method from generation of a polyphase test pattern to optical simulation using a model.

FIG. 2 is an explanatory diagram illustrating a single-layer test pattern.

FIG. 3 is a flowchart illustrating a processing procedure of a pattern verification method using a model generated using a single-layer test pattern.

FIG. 4 is an explanatory diagram exemplifying a difference of a base to be considered in a multilayer structure such as an actual semiconductor integrated circuit;

FIG. 5 is an explanatory diagram illustrating a multilayer test pattern.

FIG. 6 is an explanatory diagram showing another example of a multilayer test pattern.

FIG. 7 is an explanatory diagram illustrating a method of applying a model in a boundary region.

FIG. 8 is an explanatory diagram separately exemplifying an adoption mode of a model for a boundary region in a case of proximity effect correction and a case of pattern verification when a completed shape for a design pattern is assumed;

FIG. 9 is a block diagram of a data processing system suitable for dividing the manufacturing process of the semiconductor integrated circuit and the simulation relating to the creation of the model and the creation of the mask pattern into specialized tasks or other specialized tasks.

FIG. 10 is a flowchart illustrating a data processing procedure when a manufacturer of a semiconductor integrated circuit uses the data processing system of FIG. 9 to separate the creation of the model and the creation of mask pattern data into a mask manufacturer.

[Explanation of symbols]

10, 11 polysilicon wiring pattern 12 p-type semiconductor substrate 13 N + semiconductor region 14 n-type well region 15 P + semiconductor region 16A-16C isolated line 17A-17D, 18A-18D, 19A-19D parallel line 20A-20C isolated line 21A- 21D, 22A to 22D, 23A to 23D Parallel line 24A to 24C Isolated line 25A to 25D, 26A to 26D, 27A to 27D Parallel line 28A to 28C Isolated line 29A to 29D, 30A to 30D, 31A to 31D Parallel line 30 Boundary region Reference Signs List 31 Information processing device of semiconductor integrated circuit maker 32 First information processing device of mask maker 33 Second information processing device of mask maker 34 Network 40-42 Semiconductor integrated circuit maker 50 Mask maker

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/82 T

Claims (17)

[Claims] A first step of forming test patterns on different bases on a semiconductor substrate using an exposure mask formed based on predetermined pattern data; and a step of forming a light intensity pattern by optical simulation using the pattern data. A second step of forming; and a third step of generating a model that defines a correction amount correlated to a dimensional difference between the light intensity pattern and the test pattern
And a fourth step of applying the model to an optical simulation using layout design pattern data of a semiconductor integrated circuit to form a light intensity pattern. 2. The pattern verification method according to claim 1, wherein the different bases are bases having different etching rates. 3. The pattern verification method according to claim 1, wherein the different bases have different light reflectivities. 4. The pattern verification method according to claim 1, wherein the different base is a base having a step between one base. 5. The method according to claim 1, wherein the third step generates a different model according to the underlying layer, and the fourth step uses a model corresponding to the underlying layer of the optical simulation target layer. The pattern verification method according to any one of claims 1 to 4. 6. The pattern verification method according to claim 1, wherein in the fourth step, a light intensity pattern is formed by further performing a proximity effect correction. 7. The light intensity pattern formed by applying the model in the fourth step can be selected from a plurality of models having different amounts of the correction amount to be applied to a boundary portion having a different background. When determining the correction amount of the proximity effect correction from, select a model that minimizes the proximity effect correction, and when the light intensity pattern formed by applying the model is used for verification of the mask pattern, the correction amount is maximized. The pattern verification method according to claim 1, wherein a model is selected. 8. An information processing system having an information processing device connectable to a network, wherein the information processing device responds to a predetermined request via a network by applying test patterns to different bases on a semiconductor substrate. A process of transmitting predetermined pattern data for forming to the request source via the network, a process of obtaining a light intensity pattern by an optical simulation using the pattern data, and an exposure mask by the transmitted pattern data. Processing to generate a model that defines a correction amount that correlates to a dimensional difference of the light intensity pattern with respect to a test pattern on a test wafer manufactured by the requestor using the request source, characterized in that: Data processing system. 9. An information processing system having an information processing device connectable to a network, wherein the information processing device uses predetermined pattern data for forming test patterns on different bases on a semiconductor substrate. A process of obtaining a light intensity pattern by optical simulation; and a process of generating a model that defines a correction amount correlated to a dimensional difference of the light intensity pattern with respect to a test pattern on a test wafer manufactured using an exposure mask based on the pattern data. And a process of transmitting the generated model data to the test wafer manufacturer via the network. 10. An information processing system having an information processing device connectable to a network, wherein the information processing device uses an optical system using predetermined pattern data for forming test patterns on different bases on a semiconductor substrate. A process of obtaining a light intensity pattern by simulation, and transmitting predetermined pattern data for forming a test pattern on a different base on a semiconductor substrate to the request source via the network in response to a predetermined request via the network And a process of generating a model that defines a correction amount that correlates to a dimensional difference of the light intensity pattern with respect to a test pattern on a test wafer manufactured by the requester using an exposure mask based on the transmitted pattern data. The generated model data to the request source via a network Data processing system for the processing of signals to, characterized in that comprising been possible. 11. The data processing system according to claim 8, wherein the model is different depending on a difference in background. 12. The base according to claim 8, wherein the different bases have different etching rates from each other.
11. The data processing system according to any one of claims 10 to 10. 13. The apparatus according to claim 8, wherein the different bases have different light reflectances.
Data processing system according to the item. 14. The data processing system according to claim 8, wherein the different base is a base having a step between itself and one base. 15. An information processing system having a first information processing device and a second information processing device connectable to a network, wherein the first information processing device forms a test pattern on different bases on a semiconductor substrate. A process of obtaining a light intensity pattern by optical simulation using predetermined pattern data, and a correction correlating with a dimensional difference of the light intensity pattern with respect to a test pattern on a test wafer manufactured using an exposure mask based on the pattern data. A process of generating a model that defines an amount; and a process of transmitting the generated model to a manufacturer of the test wafer via the network, wherein the second information processing device is configured to The layout of the model and the semiconductor integrated circuit from the manufacturer of the test wafer. Receiving the pattern data, generating a light intensity pattern by applying the model to an optical simulation using the received layout design pattern data, and generating mask pattern data evaluated using the generated light intensity pattern. A data processing system for transmitting the data to the test wafer manufacturer via the network. 16. The data processing system according to claim 15, wherein said second information processing apparatus generates said light intensity pattern by further performing proximity effect correction. 17. The second information processing apparatus can select, as the model to be applied at a boundary portion having a different background, from a plurality of types in which the magnitude of a correction amount correlated to the dimensional difference is different. When determining the correction amount of the proximity effect correction from the light intensity pattern formed by applying, a model that minimizes the proximity effect correction is selected, and the light intensity pattern formed by applying the model is used for verification of the mask pattern. 16. The data processing system according to claim 15, wherein a correction model that maximizes a correction amount correlated with the dimensional difference is selected.