JP2002175064A - Liquid crystal display and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the response time of a liquid crystal and the scanning time of a scanning line, when color display is conducted by a field sequential system. SOLUTION: (1) The signals of signal lines are written, in the order starting from the pixel TFT of a pixel having a long liquid crystal response time; (2) the signal of a signal line is written to a pixel TFT which displays the same gradation among pixel TFTs connected to one signal line; and the (3) the signal of a signal line is written to pixel TFTs displaying the same or approximate gradations among pixel TFTs connected to one signal line at the same time. Then, a regular signal voltage is applied to the pixel electrodes of the pixel TFTs displaying the approximate gradations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device and a driving method thereof. A liquid crystal display device displays light and dark by utilizing the fact that the polarization state, scattering state, or wavelength characteristics of light passing through the liquid crystal layer is changed by the voltage applied to the liquid crystal layer held between the substrates. It is.

In this specification, a thin film transistor (T
FT) indicates a semiconductor element having a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

[0003]

2. Description of the Related Art Liquid crystal display devices are widely used in portable applications and personal computers because of their light weight and low power consumption.

In a liquid crystal display, three primary colors, red,
A field sequential system in which green and blue light sources are sequentially turned on to perform color display has attracted attention. Since the field sequential method does not require a color filter, high definition display is expected.

As a field sequential system, there has been proposed a system in which a light source is sequentially turned on while changing the emission color (Monthly FPD Intelligence Press Journal 1999.2, pp. 66-69). In this method, when the light emission color of the light source is switched, it is necessary to set the entire screen to a black level to prevent color mixture of the light source in each pixel.

As a field sequential system, there has been proposed a system in which a light source is turned on after a response of a liquid crystal is completed in a screen (edited by Shunsuke Kobayashi, Color Liquid Crystal Display, Sangyo Tosho Nihon p127). This method is
Since the light source lights intermittently, when the light source is off,
Perfect black can be achieved. For this reason, CRT (cathoderay
An impulse method, which is a driving method of a tube, can also be achieved in a liquid crystal display device, and is expected as a means for preventing an afterimage unique to a liquid crystal display device.

[0007]

Problems to be solved by the invention will be described below.

In this specification, a TFT provided in a pixel portion is called a pixel TFT.

Further, in this specification, the pixels S1 to S1
A signal line having an address of Sm, a scanning line having an address of G1 to Gn, and pixels arranged near an intersection of the signal line and the scanning line are provided. Each pixel has a pixel TFT. The pixel TFT has a gate electrode connected to a scanning line and a source electrode connected to a signal line. The address of each pixel is indicated by the address of the signal line to which the source electrode of the pixel TFT is connected and the address of the scanning line to which the gate electrode is connected. For example, if the pixel TFT is i
When connected to the signal line in the column and the scanning line in the j-th row, the address of the pixel having this pixel TFT is (i,
j).

A pixel electrode is provided in connection with the drain electrode of the pixel TFT, and there is a counter electrode facing the pixel electrode. Liquid crystal is sandwiched between the pixel electrode and the counter electrode via an alignment film, and the liquid crystal switches according to a potential difference between the pixel electrode and the counter electrode.

In the dot sequential driving, the time required from the selection of the first scanning line to the selection of the nth scanning line is referred to as a "scanning line scanning period". Further, in order to activate the semiconductor layer, a predetermined potential, for example, +8 V is applied to the scanning line.
Giving a potential of ~ + 11V is referred to as "selecting a scanning line". A period for selecting a scanning line is referred to as a “scanning line selection period”.

That is, the "scanning period of the scanning line" is the time required from the start of the selection of the first scanning line to the end of the selection of the nth scanning line. Further, "selecting a scanning line" means to apply a gate pulse to a pixel TFT connected to the scanning line to make the source and drain of the pixel TFT connected to the scanning line conductive. .
The scanning line selection period is a period for selecting one row of scanning lines, and the “scanning line scanning period” is obtained by multiplying the scanning line selection period by n times.

[0013] Selecting a signal line means applying a signal voltage to the signal line and applying a potential of the signal line to a pixel TFT connected to the signal line.

A period starting from applying a potential required for image display to the pixel electrode of the pixel TFT having the address of (1, 1) to forming one single-color image is referred to as a “sub-frame period”. . Further, a period from applying a potential necessary for image display to a pixel electrode of a pixel TFT having an address of (1, 1) to forming one color-displayed image is referred to as a “frame period”.

In the field sequential system, a frame period in which a color-displayed image is formed includes a sub-frame period for forming a red image, a sub-frame period for forming a blue image, and a sub-frame period for forming a green image. Period.

FIG. 7 shows a timing chart of the field sequential system in which the light source is intermittently turned on. In the field sequential system, the period (T) of one frame period is 16.6 msec, and the period (T / 3) of the sub-frame period is 5.5 msec.

In the dot sequential driving, one scanning line is selected, and a signal line is sequentially selected by a shift register of a source driver, so that a signal is applied to a pixel electrode of a pixel TFT connected to the selected scanning line. The potential of the line is applied. The sub-frame period includes a standby period 301 and a scanning line selection period 30
2, a liquid crystal response period 303 and a light source lighting period 304. The standby period is a period from the start of one frame period to the selection of the scanning line connected to the pixel TFT. The liquid crystal response period is a period in which the liquid crystal responds according to the potential of the pixel electrode. The scanning line selection period is set to the number of scanning lines n
The scanning period 308 of the scanning line is obtained by multiplying by.

A scanning line is selected during a scanning line selection period 302, and a potential of a signal line is sequentially applied to a pixel electrode of a pixel TFT connected to the scanning line in accordance with a desired gradation. In the liquid crystal response period 303, the optical response of the liquid crystal ends. During the light source lighting period 304, the light source is turned on intermittently, and the first emission color 30
5, the second emission color 306, and the third emission color 307 are sequentially
The light enters the liquid crystal display device. For example, red can be used as the first emission color, green can be used as the second emission color, and blue can be used as the third emission color. However, as described above, when the light source is intermittently turned on, the liquid crystal response period 303 of the pixel TFT connected to the first scanning line and the pixel TFT connected to the nth scanning line naturally increases. different. Therefore, when the response of the liquid crystal takes a long time, or when the scanning period 308 of the scanning line is used.
When the light source is long, if the light source is turned on after the response of the liquid crystal is completed, the lighting period 304 of the light source becomes short and the brightness decreases.

That is, in the field sequential system, one of the important factors is the response time of the liquid crystal. The quicker the response time of the liquid crystal, the longer the lighting period of the light source and the brighter the display.

Further, in the field sequential system, an important factor is a scanning period of a scanning line. Assuming that the number of scanning lines is 1 to n, if the scanning period becomes longer, the time from applying the potential of the signal line to the pixel electrode to turning on the light source becomes shorter as the scanning line approaches the n-th line. The light source is turned on before the liquid crystal has responded. Since the gradation level is determined by the integrated value of the brightness of the liquid crystal when the light source is on, if the light source is turned on before the liquid crystal has responded, the gradation level when displaying the screen changes. I will. Conversely, if the light source is turned on after the liquid crystal responds, the lighting period of the light source is shortened and the display becomes dark.

XGA (1024 horizontal pixels) having a large number of scanning lines
In a liquid crystal display device of PXGA (1280 pixels × 1024 pixels) and SXGA (pixels × 768 pixels), the ratio of the scanning period of the scanning line to the sub-frame period cannot be ignored. SX
When performing dot sequential driving in a GA liquid crystal display device,
Write time of signal to one pixel is 0.75 to 1.5 ns
ec, the scanning period of the scanning line was estimated to be 1 to 2 msec. Therefore, the subframe period (5.5 mse
Excluding the scanning period of the scanning line from c), 3.5 to 4.5 m
Only the time of sec is left, and when the liquid crystal is made to respond until the desired brightness is exhibited at this time and then the light source is turned on, the lighting time of the light source becomes considerably short, and it becomes difficult to display brightly.

In the present specification, it is an object of the present invention to drive a liquid crystal display device by a field sequential method to end the optical response of the liquid crystal more quickly. Another object is to shorten the scanning period of the scanning line and reduce the ratio of the standby period 301 to the subframe period.

That is, in this specification, in the field sequential system, the sum of the standby period 301 and the liquid crystal response period 303 is shortened, and the lighting period 304 of the light source is lengthened,
An object is to provide a bright display.

[0024]

According to the present invention, when a pixel electrode having a potential of a first signal voltage in a first sub-frame period has a potential of a second signal voltage in a second sub-frame period, the present invention relates to The response time of the liquid crystal when the voltage value changes from the first signal voltage to the second signal voltage is calculated, and the pixel electrodes of the pixels are sequentially arranged in order from the pixel having the longer liquid crystal response time calculated in the second sub-frame period. And a potential of the second signal voltage.

According to the present invention, a first means for storing the potential of a first signal voltage applied to a pixel electrode in a first sub-frame period in a circuit configuration thereof, and a first means for applying a potential to a pixel electrode in a second sub-frame period A second means for storing the potential of the second signal voltage; and a third means for calculating a response time of the liquid crystal when the voltage value changes from the first signal voltage to the second signal voltage.
Means, and in the order of the pixels of the calculated response time of the liquid crystal,
Fourth means for applying a second signal voltage to the pixel electrode of the pixel.

In the field sequential system, a sub-frame period is a period for forming a monochromatic image, and a frame period is a period for forming a colorized image by continuously combining three sub-frame periods. . The above configuration can be applied to this field sequential system. Further, by substituting the above-described sub-frame period with a frame period, the present invention is not limited to the field sequential method, and can be widely applied to a liquid crystal display device and a driving method thereof.

In the dot sequential driving, pixels are sequentially selected from the pixel electrode connected to the pixel TFT connected to the first matrix scanning line to the pixel having the pixel TFT connected to the nth scanning line. For this reason, if the response time of the liquid crystal in the pixel connected to the n-th scanning line is long, the liquid crystal may not respond completely until the light source is turned on in the field sequential method. However, according to the present invention, the image changes from the first sub-frame period to the second sub-frame period, and when the liquid crystal responds, the pixels that take the response time of the liquid crystal are preferentially selected. In the field sequential timing chart of FIG. 7, the standby period 301 is shortened for a pixel having a long liquid crystal response period 303, and the sum of the standby period 301 and the liquid crystal response period 303 can be shortened. That is, the lighting period 304 of the light source can be lengthened,
Bright display becomes possible.

Further, according to the present invention, the pixel electrodes of a plurality of pixels connected to the same signal line and displaying the same gradation are simultaneously
It is characterized in that the same signal voltage potential is applied. By simultaneously selecting a plurality of pixels, the scanning time of a scanning line can be reduced.

Further, according to the present invention, a first pixel TFT connected to a first pixel TFT connected to a signal line and a first scanning line is provided.
Pixel electrode, and a second electrode connected to the signal line and the second scanning line.
And a second pixel electrode provided in connection with the pixel TFT.

Then, the signal line and the second scanning line are selected, and the difference between the absolute value of the second pixel electrode and the first signal voltage is 0 V.
A second step of applying a potential of a second signal voltage larger than 0.5V.

As described above, in the first stage, the first pixel electrode is connected to the second pixel electrode connected to the drain electrode of the second pixel TFT.
The liquid crystal is made to respond in advance by giving the potential of the signal voltage. The second pixel electrode is a pixel electrode that displays a gradation similar to that of the first pixel electrode. Approximate gray scale is defined as 0 V relative to the absolute value of the voltage applied to the first pixel electrode.
It means a gray scale displayed by an absolute value of a voltage larger than 0.5 V. Then, in the second stage, a second signal voltage is applied to the second pixel electrode to cause the liquid crystal to respond so as to display a normal gradation. By causing the liquid crystal to respond in advance in this way, it is possible to reduce the response time required for responding to the gradation of the display image when the potential of the second signal voltage is applied to the second pixel electrode.

Of course, in order to prevent the seizure of the liquid crystal,
At the same time, the first pixel TFT and the second pixel
May be a pixel TFT to which a voltage having the same polarity is to be written in advance.

Each of the inventions described above can be widely used as a liquid crystal display device and a driving method thereof, but is particularly effective in a field sequential system in which a light source is intermittently turned on. Since the light source is turned on intermittently, even if the order of writing the signal voltage to the pixel TFT is random, the light source is not turned on while the signal voltage is being written to the pixel TFT, so this random writing is not visible to the user. That's why.

If the above inventions can be used in combination, the invention can be widely applied not only to the field sequential system but also to a known liquid crystal driving system.

[0035]

[Embodiment 1] The circuit configuration of the present invention will be described with reference to FIG. FIG. 1 shows a pixel and a drive circuit of the present embodiment. FIG. 1 shows that in a pixel portion having pixels arranged in a matrix in m columns × n rows, addresses of pixels arranged in an i-th column and a j-th row are represented by (i,
j) (i is an integer of 1 or more and n or less, j is an integer of 1 or more and m or less).

One frame period includes a first sub-frame period to a third sub-frame period. The video signal 130 in the first to third sub-frame periods and the address of the pixel to which the video signal is input are input to the first means or the second means in accordance with the designation of the switching circuit 131.

The video signal 130 may be an analog signal or a digital signal. However, in order to store the video signal with high accuracy, if the video signal 130 is an analog signal, an analog-to-digital converter (AD converter) must be provided before the video signal is input to the first means or the second means. It may be converted to a digital signal by using this.

There is a first means for storing the potential of the first signal voltage applied to the pixel electrode during the first sub-frame period. The first means is changed from its function to the first storage means 101.
Called. In addition, there is a second means for storing the potential of the second signal voltage applied to the pixel electrode during the second sub-frame period. The second means is changed from its function to the second storage means 1
02.

Then, in the same pixel TFT, the first
There is a third means for calculating the response time of the liquid crystal when the voltage value changes from the first signal voltage to the second signal voltage. The third means is referred to as a comparison operation means 103 because of its function. The calculation of the response time of the liquid crystal is based on the rotational viscosity coefficient, elastic constant,
The theoretical value of the response time may be calculated from physical constants such as dielectric anisotropy. Alternatively, the relationship between the response time of the liquid crystal and the drive voltage may be input to the comparison operation means in advance, and the data may be referred to. Then, the order in which the signal of the signal line is written to the pixel TFT in the second sub-frame period is determined according to the calculated response time of the liquid crystal.

First, the response time of the liquid crystal when the signal voltage changes from the first signal voltage to the second signal voltage is calculated. The response time of the liquid crystal when the calculation is performed in all the pixels is the longest in the pixel of the address of (2, 2), and the response time of (2, 1), (1, 1), and (1, 2) It is assumed that the response time becomes shorter in the order of the pixels. That is, it is assumed that the response time of the liquid crystal when the pixel at the address (1, 2) of the four pixels changes the signal voltage from the first signal voltage to the second signal voltage is the shortest. In this case, when displaying an image in the second sub-frame period, the order of writing the signal of the signal line to the pixel TFT is (2, 2), (2,
1), (1, 1) and (1, 2) in this order.
That is, the signal of the signal line is written in the second sub-frame period in order from the pixel TFT of the pixel having the longer response time of the liquid crystal. For convenience, the description has been made with four pixels. However, the same applies to n × m pixels. When the signal voltage changes from the first signal voltage to the second signal voltage,
A signal of a signal line is written in order from a pixel TFT of a pixel having a long response time of liquid crystal. When the response time of the liquid crystal is the same in a plurality of pixels, the signal of the signal line is written to the pixel TFT in order of approaching the pixels in order to reduce the load on the driving circuit.

Then, during the first sub-frame period,
The order in which the signal of the signal line is written to the pixel TFT in the second sub-frame period is stored in the comparison operation data storage unit 104.

Then, there is a fourth means for applying a second signal voltage to the pixel electrode of the pixel in the order of the pixels having the longest calculated response time of the liquid crystal. In the present embodiment, the fourth means is an X address write control means 110 having an X address decoder 106, a video signal output means 108 connected to the X address decoder, a Y address decoder 105,
Level shifter 107 connected to Y address decoder
And a Y address writing control means 109 having

Among the fourth means, the X-address writing control means 110 having the X-address decoder 106 and the video signal output means 108 is the comparison operation data storage means 1
There is a function of selecting a signal line connected to the pixel TFT based on the X address data output from the pixel 04. Also,
The Y address writing control unit 109 having the Y address decoder 105 and the level shifter 107 has a function of selecting a scanning line connected to the pixel TFT based on the Y address data output from the comparison operation data storage unit 104.

Based on the Y address data output from the comparison operation data storage means 104, the address of the scanning line of the pixel TFT to which the signal of the signal line is written is designated by the Y address decoder 105. SXGA (1280 horizontal)
In the case of the number of pixels of (× 1024), if the number of input terminals of the Y address decoder is set to 10 in accordance with the number of pixels, 2 ¹⁰ scanning lines can be arbitrarily selected. An output pulse is output from an output terminal having a Y address designated by the Y address data among output terminals of the Y address decoder. Then, the voltage of the output pulse is amplified by the level shifter 107, and a gate pulse is output to the scanning line having the designated Y address.

The X address decoder 106 specifies a signal line for applying a signal voltage potential. SXGA
When the number of pixels is (1280 horizontal × 1024 vertical), the number of input terminals of the X address decoder may be 11 in accordance with the number of pixels. An output pulse is output from the output terminal of the X address specified by the X address decoder 106 and input to the video signal output means 108. Then, a video signal (signal voltage) is input to the signal line of the designated X address, and a signal voltage is applied to the signal line. With respect to the video signal 119, the order in which the video signal is written to the pixel TFT is determined by an external circuit (comparison operation data storage unit 104), and is input to the video signal output unit 108.

If the video signal input to the video signal output means is a digital signal, a digital-to-analog converter (DA converter) is built in the video signal output means and converted to an analog signal.

Thus, the comparison operation data storage means 104
The signals of the signal lines are sequentially written to the pixel TFTs 118 in accordance with the order stored in the step (b) to form an image in the second sub-frame period.

The operation of the circuit will be described with reference to FIG. By combining the images displayed in the first to third sub-frame periods, a color-displayed image is displayed in the first frame period 916.
In the preparation period 912, first, the address of the pixel TFT and the pixel TF thereof in the first subframe period are stored in the first storage means.
First period 9 for storing first signal voltage to be written to T
00. Next, there is a second period 901 for calculating the response time of the liquid crystal in each pixel when the image of the first sub-frame period is formed by the comparison operation means. Finally, there is a third period 902 during which the data of the comparison operation means is moved to the comparison operation data storage means.

In the first sub-frame period 913, there is a period 903 in which a signal of a signal line is written to the pixel TFT. Next, there is a liquid crystal response period 904 in which the liquid crystal responds according to the written first signal voltage. Then, there is a lighting period 905 of the light source where the light source is turned on. The first light emission color emitted by the light source in the first sub-frame period can be, for example, red among the three primary colors of the additive color mixture.

In the first sub-frame period 913,
In parallel, in order to form an image in the second sub-frame period, the order in which the second signal voltage is written to the pixel TFT is determined. Since the first storage means has already stored the first signal voltage of the pixel at each of the X address and the Y address in the first subframe period, the fourth period 90
At 6, the second signal voltage in the pixel at the X address and the Y address in the second sub-frame period is stored in the second storage means. Next, in the fifth period 907, the comparison operation means calculates the response time of the liquid crystal when the signal voltage changes from the first signal voltage to the second signal voltage, and selects a pixel from the calculation result. Determine the order to do. Then, in the sixth period 908, the data of the comparison operation means is moved to the comparison operation data storage means.

Next, in the second sub-frame period 914, the pixel data of the comparison operation data storage means is written to the pixel. The second sub-frame period includes a pixel data writing period 909, a liquid crystal response period 910, and a period 911 during which a light source is turned on. The second emission color emitted by the light source can be, for example, green.

An image in the third sub-frame period is formed by the circuit operation according to the second sub-frame period. In the third sub-frame period 915, the third light emission of the light source is performed.
Can be, for example, blue. Thus, an image to be displayed in color in the first frame period is formed. By repeatedly performing the above operations, a moving image display made of a colorized image can be displayed.

That is, with reference to the timing chart of the field sequential system shown in FIG. 7, according to the present invention, a pixel having a long response period 303 of the liquid crystal is placed in the standby period 3
01 can be shortened, so that the waiting period 301
And the liquid crystal response period 303 can be shortened.
Thereby, the lighting period 304 of the light source can be lengthened. In addition, since the present embodiment is used in combination with the field sequential color display method in which the light source is intermittently lit, the light source remains in the period in which the liquid crystal responds even if the order of selecting pixels is random. This random writing does not need to be recognized by the user because of non-lighting.

FIG. 3 shows the Y address write control means 10.
9 shows a timing chart. A drive circuit having a level shifter and a Y address decoder is referred to as a Y address write control means. The Y address writing control means is a means for selecting a scanning line connected to the pixel TFT.

The timing chart of the Y address writing control means will be described. First, a plurality of Y address data 111 are input to the input terminal of the Y address decoder.
For example, if there are 1024 scanning lines,
There are ten pieces of X address data for selecting any one of the scanning lines, and each piece of X address data has information of “0” or “1”. Then, an output pulse 112 is output from the output terminal of the Y address decoder having the Y address specified by the Y address data. The voltage value of the output pulse 112 is amplified by the level shifter and converted into a gate pulse 117. Then, the gate pulse is output to the scanning line of the designated Y address. Thus, the pixel T of the pixel which takes a long response time of the liquid crystal
The scanning line connected to the FT is preferentially selected. In the first sub-frame period, output pulses 112 to 116 are sequentially output to the designated Y address in accordance with the order of the pixel TFTs for writing the first signal voltage. The output pulse is converted into gate pulses 117 to 121 by the shift register, and a scanning line is selected. In the second sub-frame period 133, as in the first sub-frame period 132, the output pulse is converted into a gate pulse, and first, the scanning line connected to the pixel TFT of the pixel that requires a long liquid crystal response time is selected. Is done. Thereafter, image formation is repeated at a timing according to this.

For example, VGA (640 horizontal pixels × 480 vertical pixels)
Pixel), the pixels having the slower response time of the liquid crystal are (1, 5), (6, 2), (150, 4),.
(60, 3) and (200, 300). That is, the response time of the liquid crystal is the longest in the pixels (1, 5),
It is assumed that the response time of the liquid crystal is the shortest in the (200, 300) pixel. In this case, the gate pulse 117 is output to the scanning line having the address of G5, the gate pulse 118 is output to the scanning line having the address of G2, and the gate pulse 119 is output to the scanning line having the address of G4. Is done. Then, the gate pulse 120 is output to the scanning line having the address of G3, and finally the gate pulse 121 is output to the scanning line having the address of G300.

FIG. 4 shows the X address write control means 11.
0 shows a timing chart. The driving circuit including the X address decoder and the video signal output circuit is referred to as X address writing control means. The X address writing control means is a means for selecting a signal line connected to the pixel TFT.

The timing chart of the X address write control means will be described. First, X address data 122 indicating the order of selecting signal lines is input to the input terminal of the X address decoder. For example, when there are 1240 signal lines, there are 11 Y address data in order to select any one of the 1240 signal lines, and each Y address data is information of “0” or “1”. Having.
Then, the output pulses 123 to 127 are output from the output terminal of the X address specified by the X address data 122 among the output terminals of the X address decoder.
The video signal 129 is input to the signal line of the designated X address, and a signal voltage potential is applied to the signal line. In the second sub-frame period, similarly to the first sub-frame period, the signal line connected to the pixel TFT of the pixel having the longest liquid crystal response time is preferentially selected. Thereafter, image formation is repeated at a timing according to this.

For example, VGA (640 horizontal pixels × 480 vertical pixels)
Pixel), the pixels having the slower response time of the liquid crystal are (1, 5), (6, 2), (150, 4),.
(60, 3) and (200, 300). That is, the response time of the liquid crystal is the longest in the pixels (1, 5),
It is assumed that the response time of the liquid crystal is the shortest in the (200, 300) pixel. In this case, after the output pulse 123 is output on the signal line having the address of S1, the output pulse 124 is output on the signal line having the address of S6.
The output pulse 125 is output on the signal line having the address of. Then, the output pulse 126 is output to the signal line having the address of S60, and finally, the output pulse 127 is output to the signal line having the address of S200.

The pulse widths of the output pulses output from the X address decoder and the Y address decoder are the same. In a pixel portion having pixels arranged in a matrix in m columns × n rows, the number of output pulses output from the X address decoder and the Y address decoder is m × n, and the pixels having the longest response time are in order. Data is written for each pixel.

[Embodiment 2] FIG. 5 shows an embodiment of the present invention. 5 is characterized by a plurality of address decoders, namely, a first Y address decoder and a second Y address decoder.
Is provided. FIG.
Describes the address of the pixel arranged in the i-th column and the j-th row as (i, j) (i is an integer of 1 to n, and j is an integer of 1 to m).

First, the data of the video signal (signal voltage) 200 at the X address and the Y address in the first sub-frame period is stored in the storage means 201. The Y address indicates the address of the signal line. The X address indicates the address of the scanning line.

That is, the video signal is stored in the storage means 201,
The address of the pixel to which the video signal is input is stored.

The first means for detecting a pixel connected to the same signal line and displaying the same gray scale is provided by a plurality of pixel TFTs 210 connected to the signal line of the same X address and displaying the same signal voltage. To the pixel TFT of the pixel
At the same time, a program is written to write the signal of the signal line. In the present embodiment, the first unit is referred to as a comparison unit 202 because of its function. For example, in a first frame period, a pixel TFT connected to a signal line having an X address of 1
When the pixels having Y addresses of 1, 10 and n perform display with the same signal voltage, the pixel TFTs of the addresses (1, 1), (1, 10) and (1, n) are detected by the comparing means. Is done. In the present embodiment, to simplify the description, the same signal voltage is simultaneously written to a maximum of two pixel TFTs. Also, the pixel TFT at the address of (1, 1)
At the same time, the pixel TFT to which the signal of the signal line is written is a pixel TFT of the address (1, n) having the larger Y address among the remaining two pixels ((1, 10) and (1, n)).
And In the dot sequential driving, a pixel TFT having a larger Y address value has a longer time for writing a signal of a signal line to the pixel TFT, and a standby time 301 in FIG. 7 tends to be longer in a field sequential method.
This is because it is better to preferentially select a pixel TFT having a large Y address value. Of course, not only can the signals of the signal lines be simultaneously written into the two pixel TFTs, but also the three pixels T
The signal of the signal line can be simultaneously written to the FT by changing the design of the driver circuit.

Next, the order in which the signals of the signal lines are written to the pixels, determined by the comparing means 202, is stored in the comparison data storing means 203.

There is a second means for simultaneously applying a signal voltage potential to the pixel electrodes of a plurality of pixel TFTs. The second means is
In the present embodiment, the X address decoder 204, the video signal output means 205, the first Y address decoder 2
06, a second Y address decoder 208, a first level shifter 207 and a second level shifter 209.

The X address decoder 204 is based on the X address data output from the comparison data storage means.
This is a means for selecting the address of the signal line. The first Y address decoder 206 and the second Y address decoder 208 are means for selecting a scan line address based on the Y address data output from the comparison data storage means.

The X address decoder 204 outputs an output pulse to the designated X address output terminal of the X address decoder based on the X address data output from the comparison data storage means 203. Although not shown, in the case of the liquid crystal display means which is the number of pixels of SXGA, X
The address decoder has 11 input terminals and 1280 output terminals. The X address of the signal line which gives the potential of the signal voltage is designated by the X address decoder.
Here, 1 is designated as the X address.

The video signal output means 205 supplies a video signal to the signal line of the X address specified by the X address data. The order of the video signal 211 is determined by an external circuit (comparison data storage means 203), and is input to the video signal output means in accordance with the order.

The first Y address decoder 206 outputs an output pulse from the output terminal of the designated Y address based on the Y address data output from the comparison data storage means 203. Although not shown, in the case of a liquid crystal display unit having the number of pixels of SXGA, the Y address decoder has ten input terminals and 1024 output terminals. It is assumed that an output pulse is output from an output terminal of the first Y address decoder whose Y address is 1. It is assumed that an output pulse is output from an output terminal of the second Y address decoder 208 whose Y address is n.

The first level shifter 207 connected to the first Y address decoder and the second level shifter 209 connected to the second Y address decoder amplify the voltage of the output pulse to generate a gate pulse having a gate voltage. To

By selecting the scanning line and the signal line of the address specified by the first Y address decoder, the second Y address decoder and the X address decoder, (1, 1) and ( 1,
The pixel TFT having the address n) is selected, and the signal of the signal line is written. Thus, the address of the pixel TFT is sequentially designated, and the signal of the signal line is written to the pixel TFT. In the present embodiment, the signal of the signal line can be written to a maximum of two pixel TFTs at the same time, so that the total time for providing the signal of the signal line to the pixel TFT, that is, the scanning time of the scanning line can be reduced.

The operation of the circuit will be described with reference to FIG. In the preparation period 912, there is a first period 900 in which signal voltage data at the X address and the Y address in the first frame period is input to the storage means. Then, in the comparison means, there is a second period 901 in which the pixel TFTs to which the same signal voltage is written are detected in the pixel TFTs connected to the same signal line, and the Y addresses of those pixel TFTs are confirmed. The third period 9 in which the order in which the signal of the signal line is applied to the pixel TFT determined by the comparing means is written in the comparison data storage means
02.

In the first sub-frame period, the signal of the signal line is applied to the pixel TF in order to display an image on the pixel TFT.
There is a period 903 for writing to T. Next, a liquid crystal response period 90 in which the liquid crystal responds according to the first signal voltage is written.
There are four. Then, there is a period 905 during which the light source is turned on.
The first light emission color emitted by the light source in the first sub-frame period can be, for example, red among the three primary colors of the additive color mixture.

In the first sub-frame period, a fourth period 90 for inputting signal voltage data at the X address and the Y address in the second sub-frame period in parallel.
6. A fifth period 907 in which the address of the pixel TFT to which the signal of the signal line is simultaneously written in the second sub-frame period is detected by the comparing means. Write to the sixth
There is a period 908.

Thereafter, in the same manner, in the second sub-frame period, a monochrome image is formed by turning on the light source, starting from the operation of supplying a signal of the signal line to the pixel TFT. The second emission color emitted by the light source can be green. In order to form an image of the third sub-frame period in parallel in the second sub-frame period,
The order in which signal voltages are written to the pixel TFTs is determined.
There is an operation of the circuit corresponding to the period from the period to the sixth period. Then, a monochrome image is displayed during the lighting period of the light source in the third sub-frame period. The third emission color emitted by the light source can be blue. Thus, a color image is formed in the first frame period. Or later,
The same operation is sequentially repeated to display a moving image.

By simultaneously writing a signal of a signal line to a plurality of pixel TFTs connected to the same signal line and displaying the same gradation, a moving image can be displayed by a driving method in which the scanning time of the scanning line is reduced. It is formed.

In FIG. 5, since the first Y address decoder and the second Y address decoder are provided in the driving circuit connected to both ends of the scanning line, pixels having the same signal voltage potential at the same time are provided. The maximum number was two. However, embodiments of the present invention are not limited to this.
By changing the circuit configuration, three or more pixel TFTs that apply the same signal voltage can be selected from the pixel TFTs connected to the same signal line. In this case, the first Y address decoder 20 in FIG.
6. Instead of providing the second Y address decoder 208, a circuit capable of selecting a plurality of scanning lines (referred to as a scanning line selection circuit) is provided between the comparison data storage means 203 and the first level shifter 207. , Scanning line selection circuit,
What is necessary is just to select three or more scanning lines simultaneously. In this case, the second level shifter 209 is not required.

According to the present embodiment, in the dot sequential driving, it is possible to reduce the scanning time of the scanning line required to apply the potential of the predetermined signal voltage to the pixel. For example, FIG.
Explaining with reference to the timing chart of FIG.
01 and the liquid crystal response period 303 can be reduced. Further, compared with the first embodiment, the comparison operation means 102 for calculating the response time in FIG. 1 is not required, so that the processing performed by the circuit is simplified and the circuit configuration is simplified.

A timing chart of the circuit of this embodiment will be described with reference to FIG. The X address decoder and the video signal output means are collectively referred to as X address write control means in this specification. The X address writing control means is a means for selecting a scanning line connected to the pixel TFT.
The X address data 122 has information of “0” or “1”, respectively. When the number of scanning lines is 1024, ten X address data are simultaneously input to the X address decoder. Based on the X address data 122, an output pulse 123 is output from the output terminal of the designated X address among the output terminals of the X address decoder. In the present embodiment, unlike the first embodiment, basically, output pulses may be sequentially output from the first column to the m-th column of the signal line. At the same time that the output pulse 123 is output,
The video signal pulse 129 is output to the signal line of the designated X address. By the above operation, a signal is supplied to the signal line of the X address specified by the X address data.

The first Y address decoder and the first level shifter are collectively referred to as first Y address write control means in this specification. The second Y address decoder and the second level shifter are collectively referred to as a second Y address write control unit in this specification. The first Y address writing control means and the second Y address writing control means are means for selecting a signal line connected to the pixel TFT. The point that the voltage of the output pulse output from the first Y address decoder and the second Y address decoder is amplified by the first level shifter or the second level shifter is the same as that of the first embodiment. Next, the operation of the first Y address decoder and the second Y address decoder will be described.

The Y address data has information of “0” or “1”. Based on the Y address data, the address of the terminal of the Y address decoder from which the output pulse is output is determined. For example, if there are 1240 signal lines, this 1
To select any one of the 240 signal lines, Y
There are 11 pieces of address data, and each Y address data has information of “0” or “1”.

In the first sub-frame period, based on the Y address data 212, an output pulse 213 is output from the specified Y address output terminal of the first Y address decoder. In this embodiment, first, an output pulse is output from the output terminal whose Y address is 1 in order to select the first scanning line of the first matrix. The output pulse 21 output from the first Y address decoder 223
When the number of scanning lines is n rows and the number of signal lines is m columns, the total number of 3 to 217 becomes mxn or less from the circuit operation.

Then, a second pixel T to which a signal on the same signal line as the first pixel TFT connected to the first scanning line is written.
If there is an FT, the second pixel TFT connected to the second
In order to select the Y address of the scanning line, an output pulse 218 is output from an output terminal of the second Y address decoder corresponding to the address of the second scanning line. Output pulse 21 output from second Y address decoder 224
8 to 220 are pixel TFTs connected to different scanning lines and are output only when there is a pixel TFT to which a signal of a signal line is simultaneously written.

Thereafter, similarly, when there are two pixel TFTs to which signals on the signal lines are simultaneously written, output pulses are simultaneously output from the first Y address decoder and the second Y address decoder to select a scanning line. .

The pulse widths of the output pulses output from the X address decoder, the first Y address decoder, and the second Y address decoder are the same.

According to the method of this embodiment, the time required to write a signal to all pixels can be reduced.

[Embodiment 3] An embodiment of the present invention will be described with reference to FIG. A feature of the present embodiment is that a first signal voltage is simultaneously written to a plurality of pixel TFTs connected to the same signal line, that is, a first pixel TFT and a second pixel TFT. The difference from the second embodiment is that the first signal voltage is applied to the second pixel TFT to make the liquid crystal respond in advance, and then the second signal voltage is further written. By causing the liquid crystal to respond twice, the response time of the liquid crystal after writing the second signal voltage to the second pixel TFT can be reduced. It is assumed that the difference between the absolute value of the first signal voltage and the absolute value of the second signal voltage is larger than 0V and smaller than 0.5V. Hereinafter, the approximate gradation refers to a gradation that can be displayed in a range where the difference between the first signal voltage and the second signal voltage applied to the liquid crystal is larger than 0 V and smaller than 0.5 V.

First, the video signal (signal voltage) 200 at the X address and the Y address in the first sub-frame period is stored in the storage means 201.

When the image of one screen is displayed by the comparing means 202, the first signal TFT of the plurality of pixel TFTs connected to the same signal line is supplied with the potential of the first signal voltage.
And a second pixel electrode for applying a potential of a second signal voltage having an absolute value greater than 0 V and smaller than 0.5 V to a first pixel TFT having a pixel electrode of Is detected. Then, a program is formed so that the potential of the first signal voltage is applied to the first pixel electrode and the second pixel electrode, and then the potential of the second signal voltage is applied to the second pixel electrode. Second pixel TF
T may be plural or singular depending on the image to be displayed.

In the driving method according to the present embodiment, as compared with the second embodiment, of the pixel TFTs connected to the signal lines, the first pixel T
Even if there is no pixel to write the same signal voltage as FT, the first pixel TF connected to the signal line and the first scanning line
When the first pixel having T and the second pixel having the second pixel TFT connected to the signal line and the second scan line display similar grayscale levels, the first pixel TFT
And writing a first signal voltage to the second pixel. In the present embodiment, in the first stage,
At the same time, the number of pixels to which signals on the same signal line are written is two at the maximum. In addition, in the dot sequential driving, the longer the pixel connected to the scanning line having the larger X address value, the longer the time for applying the potential of the predetermined signal voltage to the pixel, and the standby time 30 in FIG.
Since 1 tends to be longer, a pixel connected to a scanning line having a larger X address value is preferentially selected.

Next, as the second stage of the driving method of the present embodiment, the scanning lines are sequentially selected from the first scanning line to the second scanning line, and the signal of the signal line is written to the pixel. of course,
If two pixel TFTs connected to the same signal line show similar gradations while selecting the second scanning line from the first scanning line, the signal of the signal line is simultaneously written to these two pixel TFTs. You can do it.

Then, as a third step of the driving method of the present embodiment, the second pixel TFT to which the first signal voltage has been written
Then, the second signal voltage of the normal gradation level is written again. The difference between the second signal voltage and the absolute value of the first signal voltage is larger than 0V and smaller than 0.5V.

In this way, the order of writing the signals of the signal lines to the pixels is determined by the comparing means 202. That is, the comparing means is programmed so as to perform the first to third steps.

That is, the feature of the driving method of this embodiment is as follows.
The signal of the signal line is written in advance to the second pixel that displays a gradation level similar to that of the first pixel at the same time as the first pixel TFT so that the liquid crystal responds. As a result, the liquid crystal responds to the approximate gradation level until the second signal voltage is written to the second pixel TFT again. (Second
(Response time) until the liquid crystal responds to the gray scale determined by the signal voltage of the liquid crystal.

Next, the pixel T for writing the signal of the signal line, determined by the comparing means 202, is stored in the comparison data storing means 203.
The order of the FT is stored.

The address of the signal line is specified by the X address decoder 204, and the video signal output means 205
The video signal 211 is supplied to the X address of the designated signal line. The video signal is input to the video signal output means according to the order of the selected pixels.

Based on the output Y address data, the first Y address decoder 206
An output pulse is output to the output terminal of the address decoder. The first level shifter 207 amplifies the voltage value of the output pulse output from the first Y address decoder, and sets the first scanning line to the gate potential.

The second scanning line is set to the gate potential by the second Y address decoder 208 and the second level shifter 209.

Thus, the same signal voltage potential is simultaneously applied to the first pixel TFT connected to the signal line and the first scanning line and to the second pixel TFT connected to the signal line and the second scanning line. .

The operation of the circuit of this embodiment is almost the same as that described in the second embodiment with reference to FIG. The difference is that in the second period 901, the comparator detects the address of a pixel connected to the same signal line and displaying an approximate gradation when forming an image in the first sub-frame period. It is.

Of course, by changing the circuit configuration, it is also possible to simultaneously select three or more pixel TFTs connected to the same signal wiring and displaying the same or similar gradation levels.

According to the present embodiment, the liquid crystal of the pixel showing the approximate gradation level is caused to respond in advance,
In the timing chart of the field sequential system of FIG. 7, the sum of the response time 303 of the liquid crystal and the standby time 301 can be reduced.

This embodiment can be used in combination with Embodiments 1 and 2. A signal of a signal line can be preferentially written to a pixel TFT of a pixel which requires a response time, or a signal of a signal line can be simultaneously written to a pixel TFT of a pixel showing the same or similar gradation.

[0105]

[Embodiment 1] FIGS. 8 to 11 show an embodiment of the present invention.
This will be described with reference to FIG. Here, a method for simultaneously manufacturing a pixel TFT and a storage capacitor in a pixel portion and a TFT of a driver circuit provided in the periphery of a display region will be described in detail according to steps. The TFT of the drive circuit manufactured in this example is
The mobility of the semiconductor layer is high, which is suitable for high-speed writing of pixel data in a field sequential method.

First, as shown in FIG. 8A, a substrate 400 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is oxidized. A base film 401 including an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed. For example, a silicon oxynitride film 401a manufactured from SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method has a thickness of 10 to 200 nm.
(Preferably 50-100 nm) and Si
Silicon oxynitride hydride film 4 made of H ₄ and N ₂ O
01b is 50 to 200 nm (preferably 100 to 150 nm).
(nm). In this embodiment, the base film 401 is used.
Is shown as a two-layer structure, but it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

The island-shaped semiconductor films 402 to 406 are formed of a crystalline semiconductor film formed by using a semiconductor film having an amorphous structure by a laser crystallization method or a known thermal crystallization method. The thickness of the island-shaped semiconductor films 402 to 406 is 25 to 80 nm.
(Preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

To form a crystalline semiconductor film by the laser crystallization method, a pulse oscillation type or continuous emission type excimer laser _{, an} Ar laser, a Kr laser, a YAG laser, a YVO ₄ laser, a YLF laser, a YAlO ₃ laser, a glass A laser, a ruby laser, an alexandrite laser, and a Ti: sapphire laser are used.
In the case of using these lasers, a method in which laser light emitted from a laser oscillator is condensed into a linear or elliptical shape by an optical system and irradiated onto a semiconductor film is preferable. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 400 mJ / cm.
² (typically 200 to 300 mJ / cm ² ). Also, Y
When an AG laser is used, its second harmonic is used to set the pulse oscillation frequency to 1 to 10 kHz and the laser energy density to 300 to 600 mJ / cm ² (typically 350 to 5 mJ / cm ² ).
00mJ / cm ² ). And width 100-1000
A laser beam condensed linearly at μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is set to 80 to 98%.

In order to obtain a crystal having a large grain size during crystallization of the amorphous semiconductor film, a solid-state laser capable of continuous oscillation is used, and the second to fourth harmonics of the fundamental wave are applied. Is preferred. Typically, a second harmonic (532 nm) or a third harmonic of a Nd: YVO ₄ laser (fundamental wave 1064 nm) is used.
A harmonic (355 nm) is applied.

Further, a continuous oscillation YVO _{4 having} an output of 10 W is provided.
A laser beam emitted from a laser may be converted into a harmonic by a nonlinear optical element, or a method of emitting a harmonic by putting a YVO ₄ crystal and a nonlinear optical element in a resonator may be used. Preferably, the laser beam is shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the laser beam is irradiated on the object. The energy density at this time is 0.01 to 100
MW / cm ² about (preferably 0.1 to 10 MW / c
m ² ) is required. And 0.5-2000cm /
Irradiation is performed by moving the substrate relative to the laser beam at a speed of about s.

Next, a gate insulating film 407 covering the island-shaped semiconductor films 402 to 406 is formed. Gate insulating film 407
Uses a plasma CVD method or a sputtering method and has a thickness of 4
The insulating film containing silicon is formed to have a thickness of 0 to 150 nm. In this embodiment, a silicon oxynitride film with a thickness of 120 nm is formed. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) is used by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300 to
400 ° C., high frequency (13.56 MHz) power density 0.
It can be formed by discharging at 5 to 0.8 W / cm ² .
The silicon oxide film thus produced is
Good characteristics as a gate insulating film can be obtained by thermal annealing at 00 to 500 ° C.

Then, a first conductive film 408 and a second conductive film 409 for forming a gate electrode are formed over the gate insulating film 407. In the present embodiment, the first conductive film 40
8 is formed of TaN to a thickness of 50 to 100 nm, and the second conductive film 409 is formed of W to a thickness of 100 to 300 nm.

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, when using the sputtering method,
By using a W target having a purity of 99.9999% and forming a W film with sufficient care so as not to mix impurities from the gas phase during film formation, the resistivity is 9 to 20 μΩc.
m can be realized.

In this embodiment, the first conductive film 408 is used.
Is TaN and the second conductive film 409 is W, but each is an element selected from Ta, W, Ti, Mo, Al, and Cu.
Alternatively, it may be formed of an alloy material or a compound material containing the above element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a combination other than this embodiment, the first conductive film is formed of tantalum (Ta), the second conductive film is formed of W, and the first conductive film is formed of tantalum nitride (TaN). There is a combination in which the second conductive film is made of Al, the first conductive film is made of tantalum nitride (TaN), and the second conductive film is made of Cu.

Next, resist masks 410 to 41 are used.
5, and a first etching process for forming electrodes and wiring is performed. In this embodiment, the ICP (Inductively
An etching gas is mixed by using a coupled plasma (inductively coupled plasma) etching method, and plasma is generated by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa. 100 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. By appropriately selecting an etching gas, the W film and the TaN film are etched to the same extent.

Under the above-mentioned etching conditions, by making the shape of the mask made of resist suitable, the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes a taper shape with an angle of 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 417 to 422 (the first conductive layers 417 a to 422 a) including the first conductive layer and the second conductive layer are formed by the first etching process.
And second conductive layers 417b to 422b). 41
Reference numeral 6 denotes a gate insulating film, and the first shape conductive layers 417 to
The region not covered by 422 is etched by about 20 to 50 nm to form a thinned region.

Then, a first doping process is performed, and n
An impurity element for imparting a mold is added. (FIG. 8B) The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 ×
10 ^{13 to} 5 × 10 ¹⁴ / cm ² , and the acceleration voltage is 60 to 100
Performed as keV. 1 as an impurity element imparting n-type
An element belonging to Group V, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 417 to 420 serve as a mask for the impurity element imparting n-type, and the first impurity regions 423 to 426 are formed in a self-aligned manner. First impurity region 4
23 to 426 are doped with an impurity element imparting n-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

Next, a second etching process is performed as shown in FIG. Using an ICP etching method, a reactive gas is introduced into the chamber, a predetermined RF power (13.56 MHz) is supplied to the coil-type electrode, and plasma is generated. On the substrate side (sample stage), a lower RF (13.56 MHz)
z) Power is applied, and a lower self-bias voltage is applied than in the first etching process. The W film is anisotropically etched to obtain second shape conductive layers 427 to 432.

Further, as shown in FIG. 8C, a second doping process is performed. In this case, doping with an impurity element imparting n-type is performed under a condition of a higher acceleration voltage with a lower dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV and the dose is set to 1 × 10 ¹³ / cm ² , and a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor film in FIG. Form.
The doping is performed using the second shape conductive layers 427 to 430 as a mask for the impurity element,
The regions below 7a to 430a are also doped so that the impurity element is added. Thus, the first conductive layer 42
Second impurity regions 433-43 overlapping with 7a-430a
7 is formed. The impurity element imparting n-type is set to have a concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ in the second impurity region.

As shown in FIG. 9A, the gate insulating film 416
Is simultaneously etched to form the first conductive layer Ta.
Since N is etched and receded, third shape conductive layers 438 to 443 (first conductive layers 438a to 443a and second conductive layers 438b to 443b) are formed. Reference numeral 444 denotes a gate insulating film, which is a third shape conductive layer 438 to 443.
The region which is not covered with is further etched by about 20 to 50 nm to form a thinned area.

In FIG. 9A, a first conductive layer 438
a to 441a and third impurity regions 445 to 449
And a fourth impurity region 4 outside the third impurity region.
50 to 454 are formed. Thus, the concentration of the impurity element imparting n-type in the third impurity region and the fourth impurity region becomes substantially equal to the concentration of the impurity element imparting n-type in the second impurity region.

Then, as shown in FIG. 9B, the island-like semiconductor films 403 and 406 forming the p-channel TFT have fourth impurity regions 458 to 4 of a conductivity type opposite to the one conductivity type.
61 is formed. Using the conductive layers 439 and 441 of the third shape as masks for impurity elements, impurity regions are formed in a self-aligned manner. At this time, the entire surface of the island-shaped semiconductor films 402, 404, and 405 forming the n-channel TFT is covered with resist masks 455 to 457. Phosphorus is added to the impurity regions 458 to 461 at different concentrations, but the impurity concentration is set to 2 × 10 ²⁰ to 2 × in any of the regions by ion doping using diborane (B ₂ H ₆ ). It should be 10 ²¹ / cm ³ .

Through the above steps, an impurity region is formed in each island-like semiconductor film. Conductive layers (conductive layers forming gate electrodes) 438 to 441 overlapping with the island-shaped semiconductor film function as gate electrodes of the TFT. 442 functions as a source wiring, and 443 functions as a wiring in a driver circuit.

In order to control the conductivity type in this way, FIG.
As shown in (C), a step of activating the impurity element added to each of the island-shaped semiconductor films is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm.
The heat treatment is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere of ppm or less. In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. However, 438-4
When the wiring material used for 43 is weak to heat, it is preferable to activate after forming an interlayer insulating film (mainly composed of silicon) in order to protect the wiring and the like.

Further, a heat treatment is performed in an atmosphere containing 3 to 100% of hydrogen at 300 to 450 ° C. for 1 to 12 hours to hydrogenate the island-like semiconductor film. In this step, dangling bonds in the semiconductor film are terminated by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Then, as shown in FIG. 10, a first interlayer insulating film 472 is formed of a silicon oxynitride film with a thickness of 100 to 200 nm. A second layer made of an organic insulating material thereon;
An acrylic resin film or a polyimide resin film having a thickness of 1.8 μm is formed as the interlayer insulating film 473 of FIG. Next, an etching step for forming a contact hole is performed.

Next, a conductive metal film is formed by a sputtering method or a vacuum evaporation method. In this method, a Ti film is formed with a thickness of 50 to 150 nm, a contact is formed with a semiconductor film which forms a source region or a drain region of an island-shaped semiconductor film, and aluminum (Al) is formed on the Ti film by a thickness of 300 nm. ~ 40
It was formed to a thickness of 0 nm, and a Ti film or a titanium nitride (TiN) film was formed to a thickness of 100 to 200 nm to form a three-layer structure.

Then, a source wiring 474 for forming a contact with the source region of the island-shaped semiconductor film in the drive circuit portion.
To 476, and drain wirings 477 to 479 forming a contact with the drain region are formed.

In the pixel portion, the connection electrode 48
0, gate wiring 481, drain electrode 482, electrode 49
Form 2

The connection electrode 480 electrically connects the source wiring 483 and the first semiconductor film 484. Although not shown, the gate wiring 481 is electrically connected to a conductive layer 485 forming a gate electrode through a contact hole.
The drain electrode 482 is electrically connected to a drain region of the first semiconductor film 484. The electrode 492 is electrically connected to the second semiconductor film 493, and makes the second semiconductor film 493 function as an electrode of the storage capacitor 505.

After that, a transparent conductive film is formed on the entire surface, and a pixel electrode 491 is formed by patterning and etching using a photomask. Pixel electrode 491
Are formed on the second interlayer insulating film 473 and the pixel TFT
And a portion overlapping with the drain electrode 482 and the electrode 492 is provided to form a connection structure.

The material of the transparent conductive film is indium oxide (I
n ₂ O ₃ ) and indium tin oxide alloy (In ₂ O ₃ —S
nO ₂ ; ITO) or the like can be formed by a sputtering method, a vacuum evaporation method, or the like. The etching of such a material is performed using a hydrochloric acid-based solution. However, in particular, since etching of ITO easily generates residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used in order to improve the etching processability. Since the indium zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to ITO, it is possible to prevent a corrosion reaction with Al contacting the end face of the drain electrode 482. Similarly,
Zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to increase the transmittance and conductivity of visible light can be used.

Thus, an active matrix substrate corresponding to a transmission type liquid crystal display device can be completed.

As described above, the n-channel TFT 5
01, p-channel TFT 502, n-channel TFT
A driver circuit portion including the pixel circuit 503 and a pixel portion including the pixel TFT 504 and the storage capacitor 505 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 501 in the driver circuit portion includes a channel formation region 462, a third impurity region 445 (GOLD region) overlapping the conductive layer 438 forming a gate electrode, and a fourth impurity formed outside the gate electrode. The semiconductor device includes a region 450 (LDD region) and a first impurity region 423 functioning as a source region or a drain region.
The channel forming region 46 is formed in the p-channel TFT 502.
3. The semiconductor device includes a fifth impurity region 446 overlapping with the conductive layer 439 forming the gate electrode, and a sixth impurity region 451 functioning as a source or drain region. In the n-channel TFT 503, a channel formation region 464, a third impurity region 447 (GOLD region) overlapping with the conductive layer 440 forming a gate electrode, and a fourth impurity region 452 (LDD region) formed outside the gate electrode. And a first impurity region 425 functioning as a source region or a drain region.

The pixel TFT 504 in the pixel portion has a channel forming region 465, a third impurity region 448 (GOLD region) overlapping with the conductive layer 485 forming a gate electrode, and a fourth impurity region 453 formed outside the gate electrode. (LD
D region) and a first impurity region 426 functioning as a source region or a drain region. The semiconductor film 493 functioning as one electrode of the storage capacitor 505 is doped with an impurity element imparting p-type. A storage capacitor is formed by the conductive layer 485 forming the gate electrode and an insulating layer (the same layer as the gate insulating film) therebetween.

The top view of FIG. 11 is indicated by the dashed line AA ′ and the dashed line B−.
The cross section cut along B ′ corresponds to the cross section cut along chain lines AA ′ and BB ′ in FIG. 801 in FIG.
Reference numerals 805 denote contact holes.

An active matrix substrate of a reflection type liquid crystal display device can be manufactured by making the drain electrode of this embodiment a conductive film having reflectivity and functioning as a pixel electrode. .

[Embodiment 2] In this embodiment, a method for manufacturing a liquid crystal display device used in a field sequential system will be described. FIG. 12 shows a liquid crystal display device using a TFT element as a switching element.

A light-shielding film (not shown) is formed on the substrate 508 of the opposite substrate. Chromium (Cr) or the like can be used for the light shielding film. The thickness of the light-shielding film is 100 nm to 20
0 nm is desirable. The light-shielding film is provided in a region where the alignment failure of the liquid crystal occurs, thereby suppressing a decrease in contrast due to the alignment failure of the liquid crystal.

A transparent conductive film 510 is formed on the light shielding film. As the transparent conductive film, an indium tin oxide (ITO) film can be used. To keep the transmittance of visible light high,
The thickness of the ITO film is desirably 100 nm to 120 nm.

On the active matrix substrate and the counter substrate, alignment films 511 to 512 are formed. The thickness of the alignment film is preferably 30 nm to 80 nm. As the alignment film, for example, SE7792 manufactured by Nissan Chemical Co., Ltd. can be used. When an alignment film having a high pretilt is used, disclination can be suppressed when a liquid crystal display device is driven by an active matrix method.

The alignment films 511 to 512 are rubbed.

Although not shown, spacers may be provided in the pixel by scattering or patterning to improve the uniformity of the cell gap. In this embodiment,
To achieve high-speed response of liquid crystal, spacers should be 1.0 μm
To increase the electric field strength when driving the liquid crystal.

The opposing substrate and the active matrix substrate are bonded to each other with the sealant 513. The opposing substrate and the active matrix substrate are bonded so that the rubbing directions of the alignment films formed on these substrates are orthogonal to each other.
The sealant is a UV-curable sealant, XN manufactured by Mitsui Toatsu.
R5610-1H1 is used. Into the sealant, a silica ball, which is a silica-based spacer, manufactured by Catalyst Chemicals Co., Ltd. is placed. The diameter of the yarn ball is 1.0 μm. After the sealant has cured,
The opposing substrate and the active matrix substrate are separated.

A liquid crystal material 514 is injected. As the liquid crystal material, a low-viscosity material is desirable in terms of high-speed response. In this example, using a nematic liquid crystal whose alignment control is easy,
A TN (Twisted Nematic) orientation is performed by adding a chiral material. Of course, a ferroelectric liquid crystal or an antiferroelectric liquid crystal capable of high-speed response may be used. In the present invention, it is desirable to select a liquid crystal capable of displaying by analog gray scale for both the ferroelectric liquid crystal and the antiferroelectric liquid crystal. It is also possible to use a material obtained by adding a polymer resin to a ferroelectric liquid crystal or an antiferroelectric liquid crystal and curing a ferroelectric liquid crystal or a mixed system of an antiferroelectric liquid crystal and a polymer resin by light irradiation. . A method in which a polymer resin is added to a ferroelectric liquid crystal or an antiferroelectric liquid crystal to align the polymer material is called a polymer stabilization method.

After confirming that the liquid crystal material has been injected, the UV
The injection port is sealed with a hardening type sealant.

Next, a polarizing plate (not shown) is attached by a known technique. Through the above steps, a liquid crystal display device is completed.

[Embodiment 3] A liquid crystal display device formed by carrying out any one of Embodiments 1 and 2 can be used for various electro-optical devices. That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in a display unit.

Examples of such electronic devices include a video camera, a digital camera, a head mounted display (goggle type display), a car navigation, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone or an electronic book, etc.). Is mentioned. Examples of those are shown in FIGS.

FIG. 13A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 13B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102.

FIG. 13C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 13D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302.

FIG. 13E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 13F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502.

FIG. 14A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

FIG. 14B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 14C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first and second embodiments.

[0161]

By implementing the present invention, it is possible to reduce the response time of the field sequential type liquid crystal and the writing time of pixel data. by this,
A bright display with a long light source lighting time can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a circuit configuration of a method for driving a liquid crystal display device according to the present invention.

FIG. 2 is a diagram showing an example of a timing chart of a driving method of a liquid crystal display device according to the present invention.

FIG. 3 is a diagram showing an example of a timing chart of a driving method of a liquid crystal display device according to the present invention.

FIG. 4 is a diagram showing an example of a timing chart of a driving method of a liquid crystal display device according to the present invention.

FIG. 5 is a diagram showing an example of a circuit configuration of a driving method of a liquid crystal display device according to the present invention.

FIG. 6 is a diagram showing an example of a timing chart of a method for driving a liquid crystal display device according to the present invention.

FIG. 7 is a diagram showing an example of a timing chart when color display is performed by a field sequential method.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing an active matrix substrate (Example 1).

FIG. 9 is a cross-sectional view illustrating a method for manufacturing an active matrix substrate (Example 1).

FIG. 10 is a cross-sectional view illustrating a method for manufacturing an active matrix substrate (Example 1).

FIG. 11 is a top view showing a pixel portion of an active matrix substrate (Example 1).

FIG. 12 is a cross-sectional view of a liquid crystal display device (Example 2).

FIG. 13 illustrates an example of an electronic device (Example 3).

FIG. 14 illustrates an example of an electronic device (Example 3).

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 621 G09G 3/20 621F 623 623D 641 641E 3/34 3/34 JF term (Reference) 2H093 NA06 NA44 NA53 NA65 NB07 NB11 NB21 NB23 NC09 NC15 NC16 NC25 NC28 NC34 NC49 NC58 ND08 ND32 ND37 NE06 NG01 NH14 5C006 AA01 AA14 AA22 AC21 AF44 BB16 BC03 BC12 BF28 FA14 5C080 AA10 BB05 JJ02 JJ04 JJ04 JJ04

Claims (14)

[Claims] When a pixel electrode having a potential of a first signal voltage in a first sub-frame period has a potential of a second signal voltage in a second sub-frame period, the pixel electrode has a potential of the second signal voltage. Calculate the response time of the liquid crystal when the voltage value changes to the second signal voltage, and in the second sub-frame period, in order from the pixel having the longer response time of the liquid crystal, the pixel of the pixel A method for driving a liquid crystal display device, wherein a potential of the second signal voltage is applied to an electrode. 2. A liquid crystal display device according to claim 1, wherein a plurality of pixels connected to the same signal line and displaying the same gray scale are simultaneously supplied with a signal voltage potential to pixel electrodes of said plurality of pixel TFTs. Drive method. 3. A first pixel electrode connected to a first pixel TFT connected to a signal line and a first scanning line, and a second pixel electrode connected to the signal line and a second scanning line. Pixel TFT
A first step of applying a potential of a first signal voltage to a second pixel electrode connected to the second pixel electrode, and a second step of sequentially selecting a scanning line from the first scanning line to the second scanning line. Two steps, selecting the signal line and the second scan line, and selecting the second
The difference between the absolute value of the first signal voltage and the absolute value of the first signal voltage is 0 V
A third step of applying a potential of a second signal voltage larger than 0.5 V and smaller than 0.5 V. 4. The liquid crystal display device according to claim 1, wherein the liquid crystal display device has a first luminescent color, a second luminescent color, and a third luminescent color.
A driving method for a liquid crystal display device, wherein the emission color of the liquid crystal is intermittently incident. 5. A first means for storing a potential of a first signal voltage applied to a pixel electrode during a first sub-frame period, and a second signal voltage applied to the pixel electrode during a second sub-frame period. A second means for storing a potential; a third means for calculating a response time of the liquid crystal when a voltage value changes from the first signal voltage to the second signal voltage;
And a fourth means for applying the second signal voltage to the pixel electrode of the pixel in the order of the calculated response time of the liquid crystal, the liquid crystal display device comprising: 6. The apparatus according to claim 5, wherein said fourth means includes means for selecting a signal line connected to a pixel TFT of said pixel, and means for selecting a scanning line connected to a pixel TFT of said pixel. Liquid crystal display device characterized by the above-mentioned. 7. The liquid crystal display device according to claim 6, wherein the means for selecting the signal line has an address decoder. 8. The liquid crystal display device according to claim 7, wherein said means for selecting a scanning line has an address decoder. 9. A first means for detecting pixel TFTs connected to the same signal line and displaying the same gradation, and said pixel TF
A second means for simultaneously applying a signal voltage potential to the T pixel electrodes. 10. The device according to claim 9, wherein said second means includes means for selecting a signal line connected to a pixel TFT of said pixel, and means for selecting a scanning line connected to a pixel TFT of said pixel. A liquid crystal display device characterized by the above-mentioned. 11. The liquid crystal display device according to claim 10, wherein the means for selecting the signal line has an address decoder. 12. A liquid crystal display device according to claim 11, wherein said means for selecting a scanning line has an address decoder. 13. A plurality of pixel TFTs connected to a signal line, a first pixel TFT having a first pixel electrode for applying a potential of a first signal voltage, an absolute value of the first signal voltage, And a second pixel TFT having a second pixel electrode for applying a potential of a second signal voltage having an absolute value larger than 0 V and smaller than 0.5 V, and detecting the first pixel electrode and the second pixel TFT. A liquid crystal display device comprising: means for applying a potential of a first signal voltage to two pixel electrodes; and means for applying a potential of a second signal voltage to the second pixel electrode. 14. The liquid crystal display device according to claim 5, wherein the light source comprises a first light source, a second light source, and a third light source. Characteristic liquid crystal display device.