JP4776836B2 - Display device and driving method of display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device and a driving method thereof. A liquid crystal display device displays light and dark using the fact that the polarization state, scattering state, or wavelength characteristic of light passing through the liquid crystal layer changes depending on the voltage applied to the liquid crystal layer sandwiched between the substrates. It is.
[0002]
In this specification, a thin film transistor (TFT) refers to a semiconductor element having a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.
[0003]
[Prior art]
Liquid crystal display devices are widely used in portable applications and personal computer applications in terms of light weight and low power consumption.
[0004]
In a liquid crystal display device, a field sequential method that performs color display by sequentially turning on light sources of three primary colors, red, green, and blue, has attracted attention. Since the field sequential method does not require a color filter, high-definition display is expected.
[0005]
As the field sequential method, a method of lighting continuously by changing the light emission color sequentially is proposed (Monthly FPD Intelligence Press Journal 1999.2 p66-69). In this method, when the light emission color of the light source is switched, it is necessary to set the entire screen to the black level and prevent color mixing of the light source in each pixel.
[0006]
As a field sequential method, a method of turning on the light source after the response of the liquid crystal is completed within the screen (edited by Keisuke Kobayashi, Color Liquid Crystal Display Industry Book Japan p127) has been proposed. In this method, since the light source is intermittently turned on, complete black can be achieved when the light source is not turned on. For this reason, an impulse method, which is a CRT (cathode ray tube) driving method, can be achieved also in a liquid crystal display device, and is expected as a means for preventing an afterimage peculiar to the liquid crystal display device.
[0007]
[Problems to be solved by the invention]
The problems to be solved by the invention are shown below.
[0008]
Note that in this specification, a TFT provided in a pixel portion is referred to as a pixel TFT.
[0009]
In this specification, the pixel portion is provided with a signal line having addresses S1 to Sm, a scanning line having addresses G1 to Gn, and a pixel disposed in the vicinity of the intersection of the signal line and the scanning line. . Each pixel has a pixel TFT, and the pixel TFT has a gate electrode connected to the scanning line and a source electrode connected to the signal line. The address of each pixel is indicated by the address of the signal line to which the source electrode of the pixel TFT is connected and the address of the scanning line to which the gate electrode is connected. For example, when the pixel TFT is connected to the i-th signal line and the j-th scanning line, the address of the pixel having this pixel TFT is (i, j).
[0010]
Further, a pixel electrode is provided in connection with the drain electrode of the pixel TFT, and there is a counter electrode facing the pixel electrode. A liquid crystal is sandwiched between the pixel electrode and the counter electrode via an alignment film, and the liquid crystal switches according to a potential difference between the pixel electrode and the counter electrode.
[0011]
In the dot sequential driving, the time taken from the selection of the first scanning line to the selection of the nth scanning line is referred to as a “scanning line scanning period”. In addition, applying a predetermined potential, for example, a potential of +8 V to +11 V to the scanning line in order to activate the semiconductor layer is referred to as “selecting the scanning line”. A period for selecting a scanning line is referred to as a “scanning line selection period”.
[0012]
That is, the “scanning period of the scanning line” is the time taken from the start of the selection of the first scanning line to the end of the selection of the nth scanning line. “Selecting the scanning line” means that a gate pulse is applied to the pixel TFT connected to the scanning line to bring the source and drain of the pixel TFT connected to the scanning line into a conductive state. . The scanning line selection period is a period for selecting one scanning line, and a scanning line scanning period is obtained by multiplying the scanning line selection period by n times.
[0013]
The selection of a signal line means that a signal voltage is applied to the signal line and a potential of the signal line is applied to the pixel TFT connected to the signal line.
[0014]
Also, a period from the start of applying a potential necessary for image display to the pixel electrode of the pixel TFT having the address (1, 1) to the formation of one monochrome image is referred to as a “subframe period”. A period from the start of applying a potential necessary for image display to the pixel electrode of the pixel TFT having the address (1, 1) to the formation of one color-displayed image is referred to as a “frame period”.
[0015]
In the field sequential method, a frame period in which a color-displayed image is formed includes a subframe period in which a red image is formed, a subframe period in which a blue image is formed, and a subframe period in which a green image is formed. Become.
[0016]
FIG. 7 shows a timing chart of the field sequential method in which the light source is intermittently turned on. In the field sequential method, the period (T) of one frame period is 16.6 msec, and the period (T / 3) of the subframe period is 5.5 msec.
[0017]
In dot-sequential driving, one scanning line is selected, and signal lines are sequentially selected by the shift register of the source driver, so that the potential of the signal line is applied to the pixel electrode of the pixel TFT connected to the selected scanning line. Is granted. The subframe period is divided into four periods: a standby period 301, a scanning line selection period 302, a liquid crystal response period 303, and a light source lighting period 304. The standby period is a period from the start of one frame period until the scanning line connected to the pixel TFT is selected. The liquid crystal response period is a period in which the liquid crystal responds according to the potential of the pixel electrode. The scanning line scanning period 308 is obtained by multiplying the scanning line selection period by the number n of scanning lines.
[0018]
A scanning line is selected in the scanning line selection period 302, and the potential of the signal line is sequentially applied to the pixel electrode of the pixel TFT connected to the scanning line in accordance with a desired gradation. In the liquid crystal response period 303, the optical response of the liquid crystal is completed. During the lighting period 304 of the light source, the light source is intermittently turned on, and the first emission color 305, the second emission color 306, and the third emission color 307 enter the liquid crystal display device in order. For example, red can be used as the first emission color, green as the second emission color, and blue as the third emission color. However, when the light source is intermittently turned on in this way, the liquid crystal response period 303 of course between the pixel TFT connected to the first scanning line and the pixel TFT connected to the nth scanning line is naturally Different. Therefore, when it takes time to respond to the liquid crystal or when the scanning period 308 of the scanning line is long, if the light source is turned on after the response of the liquid crystal is completed, the lighting period 304 of the light source is shortened and the brightness is lowered. To do.
[0019]
That is, the response time of the liquid crystal is one of the important elements in the field sequential method. The faster the liquid crystal response time, the longer the lighting period of the light source, and the brighter the display.
[0020]
Further, an important factor in the field sequential method is the scanning period of the scanning line. Assuming that there are 1 to n scanning lines, the longer the scanning period, the shorter the time from when the signal line potential is applied to the pixel electrode until the light source is turned on as the scanning line approaches the nth line. The light source is turned on before the liquid crystal is fully responsive. Since the gradation level is determined by the integral value of the brightness displayed by the liquid crystal when the light source is on, if the light source is turned on before the liquid crystal is fully responsive, the gradation level when the screen is displayed will change. End up. Conversely, when the light source is turned on after the liquid crystal responds, the lighting period of the light source is shortened and the display becomes dark.
[0021]
In addition, in an XGA (horizontal 1024 pixels × vertical 768 pixels) and SXGA (horizontal 1280 pixels × vertical 1024 pixels) liquid crystal display device having a large number of scanning lines, the ratio of the scanning period of the scanning lines to the subframe period cannot be ignored. When dot-sequential driving is performed in the SXGA liquid crystal display device, the scanning period of the scanning line is estimated to be 1 to 2 msec even if the signal writing time to one pixel is set to 0.75 to 1.5 nsec. Therefore, when the scanning period of the scanning line is removed from the subframe period (5.5 msec), only 3.5 to 4.5 msec is left, and the liquid crystal is made to respond until it shows a desired brightness at this time, Next, when the light source is turned on, the lighting time of the light source is considerably shortened, and bright display becomes difficult.
[0022]
In this specification, it is an object to finish the optical response of liquid crystal more quickly when driving a liquid crystal display device by a field sequential method. It is another object of the present invention to reduce the scanning period of the scanning line and reduce the ratio of the standby period 301 to the subframe period.
[0023]
That is, in this specification, in the field sequential method, it is an object to shorten the sum of the standby period 301 and the liquid crystal response period 303, to lengthen the light source lighting period 304, and to display brightly.
[0024]
[Means for solving the problems]
According to the present invention, when the pixel electrode having the potential of the first signal voltage in the first subframe period has the potential of the second signal voltage in the second subframe period, The response time of the liquid crystal when the voltage value changes to the signal voltage is calculated, and the second signal voltage of the second signal voltage is applied to the pixel electrode of the pixel in order from the pixel having the long response time of the liquid crystal calculated in the second subframe period It is characterized by providing a potential.
[0025]
In the present invention, the circuit configuration includes a first means for storing a potential of a first signal voltage applied to the pixel electrode in the first subframe period, and a second signal applied to the pixel electrode in the second subframe period. A second means for storing the potential of the voltage; a third means for calculating the response time of the liquid crystal when the voltage value changes from the first signal voltage to the second signal voltage; and the calculated response time of the liquid crystal And fourth means for applying a second signal voltage to the pixel electrode of the pixel in the order of the longer pixels.
[0026]
The field sequential method includes a sub-frame period that is a period for forming a monochrome image and a frame period that is a period for forming a color image by combining three sub-frame periods in succession. The above configuration can be applied to this field sequential method. Further, by replacing the subframe period with a frame period, the present invention is not limited to the field sequential method, and can be widely applied to a liquid crystal display device and a driving method thereof.
[0027]
In the dot sequential driving, pixels are sequentially selected from the pixel electrode connected to the pixel TFT connected to the first-row scanning line to the pixel having the pixel TFT connected to the n-th scanning line. For this reason, if the response time of the liquid crystal is long in the pixels connected to the n-th scanning line, the liquid crystal may not fully respond until the light source is turned on in the field sequential method. However, according to the present invention, when the image changes from the first sub-frame period to the second sub-frame period and the liquid crystal responds, the pixels that take the response time of the liquid crystal are preferentially selected. 7, the waiting period 301 is shortened in a pixel having a long liquid crystal response period 303, and the sum of the waiting period 301 and the liquid crystal response period 303 can be shortened. That is, the lighting period 304 of the light source can be lengthened and bright display is possible.
[0028]
Further, the present invention is characterized in that the same signal voltage potential is simultaneously applied to the pixel electrodes of a plurality of pixels displaying the same gradation connected to the same signal line. By simultaneously selecting a plurality of pixels, the scanning time of the scanning line can be shortened.
[0029]
In addition, the present invention provides a first pixel electrode connected to the first pixel TFT connected to the signal line and the first scanning line, and a second pixel electrode connected to the signal line and the second scanning line. There is a first stage in which a potential of a first signal voltage is applied to a second pixel electrode provided in connection with the pixel TFT.
[0030]
Then, a second signal line and a second scanning line are selected, and a second signal voltage having a difference in absolute value from the first signal voltage larger than 0V and smaller than 0.5V is applied to the second pixel electrode. Having stages.
[0031]
In this way, in the first stage, the liquid crystal is caused to respond in advance by applying the potential of the first signal voltage to the second pixel electrode connected to the drain electrode of the second pixel TFT. The second pixel electrode is a pixel electrode that displays a gradation approximate to that of the first pixel electrode. The approximate gradation is a gradation displayed by an absolute value of a voltage larger than 0V and smaller than 0.5V with respect to the absolute value of the voltage applied to the first pixel electrode as a guide. Then, in the second stage, a second signal voltage is applied to the second pixel electrode, and the liquid crystal is caused to respond so as to display a normal gradation. By causing the liquid crystal to respond in this manner, the response time until response to the gradation of the display image can be shortened when the potential of the second signal voltage is applied to the second pixel electrode.
[0032]
Of course, in order to prevent liquid crystal burn-in, the first pixel TFT and the second pixel TFT that simultaneously write signals of the signal lines may be pixel TFTs that are scheduled to be written with the same polarity in advance.
[0033]
Each of the above-described inventions can be widely used as a liquid crystal display device and a driving method thereof, but is particularly effective in a field sequential system in which a light source is intermittently turned on. Since the light source is turned on intermittently, even if the order of writing the signal voltage to the pixel TFT is random, the light source is not turned on while the signal voltage is written to the pixel TFT, so this random writing is not visible to the user. Because.
[0034]
If the above invention can be used in combination, it can be widely applied not only to the field sequential method but also to a known liquid crystal driving method.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
The circuit configuration of the present invention will be described with reference to FIG. FIG. 1 shows a pixel and a drive circuit of this embodiment. In FIG. 1, in a pixel portion having pixels arranged in a matrix of m columns × n rows, the addresses of the pixels arranged in the i-th column and the j-th row are (i, j) (i is 1 An integer of n or less and j is an integer of 1 or more and m or less).
[0036]
One frame period includes a first subframe period to a third subframe period. The video signal 130 in the first subframe period to the third subframe period and the address of the pixel to which the video signal is input are input to the first means or the second means depending on the designation of the switching circuit 131.
[0037]
Note that the video signal 130 may be an analog signal or a digital signal. However, in order to store the video signal with high accuracy, when the video signal 130 is an analog signal, an analog-digital converter (AD converter) is used before inputting the video signal to the first means or the second means. It is good to convert it into a digital signal.
[0038]
There is a first means for storing the potential of the first signal voltage applied to the pixel electrode in the first subframe period. The first means is referred to as first storage means 101 because of its function. In addition, there is a second means for storing the potential of the second signal voltage applied to the pixel electrode in the second subframe period. The second means is referred to as second storage means 102 because of its function.
[0039]
Then, in the same pixel TFT, there is a third means for calculating the response time of the liquid crystal when the voltage value changes from the first signal voltage to the second signal voltage. The third means is referred to as a comparison calculation means 103 because of its function. In calculating the response time of the liquid crystal, the theoretical value of the response time is preferably calculated from physical constants such as the rotational viscosity coefficient, elastic constant, and dielectric anisotropy of the liquid crystal. Further, the relationship between the response time of the liquid crystal and the driving voltage may be input to the comparison calculation means in advance and the data may be referred to. Then, in accordance with the calculated response time of the liquid crystal, the order of writing the signal line signals to the pixel TFTs in the second subframe period is determined.
[0040]
First, the response time of the liquid crystal when the signal voltage changes from the first signal voltage to the second signal voltage is calculated. The response time of the liquid crystal when the calculation is performed on all the pixels is the longest in the pixel of the address (2, 2), and the address of (2, 1), (1, 1), (1, 2). It is assumed that the response time decreases in the order of the pixels. That is, it is assumed that the response time of the liquid crystal is the shortest when the signal voltage changes from the first signal voltage to the second signal voltage in the pixel at the address (1, 2) among the four pixels. In this case, when an image in the second subframe period is displayed, the order of writing the signal line signal to the pixel TFT is (2, 2), (2, 1), (1, 1), (1 2) in the order of addresses. That is, the signal line signal is written in the second subframe period in order from the pixel TFT of the pixel having a long response time of the liquid crystal. For convenience, the description has been made with four pixels, but the same applies to n × m pixels, and the response time of the liquid crystal when the signal voltage changes from the first signal voltage to the second signal voltage. The signal line signal is written in order from the pixel TFT of the long pixel. When the response times of the liquid crystals are the same in a plurality of pixels, the signal line signals are written into the pixel TFTs in the order in which the pixels are close to reduce the burden on the driving circuit.
[0041]
Then, during the first subframe period, the order of writing the signal line signals to the pixel TFTs in the second subframe period is stored in the comparison calculation data storage unit 104.
[0042]
Then, there is a fourth means for applying the second signal voltage to the pixel electrodes of the pixels in order of the pixels having the long response time of the calculated liquid crystal. In this embodiment, the fourth means includes an X address write control means 110 having an X address decoder 106 and a video signal output means 108 connected to the X address decoder, a Y address decoder 105 and a level shifter connected to the Y address decoder. Y address write control means 109 having -107.
[0043]
Of the fourth means, the X address write control means 110 having the X address decoder 106 and the video signal output means 108 is connected to the pixel TFT based on the X address data output from the comparison calculation data storage means 104. There is a function to select a signal line. The Y address write control means 109 having the Y address decoder 105 and the level shifter 107 has a function of selecting a scanning line connected to the pixel TFT based on the Y address data output from the comparison operation data storage means 104. is there.
[0044]
Based on the Y address data output from the comparison calculation data storage means 104, the address of the scanning line of the pixel TFT to which the signal of the signal line is written is designated by the Y address decoder 105. When the number of pixels is SXGA (horizontal 1280 × vertical 1024), the number of input terminals of the Y address decoder is 10 in accordance with the number of pixels. ^Ten The scanning lines can be arbitrarily selected. Of the output terminals of the Y address decoder, an output pulse is output from an output terminal having a Y address designated by the Y address data. Then, the level shifter 107 amplifies the voltage of the output pulse and outputs the gate pulse to the scanning line having the designated Y address.
[0045]
The X address decoder 106 designates a signal line for applying a signal voltage potential. When the number of pixels is SXGA (horizontal 1280 × vertical 1024), the number of input terminals of the X address decoder may be set to 11 in accordance with the number of pixels. An output pulse is output from the output terminal of the X address designated by the X address decoder 106 and input to the video signal output means 108. Then, a video signal (signal voltage) is input to the signal line of the designated X address, and a signal voltage is applied to the signal line. Regarding the video signal 119, the order in which the video signals are written to the pixel TFTs is determined by the external circuit (comparison calculation data storage unit 104), and is input to the video signal output unit 108.
[0046]
When the video signal input to the video signal output means is a digital signal, a digital analog converter (DA converter) is built in the video signal output means and converted to an analog signal.
[0047]
In this way, the signals of the signal lines are sequentially written into the pixel TFT 118 in accordance with the order stored by the comparison calculation data storage means 104, and an image in the second subframe period is formed.
[0048]
The operation of the circuit will be described with reference to FIG. By combining the images displayed in the first subframe period to the third subframe period, a color-displayed image is displayed in the first frame period 916. In the preparation period 912, first, there is a first period 900 in which the first memory means stores the address of the pixel TFT in the first subframe period and the first signal voltage to be written in the pixel TFT. Next, when the image of the first subframe period is formed in the comparison calculation means, there is a second period 901 for calculating the response time of the liquid crystal in each pixel. Finally, there is a third period 902 in which the data of the comparison calculation means is moved to the comparison calculation data storage means.
[0049]
In the first subframe period 913, there is a period 903 in which a signal of a signal line is written to the pixel TFT. Next, there is a liquid crystal response period 904 in which the liquid crystal responds according to the written first signal voltage. There is a light source lighting period 905 in which the light source is turned on. The first emission color emitted from the light source in the first subframe period can be, for example, red among the three primary colors of additive color mixing.
[0050]
In the first subframe period 913, in order to form an image in the second subframe period in parallel, the order in which the second signal voltage is written to the pixel TFT is determined. Since the first memory means already stores the first signal voltage in the pixels of the X address and Y address in the first subframe period, in the fourth period 906, the first memory voltage is stored in the second memory means. The second signal voltage in each pixel of the X address and Y address in the second subframe period is stored. Next, in the fifth period 907, the comparison calculation means calculates the response time of the liquid crystal when the signal voltage changes from the first signal voltage to the second signal voltage, and selects a pixel from the calculation result Decide the order to do. Then, in the sixth period 908, the data of the comparison calculation means is moved to the comparison calculation data storage means.
[0051]
Next, in the second subframe period 914, the pixel data of the comparison calculation data storage unit is written into the pixels. The second subframe period includes a pixel data writing period 909, a liquid crystal response period 910, and a light source lighting period 911. The second emission color emitted from the light source can be, for example, green.
[0052]
An image in the third subframe period is formed by a circuit operation according to the second subframe period. In the third subframe period 915, the third emission color emitted from the light source can be, for example, blue. Thus, an image for color display is formed in the first frame period. By continuously repeating the above operation, a moving image consisting of a colorized image can be displayed.
[0053]
In other words, using the field sequential timing chart of FIG. 7, according to the present invention, a pixel having a long liquid crystal response period 303 can shorten the standby period 301, so that the standby period 301 and the liquid crystal response period are shorter than conventional ones. The sum with 303 can be shortened. Thereby, the lighting period 304 of the light source can be lengthened. In addition, the field sequential color display method in which the light source is intermittently lit and the present embodiment are used in combination, and even if the order of selecting pixels is random, the light source is in the response period of the liquid crystal. This random writing is not recognized by the user because it is not lit.
[0054]
FIG. 3 shows a timing chart of the Y address write control means 109. A drive circuit having a level shifter and a Y address decoder is referred to as Y address write control means. The Y address writing control means is means for selecting a scanning line connected to the pixel TFT.
[0055]
The timing chart of the Y address write control means will be explained. First, a plurality of Y address data 111 is input to the input terminal of the Y address decoder. For example, when there are 1024 scanning lines, there are 10 X address data for selecting any one of the 1024 scanning lines, and each X address data is information of “0” or “1”. Have Then, an output pulse 112 is output from the output terminal of the Y address decoder having the Y address designated by the Y address data. The voltage value of the output pulse 112 is amplified by a level shifter and converted into a gate pulse 117. The gate pulse is then output to the designated Y address scan line. In this way, the scanning line connected to the pixel TFT of the pixel that takes a long response time of the liquid crystal is preferentially selected. In the first subframe period, the output pulses 112 to 116 are sequentially output to the designated Y address according to the order of the pixel TFTs to which the first signal voltage is written. The output pulse is converted into gate pulses 117 to 121 by the shift register, and the scanning line is selected. In the second subframe period 133, as in the first subframe period 132, the output pulse is converted into a gate pulse, and a scanning line connected to the pixel TFT of the pixel that takes a long response time of the liquid crystal is selected first. Is done. Thereafter, image formation is repeated at a timing according to this.
[0056]
For example, in a display device of VGA (horizontal 640 pixels × vertical 480 pixels), the pixels with a slow response time of the liquid crystal are (1, 5), (6, 2), (150, 4). 3), (200, 300). That is, it is assumed that the response time of the liquid crystal is the longest in the pixels (1, 5) and the response time of the liquid crystal is the shortest in the pixels (200, 300). In this case, the gate pulse 117 is output to the scanning line having the address G5, the gate pulse 118 is output to the scanning line having the address G2, and the gate pulse 119 is output to the scanning line having the address G4. Is done. Then, the gate pulse 120 is output to the scanning line having the address of G3, and finally the gate pulse 121 is output to the scanning line having the address of G300.
[0057]
FIG. 4 shows a timing chart of the X address write control means 110. A drive circuit comprising an X address decoder and a video signal output circuit is referred to as X address write control means. The X address writing control means is means for selecting a signal line connected to the pixel TFT.
[0058]
The timing chart of the X address write control means will be described. First, X address data 122 indicating the order in which signal lines are selected is input to the input terminal of the X address decoder. For example, when there are 1240 signal lines, there are 11 Y address data for selecting any one of these 1240 signal lines, and each Y address data is information of “0” or “1”. Have Output pulses 123 to 127 are output from the output terminal of the X address designated by the X address data 122 among the output terminals of the X address decoder. The video signal 129 is input to the signal line of the designated X address, and a signal voltage potential is applied to the signal line. In the second subframe period, similarly to the first subframe period, the signal line connected to the pixel TFT of the pixel having the longest response time of the liquid crystal is preferentially selected.
Thereafter, image formation is repeated at a timing according to this.
[0059]
For example, in a display device of VGA (horizontal 640 pixels × vertical 480 pixels), the pixels with a slow response time of the liquid crystal are (1, 5), (6, 2), (150, 4). 3), (200, 300). That is, it is assumed that the response time of the liquid crystal is the longest in the pixels (1, 5) and the response time of the liquid crystal is the shortest in the pixels (200, 300). In this case, after the output pulse 123 is output on the signal line having the address S1, the output pulse 124 is output on the signal line having the address S6, and the output pulse 125 is output on the signal line having the address S150. The Then, the output pulse 126 is output to the signal line having the address of S60, and finally the output pulse 127 is output to the signal line having the address of S200.
[0060]
The pulse widths of output pulses output from the X address decoder and the Y address decoder are the same. In the pixel portion having pixels arranged in a matrix of m columns × n rows, the number of output pulses output from the X address decoder and the Y address decoder is m × n, respectively, and the pixels having the long response time are sequentially ordered. Data is written for each pixel.
[0061]
[Embodiment 2]
An embodiment of the present invention is shown in FIG. 5 is characterized in that a plurality of address decoders, that is, a first Y address decoder and a second Y address decoder are provided. In FIG. 5, the addresses of the pixels arranged in the i-th column and the j-th row are described as (i, j) (i is an integer from 1 to n, j is an integer from 1 to m). Yes.
[0062]
First, data of the video signal (signal voltage) 200 at the X address and the Y address in the first subframe period is stored in the storage unit 201. The Y address indicates the address of the signal line. The X address indicates the address of the scanning line.
[0063]
That is, the video signal and the address of the pixel to which the video signal is input are stored in the storage unit 201.
[0064]
The first means for detecting pixels displaying the same gradation connected to the same signal line is a pixel that displays with the same signal voltage in the plurality of pixel TFTs 210 connected to the signal line of the same X address. A program is written to simultaneously write the signal line signal to the pixel TFTs. In the present embodiment, the first means is referred to as comparison means 202 because of its function. For example, in the first frame period, among the pixel TFTs connected to the signal line with the X address of 1, when the pixels with the Y address of 1, 10 and n perform display with the same signal voltage, (1, 1), ( Pixel TFTs with addresses 1, 10) and (1, n) are detected by the comparison means. In this embodiment, in order to simplify the description, the same signal voltage is simultaneously written into a maximum of two pixel TFTs. In addition, the pixel TFT that writes the signal line signal simultaneously with the pixel TFT with the address (1, 1) has a larger Y address among the remaining two pixels ((1, 10) and (1, n)). It is assumed that the pixel TFT has an address (1, n). In the dot sequential driving, the pixel TFT having a larger Y address value has a longer time for writing a signal line signal to the pixel TFT, and the waiting time 301 in FIG. 7 tends to be longer in the field sequential method. This is because it is better to preferentially select a pixel TFT having a large value. Of course, not only the signal line signals can be simultaneously written to the two pixel TFTs, but also the signal line signals can be simultaneously written to the three pixel TFTs by changing the design of the drive circuit.
[0065]
Next, the comparison data storage unit 203 stores the order of writing the signal line signals to the pixels, which is determined by the comparison unit 202.
[0066]
There is a second means for simultaneously applying the potential of the signal voltage to the pixel electrodes of the plurality of pixel TFTs. In the present embodiment, the second means is the X address decoder 204, the video signal output means 205, the first Y address decoder 206 and the second Y address decoder 208, the first level shifter 207 and the second level shifter. 209.
[0067]
The X address decoder 204 is a means for selecting the address of the signal line based on the X address data output from the comparison data storage means. The first Y address decoder 206 and the second Y address decoder 208 are means for selecting the address of the scanning line based on the Y address data output from the comparison data storage means.
[0068]
The X address decoder 204 outputs an output pulse to the output terminal of the designated X address of the X address decoder based on the X address data output from the comparison data storage means 203. Although not shown, in the case of liquid crystal display means having the number of pixels of SXGA, the X address decoder has 11 input terminals and 1280 output terminals. The X address of the signal line that gives the potential of the signal voltage is designated by the X address decoder. Here, 1 is designated as the X address.
[0069]
The video signal output means 205 supplies a video signal to the X address signal line designated by the X address data. The order of the video signals is determined by the external circuit (comparison data storage means 203), and the video signals 211 are input to the video signal output means in accordance with the order.
[0070]
The first Y address decoder 206 outputs an output pulse from the output terminal of the designated Y address based on the Y address data output from the comparison data storage means 203. Although not shown, in the case of the liquid crystal display means having the number of SXGA pixels, the Y address decoder has 10 input terminals and 1024 output terminals. Assume that an output pulse is output from an output terminal whose Y address of the first Y address decoder is 1. Assume that an output pulse is output from an output terminal whose Y address of the second Y address decoder 208 is n.
[0071]
The first level shifter 207 connected to the first Y address decoder and the second level shifter 209 connected to the second Y address decoder amplify the voltage of the output pulse to form a gate pulse having a gate voltage.
[0072]
By selecting the scanning line and the signal line of the address designated by the first Y address decoder, the second Y address decoder, and the X address decoder, (1, 1) and (1, n) of the pixel TFT 210 are selected. ) Is selected and the signal line signal is written. Thus, the address of the pixel TFT is sequentially specified, and the signal line signal is written to the pixel TFT. In this embodiment, since the signal line signal can be simultaneously written to a maximum of two pixel TFTs, the total time of applying the signal line signal to the pixel TFTs, that is, the scanning time of the scanning lines can be shortened.
[0073]
The operation of the circuit will be described with reference to FIG. In the preparation period 912, there is a first period 900 in which the signal voltage data at the X address and the Y address in the first frame period is input to the storage unit. In the comparison means, there is a second period 901 in which pixel TFTs to which the same signal voltage is written are detected in the pixel TFTs connected to the same signal line, and the Y address of those pixel TFTs is confirmed. There is a third period 902 in which the order of applying signal line signals to the pixel TFTs determined by the comparison means is written in the comparison data storage means.
[0074]
In the first subframe period, there is a period 903 in which a signal line signal is written to the pixel TFT in order to display an image on the pixel TFT. Next, there is a liquid crystal response period 904 that responds according to the first signal voltage in which the liquid crystal is written. There is a period 905 during which the light source is turned on. The first emission color emitted from the light source in the first subframe period can be, for example, red among the three primary colors of additive color mixing.
[0075]
In the first subframe period, the signal of the signal line is simultaneously input in the fourth period 906 for inputting the signal voltage data in the X address and Y address in the second subframe period in parallel in the second subframe period. There is a fifth period 907 in which the address of the pixel TFT to be written is detected by the comparison means, and a sixth period 908 in which the order of signal writing of the signal lines determined by the comparison means is written in the comparison data storage means.
[0076]
Thereafter, similarly, in the second sub-frame period, a monochrome image is formed by starting the operation of applying a signal line signal to the pixel TFT and turning on the light source. The second emission color emitted from the light source can be green. A circuit according to the fourth to sixth periods for determining the order in which signal voltages are written to the pixel TFTs in order to form an image in the third subframe period in parallel in the second subframe period. There is an operation. Then, a monochrome image is displayed during the lighting period of the light source in the third subframe period. The third emission color emitted from the light source can be blue. In this way, a color image is formed in the first frame period. Thereafter, the same operation is sequentially repeated to display a moving image.
[0077]
By simultaneously writing signal line signals to a plurality of pixel TFTs displaying the same gradation connected to the same signal line, a moving image display image is formed by a driving method that shortens the scanning time of the scanning line. .
[0078]
In FIG. 5, since the first Y address decoder and the second Y address decoder are provided in the drive circuit connected to both ends of the scanning line, the number of pixels having the same signal voltage potential at the same time is as follows. There were a maximum of two. However, the embodiment of the present invention is not limited to this. By changing the circuit configuration, it is possible to select three or more pixel TFTs that apply the same signal voltage potential among the pixel TFTs connected to the same signal wiring. In this case, in FIG. 5, instead of providing the first Y address decoder 206 and the second Y address decoder 208, a circuit capable of selecting a plurality of scanning lines (referred to as a scanning line selection circuit) is stored in the comparison data memory. Provided between the means 203 and the first level shifter 207, three or more scanning lines may be simultaneously selected by the scanning line selection circuit. In this case, the second level shifter 209 is not necessary.
[0079]
According to the present embodiment, it is possible to shorten the scanning time required for applying a predetermined signal voltage to a pixel in dot sequential driving. For example, using the timing chart of FIG. 7, the sum of the standby period 301 and the liquid crystal response period 303 can be shortened. Further, compared with the first embodiment, the comparison calculation means 102 for calculating the response time in FIG. 1 is not required, so that the processing performed by the circuit is facilitated and the circuit configuration is simplified.
[0080]
A timing chart of the circuit of this embodiment will be described with reference to FIG. The X address decoder and the video signal output means are collectively referred to as X address write control means in this specification. The X address writing control means is means for selecting a scanning line connected to the pixel TFT. Each of the X address data 122 has information of “0” or “1”. When the number of scanning lines is 1024, ten X address data are simultaneously input to the X address decoder. Based on the X address data 122, an output pulse 123 is output from the output terminal of the designated X address among the output terminals of the X address decoder. In the present embodiment, unlike the first embodiment, basically, output pulses may be sequentially output from the first column to the m-th column of signal lines. At the same time as the output pulse 123 is output, the video signal pulse 129 is output to the signal line of the designated X address. With the above operation, a signal is given to the signal line of the X address designated by the X address data.
[0081]
The first Y address decoder and the first level shifter are collectively referred to as first Y address write control means in this specification. The second Y address decoder and the second level shifter are collectively referred to as second Y address write control means in this specification. The first Y address write control means and the second Y address write control means are means for selecting a signal line connected to the pixel TFT. Since the voltage of the output pulse output from the first Y address decoder and the second Y address decoder is amplified by the first level shifter or the second level shifter as in the first embodiment, FIG. 6 is used. The operations of the first Y address decoder and the second Y address decoder will be described.
[0082]
The Y address data has information of “0” or “1”. Based on the Y address data, the address of the terminal of the Y address decoder to which the output pulse is output is determined. For example, when there are 1240 signal lines, there are 11 Y address data to select any one of these 1240 signal lines, and each Y address data is “0” or “1”. Have information.
[0083]
In the first subframe period, based on the Y address data 212, an output pulse 213 is output from the output terminal of the designated Y address of the first Y address decoder. In this embodiment, first, in order to select the first scanning line in the first matrix, an output pulse is output from the output terminal whose Y address is 1. Note that the total number of output pulses 213 to 217 output from the first Y address decoder 223 is mxn or less from the circuit operation when there are n rows of scanning lines and m columns of signal lines.
[0084]
If there is a second pixel TFT that writes a signal of the same signal line as the first pixel TFT connected to the first scanning line, the Y of the second scanning line to which the second pixel TFT is connected. In order to select an address, an output pulse 218 is output from the output terminal corresponding to the address of the second scanning line of the second Y address decoder. The output pulses 218 to 220 output from the second Y address decoder 224 are output only when there are pixel TFTs connected to different scanning lines and simultaneously writing signals on the signal lines.
[0085]
Thereafter, similarly, when there are two pixel TFTs for simultaneously writing the signal of the signal line, output pulses are simultaneously output from the first Y address decoder and the second Y address decoder to select the scanning line.
[0086]
Note that the pulse widths of the output pulses output from the X address decoder, the first Y address decoder, and the second Y address decoder are the same.
[0087]
According to the method of this embodiment, it is possible to shorten the time required to write signals to all the pixels.
[0088]
[Embodiment 3]
An embodiment of the present invention will be described with reference to FIG. What is characteristic in this embodiment is that the first signal voltage is simultaneously written in a plurality of pixel TFTs connected to the same signal line, that is, the first pixel TFT and the second pixel TFT. The difference from the second embodiment is that after applying the first signal voltage to the second pixel TFT and causing the liquid crystal to respond in advance, the second signal voltage is further written. By making the liquid crystal respond in two steps in this way, the time for the liquid crystal to respond after writing the second signal voltage to the second pixel TFT can be shortened. It is assumed that the difference between the absolute value of the first signal voltage and the absolute value of the second signal voltage is larger than 0V and smaller than 0.5V. Hereinafter, the approximate gradation refers to a gradation that can be displayed in a range where the difference between the first signal voltage applied to the liquid crystal and the second signal voltage is greater than 0V and less than 0.5V.
[0089]
First, the video signal (signal voltage) 200 at the X address and Y address in the first subframe period is stored in the storage unit 201.
[0090]
When the comparison unit 202 displays an image on one screen, the first pixel electrode having the first pixel electrode that applies the potential of the first signal voltage among the plurality of pixel TFTs connected to the same signal line. The second pixel TFT having a second pixel electrode that provides a potential of the second signal voltage having an absolute value larger than 0V and smaller than 0.5V, and a difference between the pixel TFT of the first pixel voltage and the absolute value of the first signal voltage And detect. Then, a program is set so that the potential of the first signal voltage is applied to the first pixel electrode and the second pixel electrode, and then the potential of the second signal voltage is applied to the second pixel electrode. Depending on the image to be displayed, the second pixel TFT may be plural or singular.
[0091]
Compared to the second embodiment, in the driving method of the present embodiment, the signal line and the first scanning line are out of the pixel TFTs connected to the signal line even if there is no pixel that writes the same signal voltage as the first pixel TFT. When the first pixel having the first pixel TFT connected to the second pixel TFT and the second pixel having the second pixel TFT connected to the signal line and the second scanning line display approximate gradation levels Has a first stage of writing a first signal voltage to the first pixel TFT and the second pixel. In the present embodiment, at the first stage, a maximum of two pixels are simultaneously written with signals of the same signal line. In addition, in the dot sequential driving, as the pixel connected to the scanning line having a large X address value, the time for applying the potential of the predetermined signal voltage to the pixel is delayed, and the standby time 301 in FIG. 7 tends to be long. A pixel connected to a scanning line having a larger X address value is preferentially selected.
[0092]
Next, as a second stage of the driving method of the present embodiment, the scanning lines are sequentially selected from the first scanning line to the second scanning line, and the signal of the signal line is written to the pixel. Of course, when two pixel TFTs connected to the same signal line exhibit an approximate gradation while selecting the second scanning line from the first scanning line, the signal of the signal line is simultaneously applied to these two pixel TFTs. May be written.
[0093]
Thereafter, as the third stage of the driving method of the present embodiment, the second signal voltage having the normal gradation level is written again to the second pixel TFT in which the first signal voltage is written. The difference between the second signal voltage and the absolute value of the first signal voltage is greater than 0V and less than 0.5V.
[0094]
Thus, the comparison unit 202 determines the order of writing the signal line signals to the pixels. That is, the comparison unit is programmed to perform the first to third stage operations.
[0095]
In other words, the driving method of the present embodiment is characterized in that the signal of the signal line is written in advance simultaneously with the first pixel TFT to the second pixel that displays the gradation level approximate to that of the first pixel, and the liquid crystal is caused to respond. Keep it. As a result, the liquid crystal responds to the approximate gradation level until the second signal voltage is written to the second pixel TFT again. Therefore, after writing the second signal voltage, a predetermined gradation is obtained. The response time until the liquid crystal responds to (gradation determined by the second signal voltage) is shortened.
[0096]
Next, the order of the pixel TFTs into which the signal of the signal line determined by the comparison unit 202 is written is stored in the comparison data storage unit 203.
[0097]
The address of the signal line is designated by the X address decoder 204, and the video signal 211 is supplied to the X address of the designated signal line by the video signal output means 205. The video signal is input to the video signal output means in accordance with the order of pixels to be selected.
[0098]
Based on the output Y address data, the first Y address decoder 206 outputs an output pulse to the output terminal of the designated Y address decoder. The first level shifter 207 amplifies the voltage value of the output pulse output from the first Y address decoder and sets the first scanning line to the gate potential.
[0099]
The second scanning line becomes the gate potential by the second Y address decoder 208 and the second level shifter 209.
[0100]
In this way, the same potential of the signal voltage is simultaneously applied to the first pixel TFT connected to the signal line and the first scanning line and to the second pixel TFT connected to the signal line and the second scanning line.
[0101]
The operation of the circuit of the present embodiment is almost the same as that described in the second embodiment with reference to FIG. The difference is that, in the second period 901, the comparison means detects the address of the pixel displaying the approximate gradation connected to the same signal line when forming the image of the first subframe period. It is.
[0102]
Of course, by changing the circuit configuration, three or more pixel TFTs connected to the same signal wiring and displaying the same or similar gradation level can be selected at the same time.
[0103]
According to this embodiment, the sum of the liquid crystal response time 303 and the standby time 301 can be shortened in the field sequential timing chart of FIG. it can.
[0104]
This embodiment can also be used in combination with the first to second embodiments. A signal line signal can be preferentially written to the pixel TFT of a pixel that takes a long response time, or a signal line signal can be simultaneously written to a pixel TFT of a pixel that exhibits the same or similar gradation.
[0105]
【Example】
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing the pixel TFT and the storage capacitor of the pixel portion and the TFT of the driver circuit provided in the periphery of the display region will be described in detail according to the process. The TFT of the driver circuit manufactured in this embodiment has high mobility of the semiconductor layer and is suitable for high-speed pixel data writing in the field sequential method.
[0106]
First, as shown in FIG. 8A, a silicon oxide film on a substrate 400 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass, A base film 401 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film 401a made of O is formed to 10 to 200 nm (preferably 50 to 100 nm) and similarly SiH _Four , N ₂ A silicon oxynitride silicon film 401b formed from O is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, the base film 401 is shown as a two-layer structure;
[0107]
The island-shaped semiconductor films 402 to 406 are formed using a crystalline semiconductor film formed by using a laser crystallization method or a known thermal crystallization method from a semiconductor film having an amorphous structure. The island-shaped semiconductor films 402 to 406 are formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.
[0108]
To produce a crystalline semiconductor film by laser crystallization, a pulsed or continuous-emitting excimer laser is used. _, Ar laser, Kr laser, YAG laser, YVO _Four Laser, YLF laser, YAlO _Three Laser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser is used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is condensed into a linear or elliptical shape by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz and the laser energy density is 100 to 400 mJ / cm. ² (Typically 200-300mJ / cm ² ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ) Then, laser light condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%.
[0109]
In order to obtain a crystal with a large grain size when crystallizing an amorphous semiconductor film, a solid-state laser capable of continuous oscillation is used, and the second to fourth harmonics of the fundamental wave are applied. preferable. Typically, Nd: YVO _Four A second harmonic (532 nm) or a third harmonic (355 nm) of a laser (fundamental wave 1064 nm) is applied.
[0110]
Furthermore, the continuous oscillation YVO with an output of 10W _Four The laser light emitted from the laser is converted into harmonics by a non-linear optical element, or YVO is placed in the resonator. _Four A method of inserting a crystal and a nonlinear optical element and emitting harmonics may be used. Preferably, a laser beam having a rectangular or elliptical shape is formed on the irradiation surface by an optical system, and the object to be processed is irradiated. The energy density at this time is 0.01 to 100 MW / cm. ² Degree (preferably 0.1-10 MW / cm ² )is required. Then, irradiation is performed by moving the substrate relative to the laser light at a speed of about 0.5 to 2000 cm / s.
[0111]
Next, a gate insulating film 407 that covers the island-shaped semiconductor films 402 to 406 is formed. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 120 nm is formed. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0112]
Then, a first conductive film 408 and a second conductive film 409 for forming a gate electrode are formed over the gate insulating film 407. In this embodiment, the first conductive film 408 is formed with TaN to a thickness of 50 to 100 nm, and the second conductive film 409 is formed with W to a thickness of 100 to 300 nm.
[0113]
When forming a W film, it is formed by sputtering using W as a target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Therefore, in the case of sputtering, the resistivity is obtained by using a W target with a purity of 99.9999% and forming a W film with sufficient consideration so that impurities are not mixed in the gas phase during film formation. 9-20 μΩcm can be realized.
[0114]
Note that in this embodiment, the first conductive film 408 is TaN and the second conductive film 409 is W, but any of these elements selected from Ta, W, Ti, Mo, Al, and Cu, or the above elements You may form with the alloy material or compound material which has as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a combination other than the present embodiment, the first conductive film is made of tantalum (Ta), the second conductive film is made of W, the first conductive film is made of tantalum nitride (TaN), and the first conductive film is made of tantalum nitride (TaN). There are combinations in which the second conductive film is made of Al, the first conductive film is made of tantalum nitride (TaN), and the second conductive film is made of Cu.
[0115]
Next, resist masks 410 to 415 are formed, and a first etching process for forming electrodes and wirings is performed. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, an etching gas is mixed, and 500 W of RF (13.56 MHz) power is applied to a coil electrode at a pressure of 1 Pa to generate plasma. Generate and do. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. By appropriately selecting the etching gas, the W film and the TaN film are etched to the same extent.
[0116]
Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer have an angle of taper of 15 due to the effect of the bias voltage applied to the substrate side. It becomes a taper shape of ˜45 °. In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 417 to 422 (the first conductive layers 417 a to 422 a and the second conductive layers 417 b to 422 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 416 denotes a gate insulating film, and a region not covered with the first shape conductive layers 417 to 422 is etched and thinned by about 20 to 50 nm.
[0117]
Then, a first doping process is performed, and an impurity element imparting n-type conductivity is added. (FIG. 8B) The doping may be performed by ion doping or ion implantation. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁴ /cm ² The acceleration voltage is set to 60 to 100 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 417 to 420 serve as a mask for the impurity element imparting n-type, and the first impurity regions 423 to 426 are formed in a self-aligning manner. The first impurity regions 423 to 426 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} /cm ^Three An impurity element imparting n-type is added in a concentration range of.
[0118]
Next, a second etching process is performed as shown in FIG. Using an ICP etching method, a reactive gas is introduced into the chamber, a predetermined RF power (13.56 MHz) is supplied to the coil-type electrode, and plasma is generated. Lower RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. The W film is anisotropically etched to obtain second shape conductive layers 427 to 432.
[0119]
Further, a second doping process is performed as shown in FIG. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is 70 to 120 keV and 1 × 10 ¹³ /cm ² A new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor film in FIG. 8B. Doping is performed using the second shape conductive layers 427 to 430 as masks against the impurity elements so that the impurity elements are also added to the lower regions of the first conductive layers 427 a to 430 a. In this manner, second impurity regions 433 to 437 overlapping with the first conductive layers 427a to 430a are formed. The impurity element imparting n-type conductivity is 1 × 10 6 in the second impurity region. ¹⁷ ~ 1x10 ¹⁸ /cm ^Three So that the concentration becomes.
[0120]
As shown in FIG. 9A, by etching the gate insulating film 416, TaN which is the first conductive layer is etched and receded at the same time, so that the third shape conductive layers 438 to 443 (first conductive layer) 438a to 443a and second conductive layers 438b to 443b) are formed. Reference numeral 444 denotes a gate insulating film, and a region not covered with the third shape conductive layers 438 to 443 is further etched by about 20 to 50 nm to form a thinned region.
[0121]
In FIG. 9A, third impurity regions 445 to 449 overlapping with the first conductive layers 438a to 441a and fourth impurity regions 450 to 454 outside the third impurity region are formed. Accordingly, the concentration of the impurity element imparting n-type in the third impurity region and the fourth impurity region is substantially equal to the concentration of the impurity element imparting n-type in the second impurity region.
[0122]
Then, as shown in FIG. 9B, fourth impurity regions 458 to 461 having a conductivity type opposite to the one conductivity type are formed in the island-shaped semiconductor films 403 and 406 forming the p-channel TFT. Using the third shape conductive layers 439 and 441 as a mask for the impurity element, impurity regions are formed in a self-aligning manner. At this time, the island-like semiconductor films 402, 404, and 405 that form the n-channel TFT are covered with resist masks 455 to 457. Phosphorus is added to the impurity regions 458 to 461 at different concentrations, but diborane (B ₂ H ₆ The impurity concentration is 2 × 10 2 in any region by ion doping using ²⁰ ~ 2x10 ^{twenty one} /cm ^Three To be.
[0123]
Through the above steps, an impurity region is formed in each island-like semiconductor film. Conductive layers (conductive layers for forming a gate electrode) 438 to 441 overlapping with the island-shaped semiconductor film function as the gate electrode of the TFT. Reference numeral 442 functions as a source wiring, and 443 functions as a wiring in the driver circuit.
[0124]
Thus, for the purpose of controlling the conductivity type, as shown in FIG. 9C, a step of activating the impurity element added to each island-like semiconductor film is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this example, the temperature is 500 ° C. for 4 hours. Heat treatment is performed. However, when the wiring material used for 438 to 443 is weak against heat, activation is preferably performed after an interlayer insulating film (having silicon as a main component) is formed in order to protect the wiring and the like.
[0125]
Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor film. This step is a step of terminating dangling bonds in the semiconductor film with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0126]
Then, as shown in FIG. 10, a first interlayer insulating film 472 is formed of a silicon oxynitride film with a thickness of 100 to 200 nm. An acrylic resin film or a polyimide resin film having a thickness of 1.8 μm is formed thereon as a second interlayer insulating film 473 made of an organic insulating material. Next, an etching process for forming a contact hole is performed.
[0127]
Next, a conductive metal film is formed by sputtering or vacuum deposition. In this method, a Ti film is formed to a thickness of 50 to 150 nm, a contact is formed with a semiconductor film that forms a source region or a drain region of an island-like semiconductor film, and aluminum (Al) 300 is overlaid on the Ti film. A three-layer structure was formed by forming a Ti film or a titanium nitride (TiN) film with a thickness of 100 to 200 nm.
[0128]
Then, source wirings 474 to 476 that form contacts with the source region of the island-shaped semiconductor film and drain wirings 477 to 479 that form contacts with the drain region are formed in the driver circuit portion.
[0129]
In the pixel portion, a connection electrode 480, a gate wiring 481, a drain electrode 482, and an electrode 492 are formed.
[0130]
The connection electrode 480 is electrically connected to the source wiring 483 and the first semiconductor film 484. Although not shown, the gate wiring 481 is electrically connected to a conductive layer 485 forming a gate electrode through a contact hole. The drain electrode 482 is electrically connected to the drain region of the first semiconductor film 484. The electrode 492 is electrically connected to the second semiconductor film 493 so that the second semiconductor film 493 functions as an electrode of the storage capacitor 505.
[0131]
Thereafter, a transparent conductive film is formed over the entire surface, and a pixel electrode 491 is formed by patterning processing and etching processing using a photomask. The pixel electrode 491 is formed over the second interlayer insulating film 473, and a portion overlapping the drain electrode 482 and the electrode 492 of the pixel TFT is provided to form a connection structure.
[0132]
The material of the transparent conductive film is indium oxide (In ₂ O _Three ) Or indium tin oxide alloy (In ₂ O _Three -SnO ₂ ; ITO) or the like can be formed using a sputtering method, a vacuum deposition method, or the like. Etching treatment of such a material is performed with a hydrochloric acid based solution. However, in particular, etching of ITO is likely to generate a residue, so in order to improve etching processability, an indium oxide-zinc oxide alloy (In ₂ O _Three —ZnO) may also be used. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and thermal stability with respect to ITO, the corrosion reaction with Al contacting with the end face of the drain electrode 482 can be prevented. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.
[0133]
In this manner, an active matrix substrate corresponding to a transmissive liquid crystal display device can be completed.
[0134]
As described above, the driver circuit portion including the n-channel TFT 501, the p-channel TFT 502, and the n-channel TFT 503, and the pixel portion including the pixel TFT 504 and the storage capacitor 505 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0135]
The n-channel TFT 501 in the driver circuit portion includes a channel formation region 462, a third impurity region 445 (GOLD region) overlapping with the conductive layer 438 forming the gate electrode, and a fourth impurity region 450 (outside of the gate electrode). LDD region) and a first impurity region 423 functioning as a source region or a drain region. The p-channel TFT 502 includes a channel formation region 463, a fifth impurity region 446 that overlaps with the conductive layer 439 that forms a gate electrode, and a sixth impurity region 451 that functions as a source region or a drain region. The n-channel TFT 503 includes a channel formation region 464, a third impurity region 447 (GOLD region) overlapping with the conductive layer 440 forming the gate electrode, and a fourth impurity region 452 (LDD region) formed outside the gate electrode. And a first impurity region 425 functioning as a source region or a drain region.
[0136]
The pixel TFT 504 in the pixel portion includes a channel formation region 465, a third impurity region 448 (GOLD region) overlapping with the conductive layer 485 forming the gate electrode, and a fourth impurity region 453 (LDD region) formed outside the gate electrode. ) And a first impurity region 426 functioning as a source region or a drain region. In addition, an impurity element imparting p-type conductivity is added to the semiconductor film 493 functioning as one electrode of the storage capacitor 505. A storage capacitor is formed by the conductive layer 485 forming the gate electrode and the insulating layer therebetween (the same layer as the gate insulating film).
[0137]
11 corresponds to the cross section cut along the chain lines AA ′ and BB ′ in FIG. 10. The cross section taken along the chain lines AA ′ and BB ′ in FIG. In FIG. 11, reference numerals 801 to 805 denote contact holes.
[0138]
An active matrix substrate of a reflective liquid crystal display device can be manufactured by using the drain electrode of this embodiment as a conductive film having reflectivity and a function as a pixel electrode.
[0139]
[Example 2]
In this embodiment, a method for manufacturing a liquid crystal display device used for a field sequential method is illustrated. FIG. 12 shows a liquid crystal display device using TFT elements as switching elements.
[0140]
A light shielding film (not shown) is formed on the substrate 508 of the counter substrate. Chrome (Cr) or the like can be used for the light shielding film. The thickness of the light shielding film is desirably 100 nm to 200 nm. The light shielding film is provided in a region where liquid crystal alignment failure occurs, and suppresses a decrease in contrast due to liquid crystal alignment failure.
[0141]
A transparent conductive film 510 is formed on the light shielding film. As the transparent conductive film, an indium tin oxide (ITO) film can be used. In order to keep the visible light transmittance high, the thickness of the ITO film is desirably 100 nm to 120 nm.
[0142]
Alignment films 511 to 512 are formed on the active matrix substrate and the counter substrate. The thickness of the alignment film is preferably 30 nm to 80 nm. For example, SE7792 manufactured by Nissan Chemical Co., Ltd. can be used as the alignment film. When an alignment film having a high pretilt is used, the occurrence of disclination can be suppressed when the liquid crystal display device is driven by an active matrix method.
[0143]
The alignment films 511 to 512 are rubbed.
[0144]
Although not shown, it is possible to improve the uniformity of the cell gap by providing spacers in the pixels by scattering or patterning. In this embodiment, in order to increase the response speed of the liquid crystal, the height of the electric field when driving the liquid crystal is increased by setting the spacer to a height of 1.0 μm.
[0145]
The counter substrate and the active matrix substrate are bonded to each other with the sealant 513. The counter substrate and the active matrix substrate are bonded so that the rubbing directions of the alignment films formed on these substrates are orthogonal to each other. The sealing agent is a UV curable sealing agent and XNR5610-1H1 manufactured by Mitsui Toatsu Co., Ltd. is used. Into the sealant, a brass ball made by Catalytic Chemical Co., which is a silica-based spacer, is placed. The diameter of the true sphere is 1.0 μm. After the sealant is cured, the counter substrate and the active matrix substrate are separated.
[0146]
Liquid crystal material 514 is injected. As the liquid crystal material, a low-viscosity material is desirable in terms of high-speed response. In this embodiment, a nematic liquid crystal with easy alignment control is used to add TN (Twisted Nematic) alignment by adding a chiral material. Of course, a ferroelectric liquid crystal or an antiferroelectric liquid crystal capable of high-speed response may be used. In the present invention, it is desirable to select a liquid crystal capable of displaying in analog gradation for both the ferroelectric liquid crystal and the anti-ferroelectric liquid crystal. It is also possible to use a material obtained by adding a polymer resin to a ferroelectric liquid crystal or antiferroelectric liquid crystal and curing a ferroelectric liquid crystal or a mixed system of an antiferroelectric liquid crystal and a polymer resin by light irradiation. . A method of aligning this polymer material by adding a polymer resin to a ferroelectric liquid crystal or an anti-ferroelectric liquid crystal is called a polymer stabilization method.
[0147]
After confirming that the liquid crystal material has been injected, the injection port is sealed with a UV curable sealant.
[0148]
Next, a polarizing plate (not shown) is attached by a known technique. The liquid crystal display device is completed through the above steps.
[0149]
[Example 3]
The liquid crystal display device formed by implementing any one of the first to second embodiments can be used for various electro-optical devices. That is, the present invention can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.
[0150]
Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) and the like. . Examples of these are shown in FIGS.
[0151]
FIG. 13A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the display portion 2003.
[0152]
FIG. 13B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be applied to the display portion 2102.
[0153]
FIG. 13C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205.
[0154]
FIG. 13D shows a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302.
[0155]
FIG. 13E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, operation switches 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.
[0156]
FIG. 13F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502.
[0157]
FIG. 14A shows a cellular phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, and the like. The present invention can be applied to the display portion 2904.
[0158]
FIG. 14B illustrates a portable book (electronic book) which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003.
[0159]
FIG. 14C illustrates a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103.
[0160]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-2.
[0161]
【The invention's effect】
By implementing the present invention, the response time of the field sequential type liquid crystal and the writing time of pixel data can be shortened. Thereby, a bright display with a long lighting time of the light source can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a circuit configuration of a driving method of a liquid crystal display device according to the present invention.
FIG. 2 is a diagram showing an example of a timing chart of a method for driving a liquid crystal display device according to the present invention.
FIG. 3 is a diagram showing an example of a timing chart of a method for driving a liquid crystal display device according to the present invention.
FIG. 4 is a diagram showing an example of a timing chart of a method for driving a liquid crystal display device according to the present invention.
FIG. 5 is a diagram showing an example of a circuit configuration of a method for driving a liquid crystal display device according to the present invention.
FIG. 6 is a diagram showing an example of a timing chart of a method for driving a liquid crystal display device according to the present invention.
FIG. 7 is a diagram illustrating an example of a timing chart when color display is performed by a field sequential method.
8 is a cross-sectional view showing a method for manufacturing an active matrix substrate (Example 1). FIG.
9 is a cross-sectional view showing a method for manufacturing an active matrix substrate (Example 1). FIG.
10 is a cross-sectional view showing a method for manufacturing an active matrix substrate (Example 1). FIG.
FIG. 11 is a top view showing a pixel portion of an active matrix substrate (Example 1).
FIG. 12 is a cross-sectional view of a liquid crystal display device (Example 2).
FIG. 13 is a diagram illustrating an example of an electronic apparatus (third embodiment).
FIG. 14 is a diagram illustrating an example of an electronic apparatus (third embodiment).

Claims (7)

A plurality of pixels;
First storage means for storing a potential of a first signal voltage applied to a pixel electrode included in one of the plurality of pixels in a frame period;
Second storage means for storing a potential of a second signal voltage applied to the pixel electrode in a frame period next to the frame period;
Means for comparing a potential difference between the potential of the first signal voltage and the potential of the second signal voltage ;
The display device, wherein the second signal voltage is sequentially input to the pixel electrode from the pixels with the large potential difference compared . A plurality of pixels;
First storage means for storing a potential of a first signal voltage applied to a pixel electrode included in one of the plurality of pixels in a certain frame period;
Second storage means for storing a potential of a second signal voltage applied to the pixel electrode in a frame period next to the frame period;
And means for calculating the response time of the display element when changing to the potential of the second signal voltage from the potential of said first signal voltage,
Sequentially from a long the pixel of the computed the response time, a display device, characterized in that the said pixel electrode second signal voltage is input. In claim 2,
The display device includes a liquid crystal. In claim 1 or claim 2 ,
Each of the plurality of pixels is controlled by a plurality of signal lines and a plurality of scanning lines,
Drive circuit for controlling said plurality of signal lines have a address decoder,
The driver circuit for controlling the plurality of scanning beam display apparatus, characterized by chromatic address decoder. An electronic apparatus comprising: the display device according to claim 1; and an operation switch. Having a plurality of pixels,
Storing a potential of a first signal voltage applied to a pixel electrode included in one of the plurality of pixels in a certain frame period;
Storing a potential of a second signal voltage applied to the pixel electrode in a frame period next to the frame period;
Comparing the potential difference between the potential of the first signal voltage and the potential of the second signal voltage;
A method of driving a display device, comprising: sequentially selecting the pixels having the large potential difference compared to each other and inputting the second signal voltage to the pixel electrode. Having a plurality of pixels,
Storing a potential of a first signal voltage applied to a pixel electrode included in one of the plurality of pixels in a certain frame period;
Storing a potential of a second signal voltage applied to the pixel electrode in a frame period next to the frame period;
Calculating a response time of the display element when changing from the potential of the first signal voltage to the potential of the second signal voltage;
A method of driving a display device, comprising: sequentially selecting the calculated pixels having a long response time and inputting the second signal voltage to the pixel electrode.

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