JP2002171159A - Comparator and light receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparator in which influence of noise input is reduced by setting a hysteresis width to be wide when a signal is not present, and sensitivity is improved by setting the hysteresis width to be wide when a signal is inputted. SOLUTION: This comparator is equipped with a differential amplifier for amplifying a differential voltage ΔV(=VA-VB) as far as a level where a logic level can be judged, a comparing means 2 provided with a hysteresis circuit which can set two hysteresis widths (ΔVa, ΔVb) shown by figures (b) and (c) with respect to the differential voltage ΔV(=VA-VB), and a logic pattern detecting means 3 constituted of a counter, a storage device, a referring circuit, etc. When a detection pattern which is set previously in the storage device is detected from a fixed logic pattern of the head of a pulse train of output voltage VO supplied from the comparing means 2, the logic pattern detecting means 3 supplies a switching signal VS and performs controlling so as to switch over the hysteresis width of the hysteresis circuit of the comparing means 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator and an optical receiving circuit for minimizing the influence of noise when there is no signal and realizing high sensitivity when a signal is input.

[0002]

2. Description of the Related Art A conventional comparator is disclosed in
As used in the optical receiving circuit disclosed in Japanese Patent Application Laid-Open No. 853737, the potential difference between two input signals is amplified until the logical level can be determined, and the output voltage is not affected by the noise input during the non-signal input period. In order to prevent the output voltage from becoming stable, there is known an output voltage having a hysteresis characteristic with respect to a potential difference between two input signals.

FIG. 11 shows a configuration example of a conventional comparator. (A) shows a symbol diagram of a conventional comparator,
(B) shows an output voltage characteristic diagram with respect to a potential difference between two input signals. (A) In FIG.
0 has two input terminals X and Y and one output terminal Z, and has a deviation voltage ΔV between a first signal VX input to the input terminal X and a second signal VY input to the input terminal Y ( = VX-
VY) is amplified until the logic level can be determined, and comparison means 51 having hysteresis characteristics with respect to the deviation voltage is provided.

The output voltage VZ of the comparing means 51 increases as the deviation voltage ΔV (= VX−VY) increases from minus (−) to 0 (VX = VY) as shown in FIG. When the threshold value (VX> VY) of (+) is reached, the logic level is changed from the logic level VL (for example, ground potential 0 V) to the logic level VH.
(↑ direction: power supply voltage 5 V, for example). Also,
The output voltage VZ maintains the logical level VH (→ direction: for example, the power supply voltage 5 V) even if the deviation voltage ΔV (= VX−VY) further increases to plus (+).

On the other hand, the output voltage VZ is equal to the deviation voltage ΔV (=
(VX-VY) decreases and reaches the plus (+) threshold value, the logic level VH (← direction: for example, the power supply voltage 5 V) is maintained, and the state of the logic level VH is the deviation voltage ΔV.
(= VX−VY) further decreases below 0 (VX = VY), and a minus (−) threshold value (← direction: VX
<VY).

The output voltage VZ is equal to the deviation voltage ΔV (= VX−V
Y) is a minus (-) threshold value (VX <VY)
, The logic level changes from the logic level VH to the logic level VL (in the direction of ↓), and the logic level VL (in the direction of ←) is maintained even if the logic level decreases to minus (-).

As described above, the output voltage VZ has the hysteresis characteristic of the hysteresis width ΔVX, and when the deviation voltage ΔV (= VX−VY) within the hysteresis width ΔVX increases and decreases, the output voltage VZ is the same. Different logic levels (H
Or L).

FIG. 12 is a diagram for explaining the noise suppressing effect of the conventional comparator. (A) Hysteresis width is 0 in the figure.
Output voltage (VZ) characteristic diagram when (Δv = 0), (b)
The figure shows an output voltage (VZ) characteristic diagram when the hysteresis width is ΔVX. The description will be made with the first signal VX as an input signal and the second signal VY as a reference voltage.

In FIG. 1A, during the non-signal input period, there is no signal component of the first signal VX, only the noise component VN is input, and the deviation voltage ΔV of the comparator 50 is (VN−V
Y) and the hysteresis width is 0, so the output voltage VZ
Indicates that the deviation voltage ΔV (= VN−VY) exceeds 0 (ΔV>
0) and the logic level VL (for example, ground potential 0 V) to the logic level VH (for example, power supply voltage 5 V).
The deviation voltage ΔV (= VN−VY) falls below 0 (ΔV <0)
From the logic level VH to the logic level VL, the influence of the noise component VN appears on the output voltage VZ, and the output voltage VZ becomes unstable.

On the other hand, in FIG. 2B, when the hysteresis width ΔVX is set, even if the noise component VN is input during the non-signal input period, the deviation voltage ΔV (= V
If (N−VY) is within the hysteresis width ΔVX (ΔVX ≧ ΔV), the effect of the noise component VN on the output voltage VZ is completely suppressed.

As described above, the conventional comparator has a hysteresis characteristic, and by setting the hysteresis width larger than the noise component during the no-signal input period, the influence of the noise component on the output voltage is completely suppressed.

[0012]

Since the conventional comparator has a hysteresis characteristic, the influence of the noise component VN during the non-signal input period can be suppressed. However, if the hysteresis width .DELTA.VX is set wide, the signal input period can be reduced. When the first signal VX is small, there is a problem that an output voltage VZ corresponding to the signal VX cannot be obtained, that is, a so-called sensitivity drop occurs.

The present invention has been made to solve such a problem. A first object is to set the hysteresis width wide when there is no signal to suppress the influence of noise input, and to reduce the hysteresis width when a signal is input. An object of the present invention is to provide a comparator which can achieve high sensitivity by setting the width narrowly.

It is a second object of the present invention to provide an optical receiving circuit which can suppress the influence of noise input and increase the sensitivity by applying the comparator of the present invention.

[0015]

In order to solve the above-mentioned problems, a comparator according to the present invention detects a logical pattern of an output voltage from a comparing means, and when the detected logical pattern matches a predetermined inspection pattern. Is characterized by comprising a logical pattern detecting means for outputting a switching signal and controlling the switching of the hysteresis width.

The comparator according to the present invention includes a logic pattern detecting means, detects the signal input period from the logic pattern of the output voltage, and outputs a switching signal to control the switching of the hysteresis width. The hysteresis width of the comparing means is set relatively wide during the input period to suppress the influence of noise, and the hysteresis width of the comparing means is set narrow during the signal input period, thereby realizing high sensitivity.

Further, the logic pattern detecting means according to the present invention comprises reset means, and when the reset signal is supplied, returns the switching signal to the initial setting state.

The logic pattern detecting means according to the present invention comprises:
A reset means is provided, and when the reset signal is supplied, the switching signal is returned to the initial setting state, so that the hysteresis width can be set wide and the influence of noise input during the no-signal input period can be suppressed.

Further, the comparator according to the present invention comprises:
A timer is provided which starts timing by using the switching signal as a trigger and supplies a reset signal to the reset means when a predetermined time is counted.

The comparator according to the present invention is provided with timer means, starts time measurement with a switching signal as a trigger, and supplies a reset signal to the reset means when a certain time is measured. The hysteresis width can be set wide to suppress the influence of noise input.

Further, the comparator according to the present invention includes a reset logic pattern detecting means for detecting a reset logic pattern of the output voltage and supplying a reset signal to the reset means.

The comparator according to the present invention includes reset logic pattern detection means, which detects a reset logic pattern of the output voltage and supplies a reset signal to the reset means. By setting the width to be wide, the influence of noise input can be suppressed.

Further, the light receiving circuit according to the present invention comprises: a light receiving element for converting an optical signal into an electric signal; and an intermediate potential generating means for generating an intermediate value signal between a peak value and a bottom value of a voltage signal corresponding to the electric signal. A voltage signal corresponding to the electric signal as a first signal, an intermediate value signal generated by the intermediate potential generating means as a second signal, and a deviation voltage between the first signal and the second signal as a logical level. Amplify until it can be determined, a comparison means having a hysteresis characteristic with respect to the deviation voltage, a logic pattern of the output voltage from the comparison means is detected, and when this logic pattern matches a previously set inspection pattern, And a comparator having a logic pattern detecting means for controlling the switching of the hysteresis width by outputting a switching signal.

The light receiving circuit according to the present invention includes a light receiving element, an intermediate potential generating means, a comparing means having a hysteresis characteristic, and a comparator having a logic pattern detecting means. It detects the data signal input period from the logic pattern of the output voltage corresponding to the deviation voltage from the intermediate value signal of the voltage signal, and outputs the switching signal to control the switching of the hysteresis width. By setting the hysteresis width of the comparison means to be narrow, high sensitivity can be realized.

[0025]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a basic block diagram of a first embodiment of a comparator according to the present invention. (A) is a basic block configuration diagram, (b) is an output voltage (VO) characteristic diagram of a hysteresis width (ΔVa) corresponding to a no signal input period, and (c) is a hysteresis width (hysteresis width corresponding to a signal input period). FIG. 11 is an output voltage (VO) characteristic diagram of ΔVb).

In FIG. 1A, a comparator 1 includes a comparing means 2 and a logical pattern detecting means 3. The comparing means 2 has two input terminals A and B, an output terminal C and a hysteresis width switching terminal D, and a first signal VA input to the input terminal A and a second signal input to the input terminal B. A differential amplifier for amplifying the deviation voltage ΔV of VB (= VA−VB) until the logical level can be determined;
−VB) is provided with a hysteresis circuit capable of setting two hysteresis widths (ΔVa, ΔVb) shown in FIGS. Note that an 8-bit fixed logical pattern of, for example, "10101010" indicating that the data signal is a data signal is added to the beginning of the data signal that is the first signal VA.

The logic pattern detecting means 3 comprises a counter, a memory, a collating circuit, etc., and has a logic level VH (for example, a power supply voltage of 5 V) of the output voltage VO supplied from the comparing means 2.
And a fixed logical pattern (for example, “1010101
0), a detection pattern set in the memory in advance (for example, a 6-bit logic pattern of “101010”) is detected, the output voltage VO is determined to be in the data signal input period, and the hysteresis width switching terminal D is determined. (E.g., a logic level VH), and controls the hysteresis width of the hysteresis circuit of the comparison means 2 to switch from the hysteresis width ΔVa shown in (b) to the hysteresis width ΔVb shown in (c). . When the switching signal VS is at the logic level VL, the hysteresis width ΔVa is set to be relatively wide, and when the switching signal VS is at the logic level VH, the hysteresis width ΔVb is set to be narrow.

The output voltage VO increases as the deviation voltage ΔV (= VA−VB) from minus (−) to 0 (VA = VB) as shown in FIG. When a positive (+) threshold value (VA> VB) is reached, a transition is made from the logic level VL (→ direction: for example, ground potential 0 V) to the logic level VH (↑ direction: for example, power supply voltage 5 V). The output voltage VO is equal to the deviation voltage ΔV (= VA−V
Even if B) further increases to plus (+), the logic level VH
(→ direction: for example, power supply voltage 5V) is maintained.

On the other hand, the output voltage VO is equal to the deviation voltage ΔV (=
VA−VB) decreases and reaches a plus (+) threshold value, the logic level VH (← direction: for example, the power supply voltage 5 V) is maintained, and the state of the logic level VH is the deviation voltage ΔV.
(= VA−VB) further decreases and falls below 0 (VA = VB), and is maintained (← direction) to a minus (−) threshold value (VA <VB).

The output voltage VO is equal to the deviation voltage ΔV (= VA−V
B) is a minus (-) threshold value (VA <VB)
, The signal transits from the logic level VH to the logic level VL (in the direction of ↓), and maintains the logic level VL (in the direction of ←) even if the logic level decreases to minus (-). The difference between (b) and (c) is that hysteresis widths ΔVa and ΔVb (ΔVa> ΔVb), which are differences between a plus (+) threshold value and a minus (−) threshold value, are different.

FIG. 2 is an explanatory diagram of the operation of the comparator of FIG. FIG. 2 shows the first signal V in the non-signal input period, the fixed pattern signal input period, and the data signal input period.
A (hereinafter, signal VA), the second signal V as a reference level
B (hereinafter, signal VB), hysteresis widths ΔVa, ΔVb, output voltage VO, and change in state of the switching signal VS.

First, during the no-signal input period, the signal VA input to the input terminal A is 0, and only the noise component VN is input. On the other hand, since a hysteresis width ΔVa wider than the amplitude of the noise component VN is set centering on the signal VB (reference level), the output voltage VO is not affected by the noise component VN and has a stable logic level VL (for example, 0
V). On the other hand, the switching signal VS is also at the initial logical level VL, and the hysteresis width is set to ΔVa.

Subsequently, in the fixed pattern signal input period,
The signal VA input to the input terminal A is a digital signal of an 8-bit fixed logic pattern “10101010”, and the amplitude of this digital signal exceeds the hysteresis width ΔVa. 10101
010 "and a fixed pulse train of a logic level VL (corresponding to the fixed pattern" 1 ") and a logic level VL (corresponding to the fixed pattern" 0 ").

On the other hand, the logical pattern detecting means 3 outputs a fixed pulse train of the output voltage VO (fixed logical pattern signal "1010101
0 ") with a detection pattern (for example, a 6-bit" 101010 "logical pattern) set in the memory in advance,
When the 6-bit “101010” pattern is detected, the setting signal is changed from the wide hysteresis width ΔVa to the narrow hysteresis width ΔVb by supplying the switching signal VS of the logic level VH to the hysteresis width switching terminal D.

During the data signal input period, the data signal VA input to the input terminal A following the fixed logic pattern signal "10101010" is detected with a narrow hysteresis width ΔVb, and the data output voltage VO corresponding to the data signal VA is detected. Is output. Since the narrow hysteresis width ΔVb is set during the input period of the data signal VA, the data signal VA having a small level can be detected, and the sensitivity can be increased.

As described above, the comparator 1 according to the present invention includes the logical pattern detecting means 3, detects the signal input period from the logical pattern of the output voltage VO, outputs the switching signal VS, and outputs the switching signal VS. ΔVa → ΔVb)
Is controlled, the hysteresis width of the comparison means 2 is set relatively wide (ΔVa) during the no-signal input period to suppress the influence of noise, and the hysteresis width of the comparison means 2 is reduced during the signal input period. (ΔVb) can be set to realize high sensitivity.

FIG. 3 shows a second embodiment of the comparator according to the present invention.
FIG. 3 is a basic block configuration diagram of the embodiment. 3, the comparator 4 includes a comparison unit 2, a logic pattern detection unit 5, and a reset terminal E. The difference from the comparator 1 of FIG. 1 lies in that a logic pattern detecting means 5 and a reset terminal E are provided.

The logic pattern detection means 5 includes a reset circuit. When a reset signal VR is supplied from the reset terminal E, the logic pattern detection means 5 outputs the switching signal VS, which has reached the logic level VH during the data signal input period, to the logic during the no signal input period. The level is returned to the level VL, and control is performed to switch the hysteresis width ΔVb to the initially set hysteresis width ΔVa.

FIG. 4 is a diagram for explaining the operation of the comparator shown in FIG. FIG. 4 shows a signal VA, a signal VB as a reference level, a hysteresis width ΔVa, ΔV in a non-signal input period, a fixed pattern signal input period, and a data signal input period.
b, state changes of the output voltage VO, the switching signal VS, and the reset signal VR.

In FIG. 4, the first non-signal input period, fixed pattern signal input period, and data signal input period have been described with reference to FIG. 2 and will be omitted.

When the data signal input period ends and the non-signal input period starts, the signal VA becomes 0 again and only the noise component VN is input, and the switching signal VS is at the logic level VH, and the hysteresis width Is continuously set to ΔVb during the data signal input period. If the amplitude of the noise component VN is larger than the hysteresis width ΔVb, unnecessary output is generated due to noise, and the output voltage VO becomes unstable.

In order to eliminate such instability of the output voltage VO, when a reset signal VR of a logic level VH having a pulse width TR is applied to the reset terminal E, the reset circuit of the logic pattern detecting means 5 operates and the switching signal VS is changed from the logic level VH to the logic level VL to drive the hysteresis circuit of the comparison means 2 to change the hysteresis width from ΔVb to ΔVb.
Change the setting to Va.

Therefore, after the reset signal VR is applied, the influence of noise is suppressed by the hysteresis width ΔVa wider than the amplitude of the noise component VN, and the output voltage VO
Becomes stable.

As described above, the logic pattern detecting means 5 according to the present invention includes the reset means, and includes the reset signal VR.
Is supplied, the switching signal VS is returned to the initial setting state, so that the hysteresis width can be set wide (.DELTA.Va) to suppress the influence of noise input during the non-signal input period.

FIG. 5 shows a third embodiment of the comparator according to the present invention.
FIG. 3 is a basic block configuration diagram of the embodiment. 5, the comparator 6 includes a comparison unit 2, a logic pattern detection unit 5, a timer unit 7, and a reset terminal E.
The difference from the comparator 4 in FIG. 3 is that a timer means 7 is provided.

The timer means 7 includes a timer for measuring a predetermined time T triggered by the rise of the logic level VH of the switching signal VS, and a single pulse generator for generating a reset signal VR having a pulse width TR when the predetermined time T has elapsed. The reset signal VR is supplied to the logic pattern detection means 5 via the reset terminal E after a lapse of a predetermined time T from the output of the switching signal VS of the logic level VH from the logic pattern detection means 5.

As a result, the switching signal VS of the logic pattern detecting means 5 is changed from the logic level VH to the logic level VL, and the hysteresis circuit of the comparing means 2 is driven to change the hysteresis width from ΔVb to ΔVa.

FIG. 6 is an explanatory diagram of the operation of the comparator shown in FIG. FIG. 6 shows a signal VA, a signal VB as a reference level, a hysteresis width ΔVa, ΔV in a non-signal input period, a fixed pattern signal input period, and a data signal input period.
b, state changes of the output voltage VO, the switching signal VS, and the reset signal VR.

In FIG. 6, when the switching signal VS of the logic level VH is output from the logic pattern detecting means 5 during the fixed pattern signal input period, the rising of the switching signal VS triggers the timer means 7 to start timing. , A fixed time T from the end of the data signal input period to the start of the no-signal input period.
Is generated, a reset signal VR of the logic level VH of the pulse width TR is generated, and the switching signal VS of the logic level VH is set to the logic level VL in the initial state.

When the switching signal VS is at the logic level VH, the hysteresis width is narrow ΔVb, and when the switching signal VS is at the logic level VL, the hysteresis width is wide ΔVa. When the transition is made, the hysteresis width ΔVa is automatically set to suppress the influence of noise to stabilize the output voltage VO.

As described above, the comparator 6 according to the present invention is provided with the timer means 7 and starts counting time with the switching signal VS as a trigger. When the predetermined time T is counted, the reset signal VR is supplied to the reset means. The hysteresis width is automatically set to be wide (ΔVa) automatically corresponding to the signal input period, so that the influence of noise input can be suppressed.

FIG. 7 shows a fourth embodiment of the comparator according to the present invention.
FIG. 3 is a basic block configuration diagram of the embodiment. 7, the comparator 8 includes a comparison unit 2, a logic pattern detection unit 5, a reset logic pattern detection unit 9, and a reset terminal E. Note that the comparator 4 in FIG.
The difference is that reset logic pattern detection means 9 is provided.

The reset logic pattern detecting means 9 comprises a counter, a memory, a collating circuit, a single pulse generator and the like, and outputs a logic level VH of the output voltage VO (for example, the power supply voltage 5
V) and a fixed logic pattern at the end of the pulse train of the logic level VL (for example, ground potential 0 V) (for example, a logic pattern of "11011011" of 8 bits), a detection pattern (for example, "110110" of 6 bits) set in the memory in advance. When a "logic pattern" is detected, it is determined that the data signal VA of the output voltage VO is at the end point, and a reset signal VR having a pulse width TR and a logic level VH is provided to the reset terminal E.

With the reset signal VR of the logic level VH,
The switching signal VS of the logical pattern detecting means 5 is changed to the logical level VH.
To the logic level VL, and drives the hysteresis circuit of the comparison means 2 to change the hysteresis width from ΔVb to ΔVa.

FIG. 8 is a diagram for explaining the operation of the comparator shown in FIG. FIG. 8 shows the signal VA, the signal VB as a reference level, the hysteresis widths ΔVa and ΔVb, the output voltage VO, the switching in the non-signal input period, the fixed pattern signal input period 1, the data signal input period and the fixed pattern signal input period 2. The state change of the signal VS and the reset signal VR is shown. Note that the fixed pattern signal input period 1 and the fixed pattern signal input period 2 represent periods in which the leading fixed logical pattern and the trailing fixed logical pattern (reset logical pattern) of the data signal occur, respectively.

A detection pattern (reset logic pattern: for example, a 6-bit “110110” logical pattern) preset in the memory is detected from a fixed logic pattern at the end of the output voltage VO (for example, an 8-bit “11011010” logical pattern). Then, a reset signal VR having a pulse width TR and a logic level VH is provided to the reset terminal E.

When the reset signal VR of the logic level VH is provided, the switching signal VS supplied from the logic pattern detection means 5 changes from the logic level VH to the logic level VL, and the hysteresis circuit of the comparison means 2 is driven. The width switches from ΔVb to ΔVa.

Therefore, the fixed pattern signal input period 2
, The hysteresis width is set to a wide ΔVa, so that the noise component VN is suppressed and the output voltage VO becomes stable.

As described above, the comparator 8 according to the present invention includes the reset logic pattern detecting means 9 and detects the reset logic pattern of the output voltage VO to supply the reset signal VR to the reset means. , The hysteresis width is automatically set wide to suppress the influence of noise input.

FIG. 9 is a basic block diagram of an embodiment of the optical receiving circuit according to the present invention. 9, the light receiving circuit 11 includes a light receiving element PD, an amplifier 12, an intermediate potential generating unit 13, and the comparator 4 shown in FIG.

The light receiving element PD converts the optical signal hν into a current IP, and the amplifier 12 amplifies the voltage of the current IP by a signal VA.
It is supplied to the input terminal A of the comparator 4 and the intermediate potential generating means 13 as a (first signal).

The intermediate potential generating means 13 generates an intermediate value from the peak value and the bottom value of the signal VA, and generates an intermediate value signal VK
(Second signal) is supplied to the input terminal B of the comparator 4 as a reference signal. Since the intermediate value signal VK is generated based on the signal VA, it differs depending on changes in the signal VA (for example, when there is no signal and when a signal is input). The intermediate potential generating means 13 resets the intermediate value signal VK to an initial state by a reset signal VR supplied from the reset terminal E of the comparator 4.

The comparator 4 includes a comparing means 2, a logical pattern detecting means 5, and a reset terminal E. In addition,
The operation of the comparator 4 is the same as in FIGS. 3 and 4, and a description thereof will be omitted. Further, in the operation explanatory diagram of the comparator of FIG. 10, since the intermediate value signal VK as the reference signal is generated based on the signal VA, the non-signal input period,
The value of the intermediate value signal VK differs between the fixed pattern signal input period and the data signal input period.

As described above, the optical receiving circuit 1 according to the present invention
1 includes a light receiving element PD, an intermediate potential generating means 12, a comparing means 2 having a hysteresis characteristic, and a comparator 4 having a logic pattern detecting means 5, so that the optical signal h
The voltage signal VA corresponding to ν and the intermediate value signal V of the voltage signal VA
The detection of the data signal input period from the logic pattern of the output voltage VO corresponding to the deviation voltage (= VA−VK) from K, outputs the switching signal VS, and outputs the hysteresis widths ΔVa, ΔV.
Since the switching of b is controlled, the sensitivity can be increased by setting the hysteresis width of the comparison means 2 narrow during the data signal input period.

In this embodiment, the comparator 4 shown in FIG. 3 is applied to the optical receiving circuit. However, the comparator 1 shown in FIG. 1, the comparator 6 shown in FIG. 3, or the comparator 8 shown in FIG. 7 is applied. Has the same effect.

[0066]

As described above, the comparator according to the present invention includes the logic pattern detecting means, and detects the signal input period from the logic pattern of the output voltage.
Since the switching signal is output to control the switching of the hysteresis width, the hysteresis width of the comparison means is set relatively wide during the non-signal input period to suppress the influence of noise,
During the signal input period, the hysteresis width of the comparison means is set to be narrow, so that high sensitivity can be realized.

Further, the optical receiving circuit according to the present invention includes the light receiving element, the intermediate potential generating means, the comparing means having hysteresis characteristics, and the comparator having the logic pattern detecting means. Detecting that it is a data signal input period from a logic pattern of an output voltage corresponding to a deviation voltage between the signal and the intermediate signal of the voltage signal
Since the switching of the hysteresis width is controlled by outputting the switching signal, the sensitivity can be increased by setting the hysteresis width of the comparing means to be narrow during the data signal input period.

[Brief description of the drawings]

FIG. 1 is a basic block diagram of a first embodiment of a comparator according to the present invention;

FIG. 2 is a diagram illustrating the operation of the comparator of FIG. 1;

FIG. 3 is a basic block configuration diagram of a comparator according to a second embodiment of the present invention;

FIG. 4 is a diagram illustrating the operation of the comparator in FIG. 3;

FIG. 5 is a basic block configuration diagram of a comparator according to a third embodiment of the present invention;

FIG. 6 is a diagram illustrating the operation of the comparator of FIG. 5;

FIG. 7 is a basic block diagram of a comparator according to a fourth embodiment of the present invention;

8 is an explanatory diagram of the operation of the comparator in FIG. 7;

FIG. 9 is a basic block configuration diagram of an embodiment of an optical receiving circuit according to the present invention;

FIG. 10 is an explanatory diagram of the operation of the comparator in FIG. 10;

FIG. 11 is a configuration example of a conventional comparator.

FIG. 12 is an explanatory diagram of a noise suppression effect of a conventional comparator.

[Explanation of symbols]

 1, 4, 6, 8 Comparator 2 Comparing means 3, 5 Logical pattern detecting means 7 Timer means 9 Reset logical pattern detecting means 11 Optical receiving circuit 12 Amplifier 13 Intermediate potential generating means PD Light receiving element

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 10/14 10/04 10/06 F term (Reference) 2G035 AC08 AD00 AD20 AD23 5J039 DA12 DB03 DB09 DB11 KK18 KK23 MM08 NN01 5K002 AA03 BA07 BA15 BA16 DA06

Claims (5)

[Claims] 1. A comparator comprising: a comparator that amplifies a deviation voltage between a first signal and a second signal until a logical level can be determined and has a hysteresis characteristic with respect to the deviation voltage. Logic pattern of the output voltage from the
A comparator, comprising: a logic pattern detection unit that outputs a switching signal when the detected logic pattern matches a previously set inspection pattern and controls switching of the hysteresis width. 2. The comparator according to claim 1, wherein said logic pattern detection means includes reset means, and returns a switching signal to an initial setting state when a reset signal is supplied. 3. A timer is started with a switching signal as a trigger,
2. The comparator according to claim 1, further comprising timer means for supplying a reset signal to said reset means when a predetermined time is counted. 4. The comparator according to claim 1, further comprising reset logic pattern detection means for detecting a reset logic pattern of an output voltage and supplying a reset signal to said reset means. 5. A light receiving element for converting an optical signal into an electric signal, an intermediate potential generating means for generating an intermediate value signal between a peak value and a bottom value of a voltage signal corresponding to the electric signal, and a voltage signal corresponding to the electric signal As a first signal, the intermediate value signal generated by the intermediate potential generating means as a second signal, and amplifying a deviation voltage between the first signal and the second signal until a logical level can be determined. Comparing means having a hysteresis characteristic with respect to the deviation voltage, detecting a logical pattern of an output voltage from the comparing means, and outputting a switching signal when the logical pattern matches a predetermined inspection pattern to output a hysteresis. An optical receiving circuit, comprising: a comparator having a logic pattern detecting unit for controlling width switching.