JP2002170936A - Method of manufacturing ferroelectric memory elements - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing ferroelectric memory elements which is suited for fine processing constituents of capacitor parts. SOLUTION: The method of manufacturing ferroelectric memory elements comprises steps: (a) of forming on the surface of a base a first region 54 having surface characteristics giving priority to depositing a material for forming a first electrode 32, and a second region 56 having surface characteristics hard to deposit the material for forming the first electrode 32, in such manner that the first region 54 is formed by charging the surface of the base or an upper layer of a substrate; and (b) of giving the material for forming the first electrode 32 to the base and selectively forming the members on the first region 54, by giving a material imparted with opposite charges to the first region 54 to form the first electrode 32 on the first region 54.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a ferroelectric memory device.

[0002]

2. Description of the Related Art A ferroelectric memory (FeRAM) uses a ferroelectric layer for a capacitor portion and holds data by its spontaneous polarization. In the conventional method of manufacturing a ferroelectric memory, the formation of the capacitor portion involves processing the electrodes and the ferroelectric layer by etching, and therefore has some drawbacks particularly when a fine pattern is formed.

For example, when high-temperature firing is required for forming a ferroelectric layer, platinum or iridium is used because aluminum electrodes cannot withstand high temperatures. Since these materials have low reactivity, it is necessary to perform etching by strengthening the chemical action. In this case, it is difficult to use an organic resist film as an etching resistant mask. On the other hand, it is conceivable to perform etching by strengthening the physical action, but the electrode material removed by etching may adhere to the electrode portion again, making it difficult to form a fine pattern. Further, when the ferroelectric layer is dry-etched, its characteristics are deteriorated.

An object of the present invention is to solve this problem, and an object of the present invention is to provide a method of manufacturing a ferroelectric memory element which can be processed precisely and does not cause deterioration of a ferroelectric layer. It is in.

[0005]

(A) A first method of manufacturing a ferroelectric memory element according to the present invention is directed to a capacitor portion having a base material having a laminated structure of a first electrode, a ferroelectric layer and a second electrode. , Comprising the following steps (a) and (b):

(A) On the surface of a substrate or a layer on a substrate,
A first region having a surface characteristic on which a material for forming the first electrode is preferentially deposited; and a material for forming the first electrode is less likely to be deposited than the first region. Forming a second region having surface properties, said first region being formed by charging the surface of the substrate or a layer on the substrate with a charge; and (b) A step of applying a material for forming the first electrode to the base material and selectively forming the member in the first region, wherein an opposite charge is applied to the first region. A first electrode is formed in the first region.

In the present invention, the first region is formed by charging the surface of the substrate or a layer on the substrate, and has an opposite charge to the first region. By applying the material, a first electrode is formed in the first region. Therefore, the first electrode is selectively formed in the first region by the Coulomb force. Therefore, a step for etching the first electrode becomes unnecessary. That is, the present invention is suitable for fine processing.

[0008] The present invention can take any of the following modes.

(1) The step (a) comprises the steps of:
Forming a precursor layer of (a-1), and irradiating the first precursor layer with a radiant energy ray, thereby causing at least a part of the first precursor layer to have a charge (a).
-2).

(2) In the step (a), the step of:
An embodiment including a step of implanting electrons or ions to form the first region.

(3) In the step (a), a step of forming a layer capable of retaining electric charges on the base material (a-
3), an embodiment including a step (a-4) of forming the first region by injecting electrons or ions into the insulating layer.

Further, the present invention can take any one of the following modes. (1) An embodiment in which the step (b) is performed by a mist deposition method. (2) An embodiment in which the step (b) is performed using a probe tip.

(B) In the second method of manufacturing a ferroelectric memory element according to the present invention, a ferroelectric material comprising a capacitor portion having a laminated structure of a first electrode, a ferroelectric layer and a second electrode on a base material. A method for manufacturing a memory element, comprising the following steps (c) and (d).

(C) a third region having a surface characteristic in which a material for forming the second electrode is preferentially deposited on the surface of the ferroelectric layer or on a layer above the ferroelectric layer. And a fourth region having a surface characteristic on which a material for forming the second electrode is less likely to be deposited as compared to the third region, wherein the third region comprises: (D) applying a material for forming the second electrode to the third region, and forming a charge on the surface of the ferroelectric layer or a layer above the ferroelectric layer; A step of selectively forming the member, wherein an oppositely charged material is applied to the third region, and the second electrode is formed in the third region.

In the present invention, the third region is formed by charging the surface of the ferroelectric layer or a layer above the ferroelectric layer, and is opposite to the third region. By providing a charged material of
The second electrode is formed in the region. For this reason,
The second electrode is selectively formed in the third region by the Coulomb force. Therefore, a step for etching the second electrode becomes unnecessary. That is, the present invention is suitable for fine processing.

The present invention can take any of the following modes.

(1) The step (c) is a step (c-1) of forming a second precursor layer on the ferroelectric layer, and irradiating the second precursor layer with a radiant energy ray. A step (c-2) of causing at least a part of the second precursor layer to be charged.

(2) An embodiment in which the step (c) includes a step of implanting electrons or ions into the surface of the ferroelectric layer to form the third region.

(3) The step (c) is a step (c-3) of forming a layer capable of holding electric charges on the ferroelectric layer, and injecting electrons or ions into the insulating layer. And forming a third region (c-4).

The present invention can take any of the following modes. (1) An embodiment in which the step (d) is performed by a mist deposition method. (2) An aspect in which the step (d) is performed using a probe tip.

(C) A third method of manufacturing a ferroelectric memory element according to the present invention provides a ferroelectric memory device having a capacitor portion having a laminated structure of a first electrode, a ferroelectric layer and a second electrode on a substrate. A method for manufacturing a memory element, comprising the following steps (e) and (f).

(E) The surface of the first electrode or the first electrode
A fifth region having a surface characteristic on which a material for forming the ferroelectric layer is preferentially deposited on a layer above the electrode;
Forming a sixth region having a surface characteristic on which a material for forming the ferroelectric layer is less likely to be deposited as compared to the fifth region, wherein the fifth region is Formed by charging the surface of a first electrode or a layer above the first electrode, and (f) applying a material for forming the ferroelectric layer;
Selectively forming the member in the fifth region, applying an oppositely charged material to the fifth region, and forming a ferroelectric layer in the fifth region. Is done.

In the present invention, the fifth region is formed by charging the surface of the first electrode or a layer above the first electrode, and has a charge opposite to the fifth region. The ferroelectric layer is formed in the fifth region by applying a material having the following characteristics. Therefore, a ferroelectric layer is selectively formed in the fifth region by the Coulomb force. Therefore, a step for etching the ferroelectric layer becomes unnecessary. That is, the present invention is suitable for fine processing.

The present invention can take any of the following modes.

(1) The step (e) is a step (e-1) of forming a third precursor layer on the first electrode, and irradiating the third precursor layer with a radiant energy ray. An embodiment including a step (e-2) of causing at least a part of the third precursor layer to be charged.

(2) The step (e) is a step (e-3) of forming a layer capable of holding electric charges on the first electrode, and injecting electrons or ions into the insulating layer. And a step (e-4) of forming the fifth region.

The present invention can take any of the following modes. (1) An embodiment in which the step (f) is performed by a mist deposition method. (2) An embodiment in which the step (f) is performed using a probe tip.

(D) A fourth method of manufacturing a ferroelectric memory device according to the present invention provides a ferroelectric memory device having a capacitor portion having a laminated structure of a first electrode, a ferroelectric layer and a second electrode on a substrate. A method for manufacturing a memory element, comprising the following step (g).

(G) a seventh region having a surface characteristic on which at least one member constituting the capacitor portion is preferentially deposited; and at least one region constituting the capacitor portion as compared with the seventh region. Forming an eighth region having a surface characteristic on which the three members are difficult to be deposited, wherein the surface of the member serving as the eighth region is charged (g-1). Applying a material for forming a surface modification layer having a charge opposite to the electric charge in the region and forming a surface modification layer in the eighth region, wherein the surface modification layer is The affinity with a material for forming at least one member constituting the capacitor portion is lower than that of the seventh region (g-2).

In the present invention, the eighth region is charged with a charge, and the eighth region is provided with a material for forming the surface modification layer having the opposite charge.
The surface modification layer can be selectively formed.

Further, since the surface modification layer has a low affinity for a material for forming at least one member constituting the capacitor portion, the member can be selectively formed in the seventh region. .

The surface modification layer can take any one of the following modes.

(1) An embodiment formed before forming the first electrode.

(2) An embodiment in which the surface modification layer is formed after forming the first electrode and before forming the ferroelectric layer.

(3) An embodiment in which the surface modification layer is formed after forming the ferroelectric layer and before forming the second electrode.

In the present invention, the step (g-2) can be performed using a probe tip.

(E) A fifth method of manufacturing a ferroelectric memory device according to the present invention provides a ferroelectric memory device having a capacitor portion having a laminated structure of a first electrode, a ferroelectric layer and a second electrode on a base material. A method for manufacturing a memory element, comprising the following step (h).

(H) on the surface of the substrate or on the layer above the substrate,
A ninth region having a surface characteristic on which a material for forming the first electrode is preferentially deposited, and a material for forming the first electrode is less likely to be deposited than the ninth region. Forming a tenth region having surface characteristics, wherein the step (h-1) of charging the surface of the base material or the layer on the base material serving as the ninth region, A step of applying a material for forming a surface modification layer having an opposite charge to the ninth region to form a surface modification layer in the ninth region, wherein the surface modification layer comprises: The affinity with the material for forming the first electrode is higher than that of the tenth region (h-2).

According to the present invention, the ninth region is charged,
In addition, a material for forming a surface modification layer having an opposite charge is applied to the ninth region to form a surface modification layer. Therefore, the surface modification layer can be selectively formed. Further, since the surface modification layer has a higher affinity for the material for forming the first electrode than the tenth region, the first electrode can be selectively formed.

In the present invention, the step (h-2) comprises:
This can be performed using a probe tip.

(F) A sixth method of manufacturing a ferroelectric memory element according to the present invention provides a ferroelectric memory device having a capacitor portion having a laminated structure of a first electrode, a ferroelectric layer and a second electrode on a base material. A method for manufacturing a memory element, comprising the following step (i).

(I) The surface of the first electrode or the first electrode
An eleventh region having a surface characteristic on which a material for forming the ferroelectric layer is preferentially deposited on a layer above the electrode, and the ferroelectric layer as compared with the eleventh region. A twelfth material having a surface characteristic on which a material to be formed is difficult to deposit.
And (c) causing the surface of the first electrode to be the eleventh region or a layer on the first electrode to be charged (i-1). A step of applying a material for forming a surface modification layer having an opposite charge to the region and forming a surface modification layer in the eleventh region, wherein the surface modification layer comprises: Compared to the eleventh region, the affinity for the material for forming the ferroelectric layer is higher (i-2).

According to the present invention, the eleventh region is charged with a charge, and the eleventh region is provided with a material for forming a surface modification layer having an opposite charge to form the surface modification layer. are doing. Therefore, the surface modification layer can be selectively formed. Further, since the surface modification layer has a higher affinity for the material for forming the ferroelectric layer than the twelfth region, the ferroelectric layer can be selectively formed.

In the present invention, the step (i-2) comprises:
This can be performed using a probe tip.

(G) A seventh method of manufacturing a ferroelectric memory element according to the present invention is directed to a ferroelectric memory device having a capacitor portion having a laminated structure of a first electrode, a ferroelectric layer and a second electrode on a base material. A method for manufacturing a memory element, comprising the following step (j).

(J) A thirteenth region having a surface characteristic in which a material for forming the second electrode is preferentially deposited on the surface of the ferroelectric layer or on a layer above the ferroelectric layer. And a fourteenth surface having a surface characteristic in which a material for forming the ferroelectric layer is less likely to be deposited than the thirteenth region.
And (c) causing the surface of the ferroelectric layer to be the thirteenth region or a layer above the ferroelectric layer to carry charges (j-1). A step of forming a surface modification layer in the thirteenth region by applying an oppositely charged material for forming a surface modification layer to the thirteenth region, wherein the surface modification layer comprises: ,
Compared with the fourteenth region, the affinity for the material for forming the second electrode is higher (j-2).

According to the present invention, the thirteenth region is charged,
Further, a material for forming a surface modification layer having an opposite charge is applied to the thirteenth region to form a surface modification layer. Therefore, the surface modification layer can be selectively formed. Further, since the surface modification layer has a higher affinity for the material for forming the second electrode than the fourteenth region, the second electrode can be selectively formed.

In the present invention, the step (j-2) comprises:
This can be performed using a probe tip.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings. 1A to 4C are views showing a method for manufacturing a ferroelectric memory element according to an embodiment to which the present invention is applied. A ferroelectric memory element is a nonvolatile semiconductor memory device. The minimum unit of information storage is a memory cell,
For example, a memory cell is formed by combining one transistor and one capacitor part. Such a plurality of memory cells can be arranged to form a memory array. In this case, the plurality of memory cells can be regularly arranged in a plurality of rows and a plurality of columns.

(Transistor forming step) As shown in FIG. 1A, a transistor 12 for controlling a ferroelectric memory element is formed on a substrate 10 made of a semiconductor wafer or the like. A structure in which a functional device such as a transistor is provided on the substrate 10 as necessary corresponds to a base material. A known structure may be applied to the transistor 12, and the transistor 12 may be a thin film transistor (TFT). MOSFET
If so, the transistor 12 has the drain and the source 1
4 and 16 and a gate electrode 18. Gate electrode 18
Are connected to the word line 544 (see FIG. 15). One of the drain and the source is connected to a bit line 542.
(See FIG. 15). Each memory cell has a LOCOS (Local Oxidation of Silicon)
17, an interlayer insulating layer 19 made of SiO ₂ or the like is formed on the transistor 12.

(Formation of First and Second Regions) First, FIG.
As shown in (B), a first precursor layer 50 is formed on the first interlayer insulating layer 19. The first precursor layer 50 includes:
It can be made of a material that is charged by performing a predetermined process. For example, it can be made of a material that is charged by irradiating radiant energy rays such as light (including laser light). More specifically, carboxylic acid group -COOH, hydroxyl group -OH, sulfonic acid group -S
Examples of the material include a material in which a functional group such as O ₃ H, a phosphonic acid group —PO ₃ H, and an amine group —NH ₂ is formed by irradiating a radiant energy ray. Carboxylic acid group -C
OOH, a material having a hydroxyl group -OH, a sulfonic acid group -SO ₃ H, a phosphonic acid group -PO ₃ H can form a negatively charged charging layer. Material having an amine group -NH _2, it is possible to form a positively charged charged layer.
The first precursor layer 50 is preferably made of a material that is charged by light having a wavelength of 100 to 400 nm. As a light source in this region, KrF (248n
m) and ArF (193 nm). If the first precursor layer is made of a material which is charged by light having a wavelength of less than 100 nm, the transmittance is high and the energy is large, so that the first precursor layer has a bad influence on the transistor inside the substrate.

Specific examples of the material of the first precursor layer 50 include a photodecomposable substance, a substance decomposed by an acid generated by light, and a substance whose structure is changed by light. Examples of the photodegradable substance include o-naphthoquinonediazide-5-sulfonic acid ester and o-naphthoquinonediazide-4-sulfonic acid ester.
Substances decomposed by the acid generated by light include t-
BOC-polyhydroxystyrene can be mentioned. Examples of the acid generated by light include an acid generated by a photoacid generator. As the photoacid generator,
By light irradiation of diazonium salt, diazoquinonesulfonic acid amide, diazoquinonesulfonic acid ester, diazoquinonesulfonic acid salt, nitrobenzyl ester, onium salt, halide, halogenated isocyanate, halogenated triazine, bisarylsulfonyldiazomethane, disulfone, etc. Compounds that decompose to generate an acid can be given. Further, as the photoacid generator, o-naphthoquinonediazide-5-sulfonate and o-naphthoquinonediazide-4-sulfonate described in the photodegradable substance can also be applied.

As a substance whose structure is changed by light, o
-Nitrobenzyl derivative esters. The o-nitrobenzyl derivative ester undergoes a hydrolysis reaction in the molecule by ultraviolet irradiation to release a carboxylic acid compound.

The first precursor layer 50 can be formed by dissolving the above materials in a solvent and applying the solution. Examples of the coating method include a spin coating method, a roll coating method, a spray coating method, and a dipping method. The thickness of the first precursor layer 50 is, for example, 1 to 100 nm.

Next, as shown in FIG. 1C, the first precursor layer 50 is selectively etched using a lithography technique. The first precursor layer 50 includes the first electrode 32
Is etched so as to remain in the region where the slab is to be formed.

Next, as shown in FIG. 2A, the first precursor layer 50 is irradiated with light. Then, a treatment in which the functional group generated by light irradiation is charged (for example, pH
Process). Thereby, the first charged layer 52 charged in the region irradiated with the light is formed. Here, the first
The region where the charging layer 52 is formed becomes the first region 54,
The area where the first charging layer 52 is not formed is the second area 5
It becomes 6. The first charging layer 52 may be positively charged,
Alternatively, it may be negatively charged. Whether the first charging layer 52 is positively or negatively charged depends on whether the first precursor layer 5
0 is determined by the material. When the first precursor layer 50 is composed of o-naphthoquinonediazide-5-sulfonate or o-naphthoquinonediazide-4-sulfonate, the sulfonic acid group is irradiated by irradiating near-ultraviolet rays of about 400 nm. The first charged layer 52 that is negatively charged can be formed by generating such a condition that the proton (H ⁺ ) of the sulfonic acid group is eliminated.

(Formation of First Electrode) Next, as shown in FIG. 2B, a material for the first electrode 32 having an opposite charge to the first charged layer 52 is applied. The first electrode 32 is selectively formed on the first charging layer 52 using Coulomb force. Specifically, when the first charged layer 52 is positively charged, a material for the negatively charged first electrode 32 is applied, and conversely, the first charged layer 52 becomes negatively charged. If so, a positively charged material for the first electrode 32 is applied. Examples of a method for forming the first electrode 32 include a mist deposition method, a CVD method (particularly, MOCVD method), an electroplating method, and an electroless plating method. First electrode 3
Raw materials for 2 can include cationic platinum complexes, iridium complexes, nickel complexes, ruthenium complexes and the like. As the cationic platinum complex, [Pt ^II (en)]
²⁺ and [Pt ^IV (en) ₂ Cl ₂ ] (en: ethylenediamine).

A method for applying a material for the charged first electrode will be described by taking a mist deposition method as an example. As shown in FIG. 5, the mist is generated from the material through the mist generator 220 from the material supply source 210. When mist is generated, mist that is positively charged due to friction,
A negatively charged mist is generated. By introducing the charged mist into the filter 230 and applying an electric field to the mist and sieving, only the mist charged to either positive or negative is selected. The selected mist is in chamber 240
Introduced into the substrate 10 through the shower head 250.
Supplied above. The mist that has not adhered to the first charging layer 52 is exhausted through the exhaust port 260. Note that the substrate 10 is rotated as necessary.

As a method for charging the material for the first electrode 32, in the case of a mist deposition method as an example, as shown in FIG. By introducing the material for the electrode 32 into the main tube 222, a mist is generated and at the same time the material is charged by friction.

(Formation of Ferroelectric Layer) Next, as shown in FIG. 2C, a ferroelectric layer 34 is formed on the entire surface. As a method for forming the ferroelectric layer 34, for example, a vapor phase method can be mentioned, and as the vapor phase method, CVD, in particular, MOCVD can be applied.

The material of the ferroelectric layer 34 may be of any composition as long as it exhibits ferroelectricity and can be used as a capacitor insulating film. For example, PZ
In addition to a T-based piezoelectric material, a material to which a metal element such as niobium, nickel, or magnesium is added can be used. Specifically, lead titanate (PbTiO ₃ ), lead zirconate titanate (Pb (Zr, Ti) O ₃ ), lead zirconate (PbZ
rO ₃ ), lanthanum lead titanate ((Pb, La), Ti
O ₃ ), lead lanthanum zirconate titanate ((Pb, L
a) (Zr, Ti) O ₃ ) or magnesium zirconium niobate lead titanate (Pb (Zr, Ti) (Mg, N
b) O ₃ ) and the like can be used. Alternatively, or SBT having Sr, Bi, Ta as a constituent element
Can also be used.

(Formation of Third Region and Fourth Region) Next, as shown in FIG.
A second precursor layer 60 is formed. Second precursor layer 60
Has the same configuration (for example, material,
Thickness) can be applied. Specifically, the configuration of the second precursor layer 60 is made of a material that is charged by performing a predetermined process, similarly to the first precursor layer 60. be able to. The second precursor layer 60 is not particularly limited as long as it does not adversely affect the characteristics of the ferroelectric layer 34. The thickness of second precursor layer 60 is, for example, 1 to 100 nm. In addition, the second precursor layer 60 can be formed by a method similar to that of the first precursor layer 50.

Next, as shown in FIG. 3B, the second precursor layer 60 is selectively etched by using a lithography technique. The second precursor layer 60 includes the second electrode 36
Is etched so as to remain in the region where the slab is to be formed.

Next, as shown in FIG. 3C, the second precursor layer 60 is irradiated with light. Then, a treatment in which the functional group generated by light irradiation is charged (for example, pH
Process). Thereby, the second charged layer 62 charged in the region irradiated with the light is formed. Here, the second
The region where the charging layer 62 is formed becomes the third region 64,
The area where the second charging layer 62 is not formed is the fourth area 6
It becomes 6. The second charging layer 62 may be positively charged,
Alternatively, it may be negatively charged. That is, the second charging layer 6
Whether 2 is positively or negatively charged is determined by the material of the second precursor layer 60.

(Formation of Second Electrode) Next, as shown in FIG. 4A, a material for the second electrode 36 having an opposite charge to the second charged layer 62 is applied. The second electrode 36 is selectively formed on the second charging layer 62 using Coulomb force. Specifically, when the second charged layer 62 is positively charged, a material for the negatively charged second electrode 36 is applied, and conversely, the second charged layer 62 becomes negatively charged. If so, a positively charged material for the second electrode 36 is applied. The method for forming the second electrode 36 can be the same as the method for forming the first electrode 32.

Next, as shown in FIG. 4B, the ferroelectric layer 34 is selectively etched using the second electrode 36 as a mask. Then, as shown in FIG.
A second interlayer insulating layer 70 is formed. Then, the first to third
After forming the through holes 70a, 70b, 70c of
In the first to third through holes 70a, 70b, 70c, the first to third contact layers 72a, 72b, 7
2c is formed. Next, a wiring layer 80 for electrically connecting the second contact layer 72b and the third contact layer 72c is formed.

(Modification) The above-described embodiment can be modified as follows.

(1) In the above embodiment, the first
After patterning the precursor layer 50, the first precursor layer 50 was irradiated with light to form a first charged layer 52. However, before patterning the precursor layer, all of the first precursor layers are irradiated with light to form a first charged layer as shown in FIG. 7A, and as shown in FIG. 7B. The first charging layer may be patterned first. This modification is different from the second charging layer 62
Is also applicable. Further, this modified example can be applied to the following embodiments.

(2) In the above embodiment, the ferroelectric layer 34 is deposited on the entire surface, and then the ferroelectric layer 34
Was patterned. However, the ferroelectric layer 34 may be selectively formed in the same manner as in the method of forming the lower electrode and the upper electrode in the above embodiment. That is, FIG.
As shown in (A), the third charging layer 9 is formed on the first electrode 32.
2 and a fifth region 94 is provided. The area other than the third charging layer 92 becomes the sixth area 96. Third charging layer 9
2 can be formed similarly to the first charging layer 62.
By providing the material of the ferroelectric layer 34 having a charge opposite to that of the third charging layer 92, as shown in FIG.
The ferroelectric layer 34 may be selectively formed using Coulomb force. As a method of applying the material of the ferroelectric layer 34, a mist deposition method can be cited, and specifically, the method described for the first electrode 32 can be cited. As a method of charging the material of the ferroelectric layer 34, a method similar to the method of charging the material for the first electrode 32 in the above embodiment can be used.

For forming the ferroelectric layer 34, a method of selectively supplying a solution of the material in a liquid state onto the first electrode 32 by an ink-jet method or the like can be adopted.

(3) In the above embodiment, the first
The first charging layer 52 was formed by irradiating the precursor layer 50 with light. However, the first charging layer 52 may be formed by irradiating an electron beam or an ion beam.
This modification is also applicable to the second charging layer 62. Further, this modified example can be applied to the following embodiments.

(4) The first charging layer 52 may be provided, if necessary,
It may be removed. Similarly, the second charging layer 62 may be removed as needed. Further, this modified example can be applied to the following embodiments.

(5) As shown in FIG. 9A, between the tip of the scanning probe tip 300 and the first charging layer 52,
The material 32 a for the first electrode 32, which has the opposite charge to that of the first charged layer 52, may be capillary-aggregated, and the material 32 a may be transported onto the first charged layer 52. Examples of the scanning probe tip include an atomic force microscope or a scanning tunnel microscope.

When a probe tip is used, FIG.
As shown in (B), the first precursor layer 50 may be irradiated with light via a waveguide 310 formed in the probe probe 300 to form the first charged layer 52. When these scanning probe tips are used, the formation of the first charging layer 52 and the formation of the first electrode 32 can be performed simultaneously.

This modification can also be applied to the case where the second electrode 36 is selectively formed. Further, this modified example can be applied to the following embodiments.

(6) The first charging layer 52 may be composed of a self-assembled film. That is, by introducing an anionic functional group or a cationic functional group into the terminal group of the molecule constituting the self-assembled film, the first charged layer 52 is formed.
May be formed. Examples of the anionic functional group include a carboxylic acid group —COOH, a hydroxyl group —OH, and a sulfonic acid group —S
O ₃ H and a phosphonic acid group —PO ₃ H can be exemplified. Examples of the cationic functional group include an amine group —NH ₂ ,
It can be exemplified pyridinium group -C ₅ H ₄ N, and the like. In the step of forming the self-assembled film, a protecting group for protecting the above-mentioned functional group is provided, and after forming the self-assembled film, light is irradiated to deprotect the above-mentioned functional group. Alternatively, it may be formed. This modification can also be applied to the second charging layer 62. Further, this modified example can be applied to the following embodiments.

(7) The first charging layer 52 has an insulating property,
It may be formed in a film capable of holding electric charge. Specifically, a film capable of holding electric charges may be formed, and electrons may be injected into the film by an electron beam to form a negatively charged charged layer. Alternatively, positive or negative ions may be ion-implanted into a film capable of holding electric charges to form a positively or negatively charged charged layer. Examples of the layer capable of retaining charges include an insulating layer and a semiconductor layer. Examples of the material of the insulating layer that can hold electric charge include silicon oxide, silicon nitride, aluminum oxide, polyimide, and tantalum oxide. Examples of the material of the semiconductor layer capable of retaining electric charge include an inorganic semiconductor (for example, a silicon semiconductor), a compound semiconductor, and an organic semiconductor (phthalocyanine, porphyrin, or a derivative thereof).

(8) As shown in FIG. 10, the first charging layer 52 may be formed in the first interlayer insulating layer 19 by injecting ions or electrons into the first interlayer insulating layer 19. . Further, this modified example can be applied to the following embodiments.

(9) In the above embodiment, the first precursor layer 50 is charged after being patterned. However, the present invention is not limited to this, and the first precursor layer 50 may be locally charged without patterning. In particular,
Using a mask or the like, the first precursor layer 50 may be locally irradiated with radiant energy rays to be charged.

This modification can be applied to the second precursor layer 60 as well. Further, this modified example can be applied to the following embodiments.

(10) The precursor layers 50 and 60 can be charged by a method utilizing plasma processing. Further, this modified example can be applied to the following embodiments.

(11) The above modifications can be combined as far as possible.

[Second Embodiment] A method of manufacturing a ferroelectric memory device according to a second embodiment will be described below. FIGS. 11A to 12C are diagrams illustrating a method of manufacturing a ferroelectric memory element according to the second embodiment.

First, in the same manner as in the first embodiment, up to the first interlayer insulating layer 19 is formed. Next, FIG.
As shown in FIG. 7, after forming a through hole 172a in the first interlayer insulating layer 19, a contact layer 172 is formed in the through hole 172a.

Next, as shown in FIG. 11B, a precursor layer 150 is formed on the first interlayer insulating layer 19. The precursor layer can be formed by the same method as in the first embodiment, and can have the same configuration (for example, material and thickness) as in the first embodiment.

Next, as shown in FIG. 11C, the precursor layer 150 is selectively etched using a lithography technique. The precursor layer 150 is etched so as to remain in a region where a surface modification layer 160 to be formed in a later step is to be formed.

Next, as shown in FIG. 12A, the precursor layer 150 is irradiated with light to form a charged layer 152. The charging layer 152 may be positively charged or negatively charged. That is, whether the charged layer 152 is charged positively or negatively depends on the material of the precursor layer 150.

Next, as shown in FIG. 12B, a material for the surface modification layer 160 having a charge opposite to that of the charging layer 152 is applied, and Coulomb force is applied on the charging layer 152. Thus, the surface modification layer 160 is selectively formed. Specifically, when the charged layer 152 is positively charged, a material for the negatively charged surface modification layer 160 is applied, and conversely,
When the charging layer 152 is negatively charged, a material for the surface modification layer 160 that is positively charged is provided.

The surface modification layer 160 is formed by a first
The electrode 32, the ferroelectric layer 34, and the second electrode 36 are made of a material having a higher affinity than the region where the surface modification layer 160 is not formed. The surface modification layer 160 may be formed by a vapor phase growth method such as a sputtering method or a CVD method, or may be formed by a method using a liquid phase such as an inkjet method, a spin coating method, a dip method, and a mist deposition method. In such a case, a substance dissolved in a liquid or a solvent is used. For example, a silane coupling agent (organosilicon compound) or a thiol compound can be used. Here, the thiol compound refers to an organic compound (R ¹ ) having a mercapto group (—SH).
-SH; R ¹ is a substitutable hydrocarbon group such as an alkyl group)
Refers to the generic name of Such a thiol compound, for example,
Dissolve in an organic solvent such as dichloromethane or trichloromethane to obtain a solution of about 0.1 to 10 mM.

The silane coupling agent is R ² _n S
iX _4-n (n is a natural number, R ² is H, a substitutable hydrocarbon group such as an alkyl group), and X is -OR
^{3, -COOH, -OOCR 3, -NH} 3-n R 3 n, -OC
N, halogen and the like (R ³ is a substitutable hydrocarbon group such as an alkyl group). Among these silane coupling agents and thiol compounds, especially R ¹ and R ³ are C _n F _{2n + 1} C _m H
A compound having a fluorine atom of _2m (n and m are natural numbers) is preferably used because the surface free energy is reduced and the affinity with other materials is reduced.

In order to impart a charge to the silane coupling agent or the thiol compound, the terminal of the hydrocarbon group may have a chargeable structure, and the terminal group having an anionic terminal group may be negatively charged. However, the cationic end groups are positively charged. Examples of the terminal group that generates an anionic terminal group include a carboxylic acid group -COOH, a hydroxyl group -OH, and a sulfonic acid group-
Examples thereof include SO ₃ H and a phosphonic acid group —PO ₃ H. A molecule having such a terminal group is likely to be charged with a negative charge and is preferably used. An amine group as the cationic terminal group
NH _2, include pyridium group -C ₅ H ₄ N, etc., molecules having such terminal groups tends positively charged, is preferably used.

Further, by applying an electric field perpendicularly to the substrate 10 in order to control the film formation of the surface modification layer 160, the film formation rate can be stabilized and increased. When the surface modification layer 160 is formed by the mist deposition method, the mist preferably has a particle size of 0.1 μm or more. If the particle size of the mist is less than 0.1 μm, the charge amount is small, and the film forming rate tends to be low. Hereinafter, a region where the surface modification layer 160 is not formed is referred to as a seventh region 164, and a region where the surface modification layer 160 is formed is referred to as an eighth region 166. Since the surface modification layer 160 is not formed in the seventh region 164,
The seventh region 164 has a higher affinity for the first electrode 32, the ferroelectric layer 34, and the second electrode 36 constituting the capacitor than the eighth region 166 where the surface modification layer 160 is formed. Have.

Next, as shown in FIG. 12C, a first electrode 32 serving as a lower electrode of a capacitor portion of the ferroelectric memory element is formed corresponding to the seventh region 164. Here, “corresponding to the seventh region 164” means that the planar shape of the first electrode 32 and the planar shape of the contact layer (plug) 172 do not need to completely match. For example,
A film formation process is performed on the entire surface of the substrate on which the transistor is formed on the substrate 10 by, for example, a gas phase method. In this way, a selective deposition process is performed. That is, since the film is formed in the seventh region 164 and is difficult to be formed in the eighth region 166, the first electrode 32 is formed only in the seventh region 164. Here, as a gas phase method, CVD, especially MOCVD (Metal Organic Chemical Vapor Deposit) is used.
It is preferred to apply ion). In the eighth region 166, it is preferable that no film is formed at all.
It is sufficient that the film formation speed is at least two orders of magnitude slower than the film formation at 66.

The first electrode 32 may be formed by selectively supplying a solution of the material in a liquid state to the seventh region 164, or by forming the solution of the material into a mist by ultrasonic waves or the like. It is also preferable to adopt a mist deposition method of selectively supplying the mist to the seventh region 164.

Examples of the material forming the first electrode 32 include the following.
For example, Pt, Ir or the like can be used. 7th on substrate
Region 166 and a surface modification film containing the material as described above
160 (eighth region 166), and select surface characteristics.
When the selectivity is formed, for Pt, for example, (C_FiveH₇
O_Two)_TwoPt, (C_FiveHFO_Two)_TwoPt, (C_ThreeH_Five) (C_FiveH
_Five) Pt as a material for forming an electrode
For example, (C_ThreeH _Five)_ThreeIr for forming electrodes
Can be selectively deposited, using as material
You.

(Step of Forming Ferroelectric Layer) Next, the first electrode 3
A ferroelectric layer 34 is formed on 2. Specifically, for example, a film forming process by a vapor phase method is performed on the entire surface. By doing so, a film is formed on the first electrode 32 and the surface modification layer 16 is formed.
Since it is difficult to form a film on 0, the ferroelectric layer 34 is formed only on the first electrode 32. Here, as the gas phase method, C
VD, in particular, MOCVD can be applied.

The ferroelectric layer 34 is formed by selectively supplying a solution of the material in a liquid state onto the first electrode 32 by an ink-jet method or the like, or by applying a solution of the material to the mist by ultrasonic waves. It is also preferable to employ a mist deposition method for selectively supplying the mist to portions other than the second region 26.

As the material of the ferroelectric layer 34, any composition can be used as long as it exhibits ferroelectricity and can be used as a capacitor insulating film. For example, a material to which a metal element such as niobium, nickel, or magnesium is added in addition to the PZT-based piezoelectric material can be used. Specifically, lead titanate (PbTi
O ₃ ), lead zirconate titanate (Pb (Zr, Ti)
O ₃ ), lead zirconate (PbZrO ₃ ), lead lanthanum titanate ((Pb, La), TiO ₃ ), lead lanthanum zirconate titanate ((Pb, La) (Zr, Ti) O ₃ ) or magnesium niobium Lead zirconium titanate (Pb
(Zr, Ti) (Mg, Nb) O ₃ ) or the like can be used. Alternatively or alternatively, SBT having Sr, Bi, and Ta as constituent elements can be used.

The material of the above-described ferroelectric layer 34 is the same as the surface modification film 160 (the eighth region 16) containing the above-described material.
6) to form the selectivity of the surface characteristics, for example, in the case of PZT, Pb is Pb (C ₂ H ₅ ) ₄ ,
(C ₂ H ₅ ) ₃ PbOCH ₂ C (CH ₃ ) ₃ , Pb (C ₁₁ H ₁₉
O ₂ ) _{2 and the} like, and for Zr, Zr (n-OC
_{4 H 9) 4, Zr (} t-OC 4 H 9) 4, Zr (C 11 H
STB is used as a material for forming the ferroelectric layer 34, using ₁₉ O ₂ ) ₄ , Zr (C ₁₁ H ₁₉ O ₂ ) _4, etc., and for Ti, Ti (i-OC ₃ H ₇ ) ₄ etc. , Sr (C ₁₁ H ₁₀ O ₂ ) ₂ etc. for Sr, Bi for Bi
(C ₆ H ₅ ) _{3 and the} like, and for Ta, Ta (OC ₂ H ₅ ) _{5 and the} like can be used as a material for forming the ferroelectric layer 34, and can be selectively deposited.

(Second Electrode Forming Step) Next, the ferroelectric layer 3
A second electrode 36 serving as an upper electrode is formed on the fourth electrode 4. Specifically, it is preferable to perform a film forming process by, for example, a gas phase method on the entire surface. In this way, a selective deposition process is performed. That is, the second electrode 36 is formed only on the ferroelectric pair film 34 because the film is formed on the ferroelectric pair film 34 and is not easily formed on the surface modification layer 160. Here, it is preferable to apply CVD, particularly MOCVD, as a gas phase method.

Next, as shown in FIG. 13, if necessary, the surface modification layer 160 and the charging layer 152 are removed.

(Modification) The second embodiment can be modified as follows.

(1) The method of forming the surface modification layer 160 may be a method using a probe. That is, the method described in the modified example (5) of the first embodiment can be applied.

(2) In the above embodiment, the surface modification layer 160 was formed before the first electrode 32 was formed. However, the surface modification layer 160 may be formed after forming the first electrode 32 and before forming the ferroelectric layer 34. That is, the surface modification layer 160 can function as a material for selectively forming the ferroelectric layer 34 and the second electrode 36. In this case, the first electrode 32
Can be formed by a known method.

The surface modification layer 160 is made of the ferroelectric material 34.
May be formed before the second electrode 36 is formed. That is, the surface modification layer 160 can function as a member for selectively forming the second electrode 36. In this case, the first electrode 32 and the ferroelectric layer 34
Can be formed by a known method.

[Third Embodiment] A method of manufacturing a ferroelectric memory device according to a third embodiment will be described.
FIGS. 16A to 20 are views showing a method for manufacturing a ferroelectric memory element according to the third embodiment.

First, as shown in FIG. 16A, the processes up to the first interlayer insulating layer 19 are formed in the same manner as in the first embodiment.

Next, on the first interlayer insulating layer 19, the first
Is formed. First precursor layer 450
Can be formed by the same method as the precursor layer of the first embodiment, and can have the same configuration (for example, material and thickness) as the first embodiment.

Next, as shown in FIG. 16B, the first precursor layer 450 is selectively etched using a lithography technique. The first precursor layer 450 is etched so as to remain in a region where the first surface modification layer 458 is to be formed.

Next, the first precursor layer 450 is irradiated with light to form a first charged layer 452. First charging layer 45
2 may be positively charged or negatively charged. That is, whether the first charging layer 252 is positively or negatively charged depends on the material of the first precursor layer 450.

Next, as shown in FIG. 16C, a material for the first surface modification layer 458 having a charge opposite to that of the first charged layer 452 is applied, and the first charged layer is formed. A first surface modification layer 458 is selectively formed on 452 using Coulomb force. Specifically, when the first charged layer 452 is positively charged, a material for the negatively charged first surface modification layer 458 is applied, and conversely, the first charged layer 4
If 52 is negatively charged, a positively charged material for the first surface modification layer 458 is applied. The first surface modification layer 458 is made of a material having a higher affinity for a material for forming the first electrode 32 than a region where the first surface modification layer 458 is not formed. First surface modification layer 45
Examples of the material 8 include a phosphonate thiol derivative, a carboxylate thiol derivative, and a bisphosphonic acid. The molecular structure of the phosphonic acid thiol derivative represented by the general formula _{SH- (CH 2) i -PO 3} H 2. i is an integer not including a negative number, and is preferably 18 or less. The general formula of the molecular structure of the carboxylic acid thiol derivative is SH- (CH
₂ ) Represented by _x- COOH. x is an integer not including a negative number, and is preferably 18 or less. The molecular structure of Bisuhon acid derivatives of the general formula PO ₃ H ₂ - represented by _{(CH 2) y -PO 3 H} 2. y is an integer not including a negative, and is preferably 18 or less. The thickness of the first surface modification layer 458 is, for example, 1 to 5
0 nm, preferably 1 to 10 nm.

The first surface modification layer 458 may be formed by a vapor phase growth method such as a sputtering method or a CVD method, or may be formed by a liquid phase such as an ink jet method, a spin coating method, a dipping method, and a mist deposition method. It may be formed by the method used, in which case a substance dissolved in a liquid or a solvent is used. In forming the first surface modification layer 458, the method for forming the surface modification layer 160 in the second embodiment can be applied to the extent possible. Hereinafter, a region where the first surface modification layer 458 is formed is referred to as a “ninth region 454”, and the first surface modification layer 458 is formed.
The region where is not formed is referred to as a “tenth region 456”. Since the first surface modification layer 458 is formed in the ninth region 454, the ninth region 454 has a higher affinity for the material for forming the first electrode 32 than the tenth region 456.

Next, as shown in FIG. 17A, a material for the first electrode layer 32 is applied. Ninth area 454
Has a higher affinity for the material of the first electrode 32 than the tenth region 456. Therefore, the ninth region 454
, The first electrode 32 is selectively formed. For example, by reacting metal fine particles with the terminal groups (thiol groups or phosphonic acid groups) of the first surface modification layer 458, the first electrode 32 can be selectively placed on the first surface modification layer 458. Can be formed. Examples of the method for forming the first electrode 32 include an inkjet method, a spin coating method, a dipping method, a mist deposition method, and a CVD method.

Next, as shown in FIG. 17B, a second precursor layer 460 is formed on the entire surface. The second precursor layer 460 can be formed by a method similar to that of the precursor layer of the first embodiment, and has the same configuration (for example, material and thickness) as that of the first embodiment. Can be.

Next, as shown in FIG. 17C, the second precursor layer 460 is selectively etched using a lithography technique. The second precursor layer 460 is etched so as to remain in a region where the second surface modification layer 468 is to be formed.

Next, the second precursor layer 460 is irradiated with light to form a second charged layer 462. Second charging layer 46
2 may be positively charged or negatively charged. That is, whether the second charging layer 462 is positively or negatively charged depends on the material of the second precursor layer 460.

Next, as shown in FIG. 18A, a material for the second surface modification layer 468 having a charge opposite to that of the second charged layer 462 is applied, and the second charged layer is formed. A second surface modification layer 468 is selectively formed on 462 using Coulomb force. Specifically, when the second charging layer 462 is positively charged, a material for the negatively charged second surface modification layer 468 is applied, and conversely, the second charging layer 4
If 62 is negatively charged, a positively charged material for the second surface modification layer 468 is applied. The second surface modification layer 468 is made of a material having a higher affinity for the material for forming the ferroelectric layer 34 than in a region where the second surface modification layer 458 is not formed. Second surface modification layer 46
As for the material and thickness of 8, the same material and thickness as those of the first surface modification layer 468 can be applied.

The second surface modification layer 468 can be formed by a method similar to that of the first surface modification layer 458. Hereinafter, a region in which the second surface modification layer 468 is formed is referred to as an “eleventh region 464”, and the second surface modification layer 46
A region where no 8 is formed is referred to as a “twelfth region 466”. The eleventh region 464 includes the second surface modification layer 468
Is formed, so that it has an affinity for the material for forming the ferroelectric layer 34 as compared with the twelfth region 466.

Next, as shown in FIG. 18B, a material for the ferroelectric layer 34 is applied. Eleventh region 464
Has a higher affinity for the material of the ferroelectric layer 34 than the twelfth region 466. Therefore, the eleventh region 4
At 64, the ferroelectric layer 34 is selectively formed.
Examples of the method for forming the ferroelectric layer 34 include an inkjet method, a spin coating method, a dipping method, a mist deposition method, and a CVD method.

Next, as shown in FIG. 18C, a third precursor layer 470 is formed on the entire surface. The third precursor layer 470 can be formed by a method similar to that of the precursor layer of the first embodiment, and has the same configuration (for example, material and thickness) as that of the first embodiment. Can be.

Next, as shown in FIG. 19A, the third precursor layer 470 is selectively etched using a lithography technique. The third precursor layer 470 is etched so as to remain in a region where the third surface modification layer 478 is to be formed.

Next, the third precursor layer 470 is irradiated with light to form a third charged layer 472. Third charging layer 47
2 may be positively charged or negatively charged. That is, whether the third charging layer 472 is charged to be positive or negative depends on the material of the third precursor layer 470.

Next, as shown in FIG. 19B, a material for the third surface modification layer 478 having a charge opposite to that of the third charged layer 472 is provided, and the third charged layer 478 is provided. A third surface modification layer 478 is selectively formed on 472 using Coulomb force. Specifically, when the third charged layer 472 is positively charged, a material for the negatively charged third surface modification layer 478 is applied, and conversely, the third charged layer 4
If 72 is negatively charged, a positively charged material for the third surface modification layer 478 is applied. The third surface modification layer 478 is made of a material having a higher affinity for the material for forming the second electrode 36 than a region where the third surface modification layer 478 is not formed. Third surface modification layer 478
Can have the same material and thickness as the first surface modification layer 458.

The third surface modification layer 478 can be formed by a method similar to that of the first surface modification layer 458. Hereinafter, a region where the third surface modification layer 478 is formed is referred to as a “thirteenth region 474”, and the third surface modification layer 47 is
The area where 8 is not formed is referred to as a “fourteenth area 476”. The thirteenth region 474 includes a third surface modification layer 478
Is formed, so that it has an affinity for the material for forming the second electrode 36 as compared with the fourteenth region 476.

Next, as shown in FIG. 19C, a material for the second electrode 36 is applied. Thirteenth area 474
Has a higher affinity for the material for forming the second electrode 36 than the fourteenth region 476. Therefore, the second electrode 36 is selectively formed in the thirteenth region 474. As a method for forming the second electrode 36, for example, a method similar to that for the first electrode 32 can be used.

Next, as shown in FIG. 20, on the first interlayer insulating layer 19, a second interlayer insulating layer 480 is formed.
Next, a first through hole 480a and a second through hole 480b are formed in the second interlayer insulating layer 480. Next, the first and second through holes 480a,
480b, the first and second contact layers 48
2a and 482b are formed. Next, a wiring layer 490 for electrically connecting the first contact layer 482a and the second contact layer 482 is formed.

(Modification) The third embodiment can be modified as follows.

(1) Surface modification layers 458, 468, 478
May be a method using a probe.
That is, the method described in the modified example (5) of the first embodiment can be applied.

(2) The first surface modification layer 458 may be formed by bonding a metal for the first electrode 32 to the terminal group (thiol group or phosphonic acid group) of the first surface modification layer 458. Good. This modification can also be applied to the second surface modification layer 478.

[Structure of Ferroelectric Memory Element] FIG. 14 is a plan view showing an example of a ferroelectric memory element. The cell structure of the ferroelectric memory element shown in FIG.
(2 transistors / 2 capacitors) type.

The transistor 12 is formed in the region 40. The electrode connected to one of the drain and the source 14 is connected to the bit line 42 shown in FIG. Gate electrode 18 is connected to word line 44 shown in FIG. The electrode connected to the other 16 of the drain and the source is connected to the drive line 46 shown in FIG.
On the electrode, a ferroelectric layer 34 is formed via a first electrode 32.

FIG. 15 is a diagram showing a circuit of the ferroelectric memory element according to the present embodiment. The operation of the ferroelectric memory device will be described with reference to FIG.

To write data in the ferroelectric memory element, an address signal is supplied from an address terminal 551, a selection signal is supplied from a chip select terminal 552, and a write control signal is supplied from a write control terminal 553. You. Turn on one of the plurality (two) of bit lines 542,
With the other bit line 542 turned off, the word line decoder and driver 550 sends the designated word line 544
Turn on. Drive line decoder and driver 560
Applies a positive pulse to the specified drive line 546. Then, the ferroelectric layer 534 is provided in the ferroelectric capacitor.
Since the residual polarization due to the hysteresis characteristic remains, the information is retained even when the power is turned off.

When data is read from the ferroelectric memory element, the word line 544 is turned on after selecting the memory cell by turning the bit line 542 into a floating state.
Next, a positive voltage is applied to the drive line 546, and the displacement current due to the polarization inversion of the ferroelectric capacitor is sensed by the sense amplifier 57.
Amplify at 0. The sense / timing control unit 80 controls the sense timing and supplies data to the data I / O 590. The data I / O 590 is connected to various devices 592 such as a CPU and other memory elements, and controls data exchange.

The present invention is not limited to the above-described embodiment, and various changes can be made within the scope of the present invention.

[Brief description of the drawings]

FIGS. 1A to 1C are diagrams showing a method of manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIGS. 2A to 2C are diagrams illustrating a method of manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIGS. 3A to 3C are diagrams illustrating a method of manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIGS. 4A to 4C are views showing a method for manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIG. 5 is a diagram schematically showing an apparatus for forming a first electrode by a mist deposition method.

FIG. 6 is a diagram schematically showing a principle diagram of a mist generating device.

FIG. 7 is a manufacturing process diagram showing a modification according to the first embodiment.

FIG. 8 is a manufacturing process diagram showing a modification according to the first embodiment.

FIG. 9 is a diagram schematically illustrating a method of forming a first electrode using a probe tip.

FIG. 10 is a manufacturing process diagram showing a modification according to the first embodiment.

FIGS. 11A to 11C are diagrams illustrating a method of manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIGS. 12A to 12C are diagrams showing a method for manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIG. 13A is a diagram illustrating a method of manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIG. 14 is a plan view showing a ferroelectric memory element according to the embodiment of the present invention.

FIG. 15 is a diagram showing a circuit of the ferroelectric memory element according to the embodiment of the present invention.

FIGS. 16A to 16C are diagrams illustrating a method of manufacturing a ferroelectric memory element according to an embodiment of the present invention.

17 (A) to 17 (C) are views showing a method for manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIGS. 18A to 18C are diagrams showing a method of manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIGS. 19A to 19C are diagrams showing a method of manufacturing a ferroelectric memory element according to an embodiment of the present invention.

FIG. 20 is a diagram illustrating the method of manufacturing the ferroelectric memory element according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 32 1st electrode 34 Ferroelectric layer 36 2nd electrode 50 1st precursor layer 52 1st charge layer 54 1st area 56 2nd area 60 2nd precursor layer 62 2nd charge layer 64 Third region 66 Fourth region 92 Third charged layer 94 Fifth region 96 Sixth region 160 Surface modification layer 164 Seventh region 166 Eighth region 300 Probe 450 First precursor layer 452 First Charging layer 454 ninth region 456 tenth region 460 second precursor layer 462 second charging layer 464 eleventh region 466 twelfth region 470 third precursor layer 472 third charging layer 474 13th area 476 14th area

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F083 AD02 AD10 AD21 AD49 FR02 FR03 JA15 JA17 JA38 LA12 LA16 LA19 MA06 MA17 MA19 MA20 PR21

Claims (28)

[Claims] 1. A method of manufacturing a ferroelectric memory device comprising a substrate having a capacitor portion having a laminated structure of a first electrode, a ferroelectric layer and a second electrode, comprising the following steps (a) and ( b) A method for manufacturing a ferroelectric memory device, comprising: (A) comparing a first region having a surface characteristic on which a material for forming the first electrode is preferentially deposited on a surface of a substrate or a layer on the substrate with the first region; And forming a second region having a surface characteristic on which a material for forming the first electrode is not easily deposited, wherein the first region is formed on the surface of the base material or on the base material. And (b) applying a material for forming the first electrode to the base material and selectively forming the member in the first region. Forming a first electrode in the first region by applying a material having an opposite charge to the first region. 2. The method according to claim 1, wherein in the step (a), a step (a-1) of forming a first precursor layer on a base material is performed by applying a radiant energy ray to the first precursor layer. A method for manufacturing a ferroelectric memory element, comprising a step (a-2) of irradiating at least a part of the first precursor layer with a charge. 3. The method of manufacturing a ferroelectric memory device according to claim 1, wherein the step (a) includes a step of injecting electrons or ions into a surface of a base material to form the first region. Method. 4. The method according to claim 1, wherein in the step (a), a step (a-3) of forming a layer capable of holding electric charges on the base material is performed. Inject the first
Forming a region (a-4). 5. The method for manufacturing a ferroelectric memory device according to claim 1, wherein the step (b) is performed by a mist deposition method. 6. The method according to claim 1, wherein the step (b) is performed using a probe.
A method for manufacturing a ferroelectric memory element. 7. A method for manufacturing a ferroelectric memory element comprising a substrate having a capacitor portion having a laminated structure of a first electrode, a ferroelectric layer and a second electrode, comprising the following steps (c) and (c). d) a method for manufacturing a ferroelectric memory element. (C) a third region having a surface property on which a material for forming the second electrode is preferentially deposited on a surface of the ferroelectric layer or a layer above the ferroelectric layer; Forming a fourth region having a surface characteristic on which a material for forming the second electrode is less likely to be deposited as compared with a third region, wherein the third region has the ferroelectricity. (D) applying a material for forming the second electrode, and applying the member to the third region; Forming a second electrode in the third region by applying an oppositely charged material to the third region. 8. The method according to claim 7, wherein in the step (c), a step (c-1) of forming a second precursor layer on the ferroelectric layer is performed. A method for manufacturing a ferroelectric memory element, comprising a step (c-2) of irradiating an energy ray to at least partially charge the second precursor layer. 9. The ferroelectric memory according to claim 7, wherein the step (c) includes a step of injecting electrons or ions into a surface of the ferroelectric layer to form the third region. Device manufacturing method. 10. The method according to claim 7, wherein the step (c) is a step (c-3) of forming a layer capable of retaining charges on the ferroelectric layer. Or, by implanting ions, the third
Forming a region (c-4). 11. The method according to claim 7, wherein the step (d) is performed by a mist deposition method. 12. The method according to claim 7, wherein the step (d) is performed using a probe.
A method for manufacturing a ferroelectric memory element. 13. A first electrode, a ferroelectric layer and a second electrode on a substrate.
A method for manufacturing a ferroelectric memory element including a capacitor portion having a laminated structure of electrodes, the method including the following steps (e) and (f). (E) a fifth region having a surface characteristic on which a material for forming the ferroelectric layer is preferentially deposited on a surface of the first electrode or a layer above the first electrode; Forming a material for forming the ferroelectric layer, which is less likely to be deposited than a region of the sixth region, and a sixth region having a surface characteristic that is less than that of the first region. The surface of the electrode or the first
(F) applying a material to form the ferroelectric layer, the material being formed by charging the layer above the electrodes;
Selectively forming the member in the fifth region, applying a material having an opposite charge to the fifth region, and forming a ferroelectric layer in the fifth region. Is done. 14. The method according to claim 13, wherein the step (e) is a step (e-1) of forming a third precursor layer on the first electrode. A method for manufacturing a ferroelectric memory element, comprising a step (e-2) of irradiating a line to at least partially charge the third precursor layer. 15. The method according to claim 13, wherein the step (e) includes a step (e-3) of forming a layer capable of retaining charges on the first electrode. By implanting electrons or ions, the fifth
Forming a region (e-4). 16. The method according to claim 13, wherein the step (f) is performed by a mist deposition method. 17. The method according to claim 13, wherein the step (f) is performed using a probe.
A method for manufacturing a ferroelectric memory element. 18. The method according to claim 18, wherein the first electrode, the ferroelectric layer and the second
A method for manufacturing a ferroelectric memory element including a capacitor portion having a laminated structure of electrodes, the method including the following step (g). (G) a seventh region having a surface characteristic on which at least one member constituting the capacitor portion is preferentially deposited; and at least one member constituting the capacitor portion as compared to the seventh region. Forming an eighth region having surface characteristics that are difficult to be deposited, wherein a step (g-1) of charging the surface of a member to be the eighth region or a layer on the member with a charge (g-1); A step of applying a material for forming a surface modification layer having a charge opposite to the electric charge in the eighth region, and forming a surface modification layer in the eighth region, The surface modification layer has a lower affinity for a material for forming at least one member constituting the capacitor portion than in the seventh region (g-2). 19. The method for manufacturing a ferroelectric memory device according to claim 18, wherein the surface modification layer is formed before forming the first electrode. 20. The method according to claim 18, wherein the surface modification layer is formed after forming the first electrode and before forming the ferroelectric layer. 21. The method according to claim 18, wherein the surface modification layer is formed after forming the ferroelectric layer and before forming the second electrode. 22. The method for manufacturing a ferroelectric memory device according to claim 18, wherein the step (g-2) is performed using a probe probe. 23. A substrate comprising a first electrode, a ferroelectric layer and a second electrode.
A method for manufacturing a ferroelectric memory element including a capacitor portion having a layered structure of electrodes, the method including the following step (h). (H) comparing a ninth region having a surface characteristic on which a material for forming the first electrode is preferentially deposited on the surface of the substrate or a layer on the substrate with the ninth region; And forming a tenth region having a surface characteristic on which a material for forming the first electrode is unlikely to be deposited, comprising: (H-1) charging a layer with a material for forming a surface modification layer, which has a charge opposite to that of the ninth region, and in the ninth region, In the step of forming a surface modification layer, the surface modification layer has a higher affinity for a material for forming the first electrode than in the tenth region (h-2). 24. The method for manufacturing a ferroelectric memory device according to claim 23, wherein the step (h-2) is performed using a probe probe. 25. A substrate comprising a first electrode, a ferroelectric layer and a second electrode.
A method for manufacturing a ferroelectric memory element including a capacitor portion having a layered structure of electrodes, the method including the following step (i). (I) an eleventh region having a surface characteristic in which a material for forming the ferroelectric layer is preferentially deposited on a surface of the first electrode or a layer on the first electrode; 11
Forming a twelfth region having a surface characteristic on which a material for forming the ferroelectric layer is less likely to be deposited as compared to the first region, wherein the first electrode serving as the eleventh region is formed. (I-1) charging the surface of the first electrode or the layer above the first electrode with a charge, and applying a material for forming a surface modification layer with the opposite charge to the eleventh region. Forming a surface modification layer in the eleventh region, wherein the surface modification layer has a higher affinity for a material for forming the ferroelectric layer than the eleventh region. Is high (i-2). 26. The method for manufacturing a ferroelectric memory device according to claim 25, wherein the step (i-2) is performed using a probe probe. 27. A first electrode, a ferroelectric layer and a second
A method for manufacturing a ferroelectric memory element including a capacitor portion having a layered structure of electrodes, the method including the following step (j). (J) a thirteenth region having a surface characteristic on which a material for forming the second electrode is preferentially deposited on a surface of the ferroelectric layer or a layer above the ferroelectric layer; First
Forming a ferroelectric layer in which a material for forming the ferroelectric layer is less likely to be deposited as compared to the third region. Charging the surface of the body layer or a layer above the ferroelectric layer (j-
1) a step of forming a surface modification layer in the thirteenth region by applying an oppositely charged material for forming a surface modification layer to the thirteenth region, The surface modification layer has a higher affinity for the material for forming the second electrode than the fourteenth region (j-2). 28. The method for manufacturing a ferroelectric memory device according to claim 27, wherein the step (j-2) is performed using a probe probe.