JP2002170880A - Method for fabricating semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for fabricating a narrow wiring interval and highly integrated semiconductor device at high yield, in which a connection holes is formed surely on wiring even if there is no overlap allowance region for the connection hole. SOLUTION: A wiring 13 is covered with an insulation film 16, in which the inner region of the wiring 13 is thicker than that of the edge region. A connection hole 25 is formed by selectively etching the insulation films 24 and 16 in such a condition that the etching rate of the insulation film 16 is higher than that of the insulation film 24 on the insulation film 16. Therefore, the time until the depth of the hole 25 reaches the wiring 13 from starting of the etching of the connecting hole 25 is longer in the edge region than that of the inner region of the wiring 13 and much longer in the region shifted from the wiring 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device which involves forming a connection hole for a wiring.

[0002]

2. Description of the Related Art An external memory, an input / output interface, a clock, etc. are added to an ASIC which is an IC designed optimally for a specific application and is a kind of custom IC, a gate array which is a kind of semi-custom LSI, and a microprocessor. In MPUs and the like, which have been implemented, a multilayer wiring structure of metal wiring is employed for high integration and high-speed operation, etc., and the specification of the multilayer wiring directly controls the degree of integration and operation speed of the semiconductor integrated circuit device. Depends.

[0003] As seen in recent VLSIs and ULSIs, design standards have been highly reduced in accordance with higher performance of semiconductor integrated circuit devices. Have been. In particular, the spacing between metal wirings in a multilayer wiring structure is a large factor related to the size of a chip that affects the dimensions of a semiconductor integrated circuit device. It is necessary to.

On the other hand, in the multilayer wiring structure, it is necessary to form a connection hole for electrically connecting the upper metal wiring and the lower metal wiring to the lower metal wiring.
There is misalignment in lithography for forming a connection hole, and there is dimensional variation in etching. The misalignment in lithography depends on the performance of the exposure apparatus, and there is a misalignment of 80 nm in a normal reduction projection exposure apparatus and 50 nm in a scanning reduction projection exposure apparatus.

For this reason, in a conventional semiconductor device, a peripheral (border) region as a margin area for the connection hole is provided in the vicinity of the connection hole in the lower metal wiring. However, if such an overlap margin area is provided, the space between the lower metal wirings becomes wider by that amount,
High integration of the semiconductor integrated circuit device becomes difficult. Therefore,
In order to reduce the space between the wirings, no overlap margin area is provided for the connection hole, and the width of the vicinity of the connection hole is equal to the width of the other parts than this vicinity, which is called a borderless structure. Wiring is considered.

FIG. 2 shows a conventional example of a method of manufacturing a semiconductor device which involves forming a connection hole for such a wiring having a borderless structure. In this conventional example, an interlayer insulating film 12 is formed on a semiconductor substrate 11 such as a Si substrate on which elements such as transistors (not shown) are formed, and a wiring 13 is formed on the interlayer insulating film 12. The wiring 13 is formed of a laminated film of a metal film 14 as an Al film and a refractory metal-containing film 15 as a TiN film on the metal film 14.

[0007] Thereafter, the SiO formed by a method capable of obtaining excellent embedding characteristics in the recess between the wirings 13.
_The wiring 13 is covered with an insulating film 16 such as a ₂ film, an insulating film 17 such as a SiO ₂ film is formed on the insulating film 16 by a method having a high deposition rate, and a resist 21 is applied on the insulating film 17. Then, the opening 22 of the pattern of the connection hole is formed in the resist 21 by lithography, and the connection hole 23 for the wiring 13 is formed by dry etching using the resist 21 as a mask.
Is formed on the insulating films 17 and 16.

Thereafter, although not shown, the resist 21 is removed by ashing, the connection hole 23 is filled with an adhesion film, which is a TiN film, and a metal plug made of W, and an upper layer wiring and the like are formed. This completes the semiconductor device. In addition,
When the metal film 14, which is an Al film, is exposed when the connection hole 23 is formed, when the connection hole 23 is buried later, T
When the iN film is formed, the Al film is nitrided and the connection hole 23 is formed.
The connection resistance at the point increases. Therefore, the refractory metal-containing film 15 is laminated on the metal film 14 so that the metal film 14 is not exposed when the connection hole 23 is formed.

[0009]

However, when forming the connection hole 23 for the wiring 13 having the borderless structure,
The connection hole 23 also deviates from the wiring 13 by the amount of misalignment caused by lithography for forming the opening 22. For this reason, when the amount of over-etching necessary to form the connection hole 23 increases due to variations in the thickness of the insulating films 17 and 16 and the like, the refractory metal-containing film 15 is also etched from the lateral direction, As shown in FIG. 2, an exposed portion occurs in the metal film 14. As a result, the connection resistance in the connection hole 23 increases about 10 to 100 times for the above-described reason.

Therefore, the present invention provides a semiconductor device with a high degree of integration, in which a connection hole is reliably formed on a wiring even if a margin area for the connection hole is not provided in the wiring, and the wiring interval is small. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be manufactured with a yield.

[0011]

In a method of manufacturing a semiconductor device according to the present invention, a wiring is covered with a first insulating film having a thickness larger in an inner region than an edge region of the wiring. By selectively etching the second and first insulating films under the condition that the etching rate of the first insulating film is higher than that of the second insulating film on the insulating film, a connection hole for a wiring is formed. For this reason, the time from the start of etching until the depth of the connection hole reaches the depth of the wiring is longer in the edge region than in the inner region of the wiring, and even longer in the region shifted from the wiring.

Therefore, even if the selective etching region for forming the connection hole is not accurately positioned with respect to the wiring and deviates from the wiring to some extent, the connection hole reaches the inner region of the wiring first and the wiring is formed. It is difficult to reach the edge region of the wiring and the region shifted from the wiring, and the phenomenon that the edge region of the wiring is etched from the lateral direction is suppressed. For this reason, the connection hole is reliably formed on the wiring even if the wiring has no margin area for the connection hole.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. Also in the present embodiment, as shown in FIG. 1A, a semiconductor substrate 11 such as a Si substrate on which elements (not shown) such as transistors are formed.
An interlayer insulating film 12 is formed thereon, and a wiring 13 is formed on the interlayer insulating film 12. The wiring 13 is formed of a laminated film of a metal film 14 as an Al film and a refractory metal-containing film 15 as a TiN film on the metal film 14.

Next, as shown in FIG. 1B, a wiring 13 is formed by an insulating film 16 which is a 750 nm thick SiO ₂ film.
Is coated. The formation of the insulating film 16, using an inductively coupled plasma CVD apparatus, SiH ₄ in the CVD apparatus
At the same time as supplying / O ₂ / Ar as a source gas, high-frequency power is applied to the mounting table of the semiconductor substrate 11.

As a result, the deposition of the SiO ₂ film and the deposited S
Sputter etching by Ar on the shoulder of the iO ₂ film proceeds simultaneously, and an insulating film 16 having a triangular cross section is formed on the relatively narrow wiring 13, and the insulating film 16 is formed on the relatively wide wiring 13. Denotes an insulating film 16 having a trapezoidal cross section.
Is formed. The insulating film 16 formed in this manner has excellent filling characteristics in the recesses between the wirings 13.

Next, as shown in FIG. 1C, an insulating film 24, which is a SiN _x film having a thickness of 1100 nm, is formed on the insulating film 16 by a plasma CVD method, and the insulating film 24 is formed by chemical mechanical polishing. The film 24 is flattened to a thickness of 750 nm.
The insulating film 24 is left. Then, as shown in FIG. 1D, a resist 21 is applied on the insulating film 24, and an opening 22 having a pattern of connection holes is formed in the resist 21 by lithography.

Next, as shown in FIG. 1E, a parallel plate type plasma etching apparatus is used to
A connection hole 25 for the wiring 13 is formed in the insulating films 24 and 16 by dry etching under the following conditions using the mask as a mask. Source gas flow rate: C ₄ F ₈ / CH ₂ F ₂ / Ar / O ₂ = 7
/ 5/700/7 sccm Reaction chamber pressure: 6.5 Pa Upper electrode: 2000 W, 2 MHz Lower electrode: 750 W, 800 kHz

As described above, the insulating film 16 on the wiring 13
Has a triangular or trapezoidal cross-section, the thickness of the insulating film 24 is larger in the edge region than in the inner region of the wiring 13 and even greater in the region shifted from the wiring 13. In addition, in the dry etching under the above conditions, the insulating film 16 is more
Has a high etching rate. For this reason, the time from the start of dry etching until the depth of the connection hole 25 reaches the depth of the wiring 13 is longer in the edge region than in the inner region of the wiring 13, and in the region shifted from the wiring 13. Even longer.

Therefore, as shown in FIG.
Even if misalignment occurs in the lithography for forming the opening 22, the connection hole 25 first reaches the inner region of the wiring 13 and hardly reaches the edge region of the wiring 13 or the region shifted from the wiring 13, The phenomenon in which the refractory metal-containing film 15 is etched from the lateral direction is also suppressed. Therefore, wiring 1
Even if 3 has a borderless structure, a good connection hole 25 is reliably formed on the wiring 13.

Thereafter, although not shown, the resist 21 is removed by incineration, the connection hole 25 is filled with an adhesion film, which is a TiN film, and a metal plug made of W, and further upper wirings and the like are formed. This completes the semiconductor device. As is clear from the above description, the number of steps for forming the connection hole 25 is not particularly increased as compared with the number of steps for forming the connection hole 23 shown in FIG.

In the above embodiment, the insulating films 16, 2
4 as SiO_TwoFilm and SiN _xAlthough a membrane was used,
The etching rate is higher in the insulating film 16 than in the edge film 24.
If the conditions can be realized, the insulating films 16 and 24
Then, another type of insulating film may be used. In addition,
In the embodiment, the metal film 14 which is an Al film and the metal film 14
And a high-melting-point metal-containing film 15 as a TiN film.
Although the line 13 was formed, the wiring 13 was formed with another type of conductive film.
May be implemented.

[0022] In the above embodiments, an inductively coupled plasma CVD apparatus, by advancing the sputter etched at the same time with respect to SiO ₂ film deposited with SiO ₂ film deposition, on the wiring 13 of the wiring 13 The insulating film 16 is formed so as to be thicker in the inner region surrounded by the edge region than in the edge region. However, if such a distribution thickness can be obtained, the insulating film 16 may be formed by another method. A film 16 may be formed.

[0023]

In the method of manufacturing a semiconductor device according to the present invention, the connection hole is reliably formed on the wiring even if a margin area for the connection hole is not provided in the wiring.
A semiconductor device with a small wiring interval and a high degree of integration can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a side sectional view of a semiconductor device sequentially showing one embodiment of the present invention.

FIG. 2 is a side sectional view of a semiconductor device manufactured in a conventional example of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate (base), 12 ... Interlayer insulating film (base), 13 ... Wiring, 14 ... Metal film, 15 ... High melting point metal containing film, 16 ... Insulating film (first insulating film), 24 ... Insulating film (Second insulating film), 25 ... connection hole

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (4)

[Claims] A step of forming a wiring on a base; and forming a wiring on the base such that a thickness of the wiring is thicker in an inner region surrounded by the edge region than in an edge region of the wiring. Forming a first insulating film to cover the wiring with the first insulating film; forming a second insulating film on the first insulating film; Forming a connection hole for the wiring by selectively etching the second and first insulating films under conditions where the etching rate is higher in the first insulating film than in the film. Production method. 2. The method according to claim 1, wherein an SiO ₂ film is formed as the first insulating film, and a SiN _x film is formed as the second insulating film. 3. The wiring according to claim 1, wherein the wiring is formed of a laminated film of a metal film and a high melting point metal-containing film laminated on the metal film.
The manufacturing method of the semiconductor device described in the above. 4. The method according to claim 1, wherein the deposition of the first insulating film and the sputter etching are performed simultaneously when the first insulating film is formed.