JP2002169852A - Method for detecting oscillation part in loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a verification method which detects and verifies an oscillation loop circuit. SOLUTION: With respect to a loop detection means which detects inhibited negative feedback of the positive feedback and negative feedback circuits in an internal circuit in the stage of logical verification, a route where the signal polarity is inverted between at least one input terminal and an output terminal of each of elements constituting the internal circuit and information of an input condition which is required to settle an output value independently of the input value of the other input terminal are generated and updated on the basis of preliminarily determined truth value information 11 and are stored as a library in a storage medium 12 of a logical verification device. The library is cited to discriminate whether the internal circuit has an oscillation loop constitution or not, and the discrimination result is displayed on an external display means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting an oscillating component in a loop circuit, and more particularly to an ASIC (Application) which is an IC for a specific application in a semiconductor device.
In many cases, various circuits are configured for a specific purpose in a time-specific IC (SOC) or a composite IC such as an SOC (System On Chip), and therefore, there is a high risk of creating a negative feedback loop using logic gates. Therefore, the present invention relates to an improved method for detecting an oscillation configuration portion in a loop circuit in which a negative feedback loop is detected before it is built in a chip.

[0002]

2. Description of the Related Art In recent years, with the advancement of the miniaturization technology of semiconductor devices, the scale of LSIs composed of the semiconductor devices has been increased.
SOC which is a semiconductor memory, a microcomputer, or a composite LSI in which these LSIs are mounted on one chip
Are also increasing in capacity. With the increase in capacity, the circuit function becomes complicated, and improving the accuracy of circuit verification at the design stage is one of the important issues.

In the internal circuits of these LSIs, a positive feedback loop or a negative feedback loop exists as a loop circuit using logic gates. In particular, if a negative feedback loop is present, in an actual device, the logic circuit oscillates → intermediate voltage, causing a leakage current. Cause you to

The negative feedback loop that causes such a problem is intended for an LSI such as an externally sold ASIC, which is mainly designed in a small scale (100K or less in number of gates) and often requires manual circuit design. It was not built into the internal circuit unless it was built specifically.

[0005] However, in recent years, the design has become large-scale, and in circuit design, an automatic design technique using a logic synthesis tool or the like has often been used. I'm starting to do it.

[0006] The circuit scale tends to further increase in the future, and it is thought that such cases will increase in the future.

[0007]

In a conventional ASIC or SOC, for example, as described above, even when such a design environment changes, a mechanism for specifically detecting an oscillation loop portion is as follows.
Although not yet developed so far, for example, Japanese Patent Application No. 1-193668 discloses an example of a method for verifying whether or not oscillation has occurred from a logical transition by using a logic simulation.

Referring to the verification method described in the publication, it is determined whether or not oscillation occurs based on a logic transition from a specific time t to t + Δt. However, depending on the circuit configuration, an initial value cannot be put in a loop. In the logic simulation, the internal logic is indeterminate to indeterminate at time t and a little later at t + Δt, and it is not possible to see the logic transition, and it is not possible to make a determination.

For example, referring to FIG. 12 showing an example of a circuit for explaining the above-mentioned conventional verification method, this circuit has an NA
It has one loop of ND12a → AND12b → NAND12a, and the input terminal B is HIGH_CLAMP (“1”).
Is clamped to the logic level "1" by the logic 12c, so that NAN is
The output of D12a is indeterminate from the beginning, and the inversion of the indeterminate is indeterminate no matter how much the time advances.

Therefore, as shown in FIG. 13 showing a waveform diagram of the simulation result, since the input A at the time t = 0 is X, X continues to circulate from the output Y to the input A thereafter. An uncertain X flows from the beginning (time t = 0) to the end, and it is not known whether or not oscillation occurs.

However, referring to FIG. 14 showing the input / output waveforms of the NAND 12a on the actual device, the logic level HI
Since the value of GH (= 1) / LOW (= 0) is repeated and gradually stabilized near the intermediate voltage, a through current may flow.

Further, in the method using a logic simulator, the possibility of detection largely depends on the quality of VECTOR. However, as the circuit scale becomes larger, it is more difficult to create a VECTOR that toggles all internal nodes. At present, it is becoming difficult to respond.

An object of the present invention has been made in view of the above-mentioned drawbacks of the related art, and by preparing a library having information based on a specific rule for each logic gate, it is possible to improve the circuit itself. Oscillation loop circuit detection,
It is to provide a verification method for performing verification.

[0014]

SUMMARY OF THE INVENTION The present invention provides a method of detecting an oscillation component in a loop circuit, comprising the steps of: verifying a prohibited negative feedback loop in a positive feedback and negative feedback loop circuit in an internal circuit of a semiconductor device; As a loop detecting means for detecting the signal, a path in which the signal polarity is inverted between at least one input terminal and an output terminal of each of the elements constituting the internal circuit, and an output value determined regardless of the input value of the other input terminal The information of the input conditions necessary for this is created and updated based on the predetermined truth value information to make a library in the storage means of the logic verification device, and while referring to the library, the configuration of the internal circuit causes an oscillation loop. A determination is made as to whether or not the configuration is established, and the determination result is displayed on an external display means.

In the above negative feedback loop, one of the input terminals of each of the exclusive OR and the exclusive NOR is used as a path, and the logic level of the other input terminal outside the negative feedback loop is clamped. If you are certain,
Verification can be performed by replacing the exclusive OR or exclusive NOR with an inverter or a non-inverter based on the truth value information.

Further, in the negative feedback loop having one input terminal of each of an exclusive OR and an exclusive NOR, a logic level of the other input terminal outside the negative feedback loop is specified. In the case of uncertainty due to an element or a specific functional block, inversion or non-inversion verification of the signal polarity in the negative feedback loop is not performed, and only verification of another block in the path of the other input terminal outside the negative feedback loop is performed. You can do it.

Further, when a small negative feedback loop is further present in the detected negative feedback loop, the small negative feedback loop is verified in advance, and the oscillation stop condition of the library in the small negative feedback loop is determined. If the value that satisfies is confirmed, continue tracing after loop interruption,
The input value of the other input terminal outside the small negative feedback loop may be uncertain and the negative feedback loop may be cut off to continue the trace.

The logic inversion path stored in the library is defined as a connection path in the negative feedback loop in which the logic is inverted between input and output terminals.
The oscillation stop condition defines information as to which value does not cause oscillation if the signal input value from the other input terminal outside the negative feedback loop is fixed.

Further, referring to the library,
A loop detection process of tracing the output stage starting from all the elements to be verified and detecting the element as the loop when returning to an already visited element, and performing exclusive OR or exclusive negation on the loop. When the sum is detected, it is possible to verify whether the input signal level from the other input terminal outside the loop is fixed, and determine whether or not it can be replaced with an inverter or a non-inverter based on the truth value information. Then, the processing of the exclusive OR or the exclusive OR to be replaced is performed, and each element in the loop is checked against the logical inversion path in the library, and how many inversion paths exist in the entire loop. Positive / negative feedback check processing to determine a negative feedback loop if the result is odd, and a positive feedback loop if the result is zero or even; In the case of a loop and when the inverter or the non-inverter cannot be replaced, each element in the negative feedback loop determines whether or not the output logic is fixed by an input signal from the other input terminal outside the loop. Out-of-loop input check processing for sequentially verifying the elements of the previous stage, and when the out-of-loop input check processing has not obtained confirmation that there is no problem, information on which element has a loop configuration is obtained. Specifically, there is provided a problem display process for ending the verification of the loop, and a loop detection confirmation process for confirming whether all the loops detected in the loop detection process have been detected.

Further, a specific element or a specific functional block which determines that the output logic is not fixed in the out-of-loop input check processing and does not trace back to the preceding element is a sequential circuit, an input / output circuit. , Adder, parity generator all terminal connection,
The terminal connection of the enable part of the latch, the multiplexer and the decoder is used.

Also, in the out-of-loop input check processing, it is arbitrarily selected whether or not to execute a trace going back to the preceding element.

Furthermore, in the input check processing outside the loop, the number of stages of the preceding trace is arbitrarily specified, and if the value is not determined or undetermined within the number of stages, it is treated as indeterminate.

Further, the processing of the exclusive OR and the exclusive NOR is performed by determining whether or not the exclusive OR or the exclusive NOT is included in the logical loop found in the loop detection processing. The first exclusive OR or exclusive OR operation, and the exclusive OR operation or exclusive OR operation detected in the preceding process, which has not been verified yet. An input stage tracing process for selecting whether or not an input value from the other input terminal outside the loop for the selected element is fixed, and the exclusive logic that performs a pre-stage trace in a pre-stage process. It is determined whether or not the sum or the exclusive NOR can be replaced with an inverter or a non-inverter. A replacement determination process to be shifted, a replacement execution process for replacing the exclusive OR or the exclusive NOR calculated by the input stage process in response to the determination result of the replacement determination process with an inverter or a non-inverter; If there is another exclusive OR or exclusive NOR found in the exclusive OR or exclusive NOR operation, the input stage trace processing is repeated for the exclusive OR or exclusive NOT, and the detection is performed again. When the determination is no longer made, a second exclusive-OR or exclusive-NOR presence / absence determination process for determining the continuation of the verification and proceeding to the positive / negative feedback process is provided.

If the input value from the other input terminal outside the loop, which is input to the exclusive OR or the exclusive NOR verified in the input stage tracing processing, is a logical level "1", If the inverter is "0", it is determined that replacement is possible with a non-inverter, and the process proceeds to the next process. In other cases, replacement is determined to be impossible and the process proceeds to the input check process outside the loop.

Further, the positive / negative feedback processing may be any of the elements detected in the loop verification processing or an arbitrary part of the loop partially converted by the exclusive OR operation or exclusive NOR operation processing. A starting point determination process of selecting an element as an element to be verified, and whether or not a signal polarity is inverted between input / output terminals in the loop of the element currently being verified is determined by a logical inversion path defined in the library. Inversion path passage determination processing for determining whether the connection is within the loop, and verification results of the inversion path passage determination processing,
When the signal polarity between the input and output terminals in the loop of the element under verification is inverted, the number of inversions is increased by one, and the number of inversions that is cleared when the positive / negative feedback processing is completed.
1 processing, a next-stage element selection process for newly selecting a subsequent-stage device as a verification target device, and whether the newly selected device in the next-stage device selection process is the same as the one selected in the start point determination process And, if they are the same, proceed to the next processing, and if not identical, return to the inversion path passing determination processing. The start point return determination processing, and the inversion number as a result from the inversion path passage determination processing to the start point return determination processing. If the number of inversions stored in the +1 process is an even number, it is determined that the feedback is positive, and the process proceeds to the problem display process. If the number is an odd number, the process proceeds to the out-of-loop input check process.

Further, in the input check processing outside the loop, an arbitrary element in the loop in which the exclusive OR or the exclusive NOR is replaced with another element is selected as an element to be verified first. Starting point determination processing, and determining whether the element currently being verified is the exclusive OR or the exclusive NOR, and determining the exclusive OR or exclusive NOR to proceed to the subsequent specified processing, respectively. Processing, and confirms whether or not the element currently being verified has the oscillation stop condition in the library. If the oscillation stop condition does not exist, the process proceeds to a subsequent element selection process, and the oscillation stop condition exists. In this case, the process for confirming the presence or absence of an oscillation stop condition that proceeds to the next stage input stage tracing process is performed. An input stage tracing process for verifying whether an input value from a terminal is fixed, and an input value from the other input terminal outside the loop for a device under verification obtained at the input stage tracing process, An oscillation stop condition comparison process for comparing with the oscillation stop condition,
If the determination result obtained in the oscillation stop condition comparison process satisfies the oscillation stop condition, the process proceeds to the next stage process; otherwise, the process proceeds to a subsequent process, that is, the next stage element selection process. If the input value from the input terminal outside the loop determined to satisfy the oscillation condition in the presence / absence confirmation processing and the presence / absence confirmation processing of the oscillation loop is fixed by a clamp, the verification of the loop currently being verified ends. When the oscillation is stopped due to the use condition of the external terminal, a condition presence / absence check process for proceeding to the next stage process, and when there is a condition for oscillation stop in the condition presence / absence check process, a condition explicit process for externally displaying the condition. In the case where it is not possible to obtain the confirmation that the oscillation can be stopped by the input value of the other input terminal outside the loop from the element currently being verified and in the case of the conditional stop, the current verification in the loop is performed. Next-stage element selection processing for selecting an element at a subsequent stage of the element as a new verification target element, and determining whether the element selected as the verification target element is the same as that selected in the start point determination processing, and In the case of (2), a verification completion check process is performed in which the process is passed to the external display process as having a conditional passage or a problem, and if not the same, the process returns to the exclusive OR or exclusive OR determination process.

In the input stage tracing process, an immediately preceding device connected to the input terminal outside the loop of the device verified in the immediately preceding process is newly selected as a device to be verified. A first element selection unit and a verification that determines whether the verification target element selected by the first element selection unit is a previously visited element, and branches into a case where the element has already visited and a case where the element is visited for the first time; Element determination processing;
If it is determined in the verification element determination processing that the element has already been visited, the path is excluded from the verification target, and the value from the path is an undetermined value setting processing. It is determined whether the input value from the other external input terminal is determined to be "0", "1", or "indeterminate". If not, the process returns to the preceding element selection processing of "0". 1 "" uncertain "determination processing.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention, as a method of detecting a negative feedback loop caused by a logic gate in particular, makes a database of prohibition information and constructs a verification system for circuit rule check (logic tracing). This makes it possible to supply high-quality chips by eliminating defects caused by such problems.

First, a first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1 which is a flowchart showing a method for detecting an oscillation component in a loop circuit according to a first embodiment of the present invention, the method is applied to a logic verification device (not shown), and , An exclusive-OR or exclusive-NOR process S2 (FIG. 2 described later), a positive / negative feedback check process S3 (FIG. 3 described later), and an out-of-loop input check process S4 (FIG. 4 to be described later), output processing S5 such as display processing and printing processing for displaying a problem by clearly indicating a circuit location, and "input stage trace" started as a subroutine from processing S1 and processing S4. The processing of FIG. 5 showing the processing is included. Further, it includes a storage medium including truth value information 11 and a dedicated library 12 (FIG. 6 described later) necessary for controlling the processes S2 and S4.

The loop detecting process S1 is a process of searching for a loop portion by using a known technique. That is, the output stage is traced starting from all the elements, and when returning to the element visited so far, the element is detected as a loop.

In the search, since the purpose is to find a loop composed of only logic gates, and from the rule of thumb, if these elements are included, oscillation does not occur. Connection described below) is excluded from the search target, and another route is searched. That is, it is determined that the route is not in a loop.

Specific elements connected by a loop not to be verified: sequential circuit, LATCH and MULTIPLEXER
ENABLE part between NETWORK and DECODER, I / O return, connection to ADDER.

Elements connected by a loop to be verified:
INVERTER, NON-INVERTER, OR,
NOR, AND, NAND, XOR, XNOR, composite gate, LATCH, MULTIPLEXER, and DECO
Data part of DER.

In the library (FIG. 6) necessary for executing the processes 3 and 4, two pieces of information, that is, the logic inversion path oscillation stop condition, are defined in advance for each element. The logical inversion path literally defines "where is the path where the logic level is inverted between the input and output terminals" in the connection path in the loop.

As the oscillation stop condition, information is defined as to what value the input value from the other input terminal outside the loop is fixed and does not oscillate.

In step S2, a process is performed when there is XOR / XNOR. XOR / XNOR changes the polarity of the signal level between the input and output terminals depending on the input value from the other input terminal outside the loop, and therefore, exceptionally, from the other input terminal outside the loop, Trace the input first to verify that the input value from outside the loop is fixed.

If it is possible to fix the input value from outside the loop, XOR / XNOR is converted to INVERTER or NON-INVERT based on the truth value information 11.
Replace with ER. If the loop is not replaced, the loop cannot make a positive feedback / negative feedback determination (process 3), so that it is determined only from a non-loop input check (process 4) of another block.

In the process S3, each element in the loop is compared with a logical inversion path stored in the library, and the number of inversion paths in the entire loop is calculated. The positive / negative feedback of the loop is determined based on the result.

If the judgment result is an odd number, a negative feedback loop
If it is “0” or an even number, it is determined as a positive feedback loop. In the case of the positive feedback loop, since there is no oscillation in the circuit, it is determined that there is no problem with the loop. As mentioned above, I
If there is an XOR or XNOR that cannot be replaced with NVERTER or NON-INVERTER, this processing is not performed.

In the process S4, each element in the loop is determined by the input value from the other input terminal outside the loop.
Verify that the output logic may be fixed. As a method, an element at the preceding stage of those elements is verified.

It is determined that the element at the preceding stage is a logic gate or the like and is determined by a specific value when connected to a clamp or an external terminal. Since the output of the preceding element is not fixed, it is determined that the value is not fixed by the connection. In the case of other elements, the preceding element is further verified.

A connection element which determines that the logic level is not fixed and does not perform any further preceding trace: a sequential circuit,
I / O wrap, adder, all connections of parity generator, connection of latch, multiplexer and enable part of decoder.

As a result of the preceding trace, when the input value from the other input terminal outside the loop of the element is fixed for the element in the loop, the oscillation stop condition stored in the library is compared with the oscillation stop condition stored in the library. Then, it is determined whether or not the output logic level of the element in the loop is fixed. If it is fixed depending on the usage conditions of the external terminal, the condition is also specified.

Strictly speaking, since the former-stage trace itself is possible even with the above-described elements / connections, it may be possible to arbitrarily select whether to perform verification.

In addition, the number of steps in the preceding trace is basically determined or not, but verification is to be performed until it becomes clear. However, the number of steps is arbitrarily specified, and the value within the number of steps is specified. If the finalization or uncertainty is not determined, the system may be treated as indeterminate.

As another condition for terminating the input trace, there is a case where an element which has been visited has come out. In such a case, a double loop is structurally formed, and the loop is cut forever because the loop continues forever.

If the output processing S5 does not provide sufficient confirmation to determine that there is no problem, information on which element is in the loop configuration is clearly displayed on an external display means, and verification of this loop is performed. To end.

For clarification, a specific name given in the circuit data for each element is used to specifically indicate which connection is a loop that may oscillate on an actual device.

Finally, in step S6, it is confirmed whether or not all the loops detected in loop detection processing S1 have been detected.

Next, FIG. 1 showing a detailed description, conditions, and reasons for the above-described individual processing, and an overall flowchart of the verification method of the present invention, and FIG. 2 showing a detailed flowchart of each processing. The embodiment will be specifically described with reference to FIGS.

First, the processing in FIG. 1 will be described. In "find loop configuration" of the process S1, a loop portion is searched. When the process S1 ends, the process moves to the process S2. The algorithm for finding the loop and its conditions are as described above.

In the processing S2 "XOR / XNOR processing", XOR / XN is added to the loop detected in the processing S1.
If there is OR INVERTER / NON-INVER
Attempt to replace with TER. If there is XOR / XNOR and replacement cannot be performed, the process proceeds to the process S4 without performing the process S3. Otherwise, the process moves to step S3.

In the process S3 "positive / negative feedback check", it is found in the process S1, and in some cases, XOR / X
It is determined whether the loop in which NOR is replaced by another block is a positive feedback loop or a negative feedback loop.

In the case of the positive feedback loop, the verification of the loop ends, and the process proceeds to step S6. Processing S in case of negative feedback loop
Move to 4. This determination is made by verifying how many "logical inversion paths" described in the "dedicated library" are used for connections in the loop.

The process S4 "input check outside the loop" is a process performed when it is determined in the process S3 that the loop is a negative feedback loop, or when all the XOR / XNOR cannot be replaced in the process S2.

From the other input terminal outside the loop for each element (excluding XOR / XNOR) in the loop detected in processing S1 or in the loop in which XOR / XNOR is replaced by another element in processing S2. It is determined whether the output is fixed by the input value of.

As a result, if the input outside the loop is fixed by the clamp and does not oscillate universally when compared with the "oscillation stop condition" defined in the "dedicated library", The verification of the loop ends, and the process proceeds to step S6. Otherwise, that is, conditional OK,
Alternatively, if there is a problem, the process proceeds to step S5.

The process S5 "specify the circuit location and display the problem" is performed when it cannot be confirmed that the oscillation does not occur universally as a result of the process S4. In particular,
This includes the case where it is not possible to confirm that the oscillation is stopped by the input value from the other input terminal where the loop verified in the process S4 is outside the loop, and the case where the oscillation is stopped depending on the use of the external terminal. In the latter case, the usage conditions of the external terminal are also displayed here. When this process ends, process S
Move to 6.

In the process S6 "Is there another loop?"
Check if there is another loop to verify in the circuit. If there is, the process returns to step S2 to perform a series of verifications.
If not, the process ends.

Next, a flow that is always performed after the loop is found in the process S1, that is, the process S2 “X” in FIG.
FIG. 2 showing a detailed verification method of “OR / XNOR processing”
Will be described. Since the processes S1 and S6 in FIG. 1 are well-known technologies, detailed description of the operations here is omitted.

Process S2a "XOR / XNOR presence / absence"
Is XOR / XNOR in the loop found in process S1.
Check if is included. If at least one is included, the process proceeds to step S2b; otherwise, the process immediately proceeds to step S3 in FIG.

The process S2b "input stage trace" is a process S2b.
One of the XOR / XNORs that have not been verified yet is selected in 2a, and it is verified whether the input value from the other input terminal outside the loop for the element is fixed.

FIG. 5 shows a more detailed verification method for the operation of the "input trace" portion, and this processing will be described later. When a return value is obtained as a result of executing the processing shown in FIG. 5, the process proceeds to processing S2c.

Process S2c "(NON-) INVERTE
Can be replaced with R? "Inverts the XOR / XNOR traced in the preceding stage in the process S2b to INVERTER / NON-I
It is determined whether it can be replaced with NVERTER.

Specifically, the XOR verified in step S2b
If the input value from the other input terminal outside the loop input to / XNOR is "1", it can be replaced with INVERTER, and if it is "0", it can be replaced with NON-INVERTER, and the process moves to step S2d. .

In other cases (undefined), it is determined that replacement is impossible, and the process goes to the process S4 in FIG. 1 at a stretch. This means that if there is a plurality of XOR / XNORs and there is at least one that cannot be replaced, the process moves to the process 4 in FIG.

The process S2d "perform replacement" is a process S2d.
In response to the determination result of step 2c, the XOR / XNOR determined in step S2c is changed to INVERTER / NON-IN
Replace with VERTER.

After that, the procedure moves to the processing S2e. Processing S2e
"Is there another XOR / XNOR?"
If there is another XOR / XNOR found in a, the process is performed again from the process S2b for that XOR / XNOR. If not, the process moves to the process S3 shown in FIG.

Next, the process S3 in FIG. 1 will be described with reference to FIG. 3, which describes a detailed verification method. As a result of the XOR / XNOR verification in the processing S2, this processing includes the XOR / XNOR in the loop detected in the processing S1.
Does not exist, or XOR / XNOR exists but all INVERTER / NON-INVERTE
This is performed when R can be replaced, and the content is determined as to whether the loop is a positive feedback loop or a negative feedback loop.

In the process S3a "determining the starting point", the process S3a
In step 1, an arbitrary element in the loop partially converted in processing 2 is selected as a verification element. Ultimately, all S elements are verified under the same conditions, so this selection method is arbitrary and does not cause any problem. After the selection, the process moves to step S3b.

In the process S3b "pass the inversion path?", It is verified whether or not the polarity of the input and output signals is inverted between the input / output terminals in the loop of the element currently being verified.

The element currently being verified is the element selected first in step S3a or the element newly selected as a verification element in step S3d described later. In the verification method, if the connection of the “logical inversion path” defined in the library (FIG. 6) is in the loop, it is determined that the connection is through the inversion path, and the process proceeds to step S3c. Otherwise, the process moves to step S3d.

The process S3c "the number of inversions + 1" is the same as the process S3b
Is performed when the polarity of the input and output signals is inverted between the input and output terminals in the loop of the element being verified.

The number of inversions is internally increased by one. The internal memory is cleared when the process S3 is completed, but is kept until that time. After this processing ends, the flow shifts to processing S3d.

In the process S3d "to the next stage", the element to be verified is moved to another element. Specifically, the latter element is selected as a new element to be verified. Processing S3 following this processing
Move to e.

In the step S3e "Return to the starting point?", It is determined whether or not the element selected as the element to be verified is the same as the element selected in the step S3a as a result of the execution of the step S3d.

If the selected elements are the same, the verification has been performed for all the elements in the loop.
Move to 3f. If they are not the same, the process returns to step S3b and the same verification is performed.

In the process S3f "determination", the processes S3b to S3b
The process is performed depending on whether the inversion number internally stored as a result up to 3e is even or odd. In the case of an even number, it is determined to be a positive feedback loop, and the next transfer destination is the process S5 in FIG.

On the other hand, in the case of an odd number, the processing S in FIG.
It becomes 4. Whichever direction is moved, the number of reversals held as internal memory is cleared once here.

Next, the process S4 in FIG. 1 will be described with reference to FIG. 4 showing a flowchart of a detailed verification method.

This process is performed when the result of the positive / negative feedback check verified in the process S3c indicates that the process is a negative feedback loop.
Also, this is performed when it is not possible to replace all the XOR / XNOR in the loop detected in the processing S1 with another element as a result of the XOR / XNOR verification in the processing S2b.

The contents are detected in step S1, and in some cases, XOR / XNOR is replaced by another element in step S2, and all the elements in the loop are output from the other input terminal outside the loop. Verify whether the output value is fixed by the input signal.

In the process S4a "deciding the starting point", the process S1
XOR / XNO in step S2 in some cases.
In verifying all the elements in the loop in which R has been replaced by another element, an arbitrary element is selected as the element to be verified first.

Since all the elements are finally verified, the selection of the elements is arbitrary and does not cause any problem. After this processing, the procedure moves to processing S4b.

In the process S4b "XOR / XNOR?"
It is determined whether the currently verified element is XOR / XNOR. The element currently being verified is an element that is first selected in step S4a or that is newly selected as a verification element in step S4i described below.

The element currently being verified is XOR / XNOR
In this case, whether or not the input value from the other input terminal outside the loop is fixed has been already performed in step S2b before reaching this point. Therefore, since it is unnecessary to further verify the device, the process immediately proceeds to the process 4i. Otherwise, the process proceeds to step S4c to perform the normal verification.

In step S4c "Oscillation stop condition?"
It is checked whether the element currently being verified has the “oscillation stop condition” defined in the dedicated library (FIG. 6).

The element to be verified at present is the element selected first in step S4a or the element newly selected as a verification element in step S4i described later. For example, IN
Elements such as VERTER which have only one input terminal and cannot stop oscillation from outside the loop do not have the "oscillation stop condition".

If there is no "oscillation stop condition", it is determined that the output value will not be fixed by the input value from the other input terminal outside the loop, and it is not necessary to further verify this element. Move on. If there is an "oscillation stop condition", the process proceeds to step S4d.

The process S4d "input stage trace" verifies whether or not the input value from the outside of the loop of the currently verified element is fixed. The element currently being verified is an element that is first selected in step S4a or that is newly selected as a verification element in step S4i described below.

In step S4c, the process is performed when the element currently being verified has the "oscillation stop condition" defined in the dedicated library (FIG. 6). FIG. 5 shows a more detailed verification method for the operation of this part, and FIG. 5 will be described later. When a return value is obtained as a result of the processing shown in FIG. 5, the process proceeds to processing S4e.

The process S4e "comparison with the oscillation stop condition" is performed by comparing the input value from the other input terminal outside the loop of the element currently being verified obtained in the process S4d with the value in the dedicated library (FIG. 6). A comparison is made as to whether the condition defined as “oscillation stop condition” is satisfied.

If the input value from the outside of the loop obtained in step S4d is undefined (X), it is not satisfied regardless of the condition presented as the "oscillation stop condition" in the dedicated library (FIG. 6). become. Thereafter, the process proceeds to step S4f.

In the process S4f "Oscillation stops?"
The next destination changes according to the result of the determination made in 4e.
Specifically, if the determination result obtained in step S4e satisfies the condition presented as the "oscillation stop condition" in the dedicated library (FIG. 6), no oscillation occurs in this loop. The processing moves to S4g.

This includes a case with a condition such as “Satisfy, but only when the external terminal is ○”. If not, the process proceeds to step S4i to verify other elements.

Processing S4g "condition exists?"
This is a process that is performed when the element currently being verified can stop oscillation by an input value from the other input terminal outside the loop. The device currently being verified is the process S4
The element selected first in step a or the element newly selected as a verification element in step S4i described below is targeted.

In the process S4d, the input from outside the loop is traced, and when it is determined that the input value of the other input terminal from outside the loop is fixed, whether the value is fixed universally by the clamp. The next destination branches depending on whether the external terminal may be fixed depending on the use conditions.

In the case where the loop is universally fixed by the clamp, it can be determined that the loop found in the currently verified process S1 does not oscillate at this time, so that the verification of this loop is completed and FIG. It moves on to the process S6 where it is. When it is determined whether or not the oscillation stops depending on the use condition of the external terminal, the process proceeds to step S4h.

The process S4h "specify condition" indicates a condition for stopping oscillation in the process S4g described above, if any. After this processing, the procedure moves to processing S4i.

The processing of step S4i "to the next stage" is performed when it is not confirmed from the element to be verified that the oscillation can be stopped by the input value from the other input terminal outside the loop, and Performed when possible but conditional and not universal.

In order to verify other elements in the loop, the element following the element currently being verified is selected as a new element currently being verified. After processing, processing S4j
Move to.

In the process S4j "Return to the starting point?", It is determined whether or not the device selected as the device to be verified is the same as the device selected in the process S4a as a result of the process S4g.

If the values are the same, the verification has been performed for all the elements in the loop. Therefore, as a verification result of the entire process S4, the condition shown in FIG. Move to processing S5. If not identical,
Returning to the process S4b, the same verification is performed.

Finally, a description will be given with reference to FIG. 5 which shows a detailed flowchart of the "input stage trace" activated as a subroutine in the processing S2b and the processing S4d in FIG. 4 in FIG.

In the process SRa “previous stage”, an element one stage before the element currently being verified is newly selected as an element to be currently verified. When first visiting here, processing S2
(b) Select the element at the previous stage from the other input terminal outside the loop of the element being verified at the time of startup from the processing S4d as the element to be verified now. If there is more than one, all will be selected. The determination regarding the (these) elements is performed in the next process SRb.

The processing SRb “has you visited before?”
If the element (group) selected in Ra is a previously visited element,
If you continue tracing that path, you end up in an infinite loop, so you need to cut it. If there is such a part, the process proceeds to processing SRc. If not, the process directly proceeds to processing SRd.

The processing SRc “cut small loop. The value is set to X” means that if the element (group) currently verified in the processing SRb is an element that has been visited before, the route is It is assumed that the value from the route is not determined (X) as not to be verified. Thereafter, the process proceeds to processing SRd.

In the process SRd “determine to any of 0, 1, and X?”, If the element (group) currently being verified is a clamp, it is determined to be “0” or “1” depending on its type and connection. It is determined.

In the case of an external terminal, it is assumed that any value of "0" or "1" can be determined (in that case, the value will be displayed later in the process S5 on condition of the determined value). In the case of a sequential circuit or the like, it is determined that it is not determined (X). In the case of other elements, the determination is suspended.

The detailed judgment conditions are as described above. From the places where these values obtained up to this point are determined / not performed / determination pending, the processing S
2b / Input value from outside the loop to the element being verified when activated from processing S4d is “0” / “1” /
It is determined whether "X" is determined.

If neither “0” / “1” / “X” is determined, the process returns to the processing SRa again.
The process returns to step S2c or S4e with the value to be determined as a return value.

Next, a first embodiment to which the above-described verification method is applied will be described with reference to FIG. 7 showing a specific example of a circuit to be verified.

Process S1 (FIG. 1): Finding a loop configuration (this process is an application of a known technique) As an example, AND7a with INVERTER shown in FIG. 7 → NON-INVER
Assume that only one loop of TER7b → two-input OR7c → AND7a is found.

Process S2 (FIG. 1): The XOR / XNOR process is a process performed when there is an XOR / XNOR in the loop found in the process S1.

Process S2a (FIG. 2) → “XOR in loop
Is / XNOR available? Since there is no "→", the process proceeds to the processing S3 with "verification continued".

Process S3 (FIG. 1): The positive / negative feedback check verifies whether the loop found in process S1 is a positive feedback loop or a negative feedback loop.

Process S3a (FIG. 3): One starting point for verification is determined in the loop found in process S1. Here, it is assumed that the AND is 7 (7a in FIG. 7).

Process S3b (FIG. 3): AND (7 in FIG. 7)
Input / output path in the loop of a) (input A → output Y)
Verify that is a logical inversion. It is checked with the "logical inversion path" in FIG.

In the case of AND (7a) in FIG. 7, when the library is referred to, the path from input A to output Y corresponds to the logical inversion path, so that the path "passes", and the process shifts to step S3c.

Process S3c (FIG. 3): The number of inversions is incremented by 1 as internal storage, and the flow advances to process S3d.

Process S3d (FIG. 3): Since the verification of the AND 7a has been completed, the process proceeds to verification of another element.

NON-INVERT in the subsequent block
Move to ER7b. Move to processing S3e.

Process S3e (FIG. 3): It is confirmed whether all elements have been verified. The starting point selected in step S3a is A
Since the ND 7a is not the NON-INVERTER 7b, the process moves to "NO". Process S3 on the flowchart
b (second time).

Process S3b (FIG. 3) -2: INVERTE
It is verified whether the input / output path (input A → output Y) in the loop at R (7b in FIG. 7) is logically inverted. It is checked with the “logical inversion path” column of the dedicated library in FIG. NON-IN of FIG.
In the case of VERTER 7b, since there is no inversion path from the library, the process proceeds to “not pass” and proceeds to the next process S3d.

Process S3d (FIG. 3) -2: NON-INV
Since the verification of the ERTER 7b has been completed, the process moves to verification of another element. Here, the process moves to the subsequent block OR7c and moves to the next process S3e.

Process S3e (FIG. 3) -2: It is confirmed whether all the elements have been verified. The starting point selected in the process S3a is the NAND 7a and not the OR 7c, so "NO"
Move to. Processing S3b on the flowchart (third time)
Hit.

Process S3b (FIG. 3) -3: OR (7 in FIG. 7)
Verify whether the input / output path in the loop in c) is logically inverted. It is checked with the "logical inversion path" in FIG.
In the case of OR7c in FIG. 7, since there is no inversion path with reference to the library, the process proceeds to “not pass” and the next processing S3
Move to d.

Process S3d (FIG. 3) -3: Since the verification of OR7c has been completed, the operation shifts to verification of another element. Here, the process moves to the subsequent block AND7a, and the next process S3e
Move to

Process S3e (FIG. 3) -3: It is confirmed whether or not all elements have been verified. The starting point selected in the process S3a is the AND 7a, and has returned to the starting point. Thus, a series of verifications is completed, the process proceeds to “NO”, and the process proceeds to the next process S3f.

Process S3f (FIG. 3): Judge. The total number of inversions stored internally is 1 and an odd number (defined in step S3c). The process proceeds to “inversion number = odd number”, and returns “negative feedback” as a result as the process S3.

If "negative feedback" is returned when returning to the process S3 in FIG. 1, the process moves to the process S4. It should be noted that the number of reversals of the internal storage is cleared once when the verification of the loop found in the process S1 is completed. (Return to 0) Process S
4 (FIG. 1): Verify whether oscillation can be stopped by an input from the other input terminal (B) outside the loop.

Process S4a (FIG. 4): In the loop found in process S1, one element as a verification start point is arbitrarily selected. It is assumed that AND (7a in FIG. 7) is set.

Process S4b (FIG. 4): AND 7a is XOR
/ XNOR (because it has been traced by another method in process S2). Since AND7a is not XOR / XNOR, the process proceeds to "NO" and moves to the next process S4c.

Process S4c (FIG. 4): The AND 7a confirms whether or not there is an oscillation stop condition. In the case of the AND 7a, if the input B is fixed at 0 with reference to the library of FIG. 6, the oscillation can be stopped, so that the process proceeds to "YES" and proceeds to the next process S4d.

Process S4d (FIG. 4): Trace (subroutine) the input stage from the other input terminal outside the loop to AND 7a.

Process SRa (FIG. 5): Traces one stage before AND 7a. The input B of the AND 7a is connected to the external terminal "I
N1 ".

Process SRb (FIG. 5): Checks whether the element located one stage before AND 7a found in process SRa has visited before. Since the user has not visited yet, the process proceeds to “NO” and proceeds to the next process SRc.

Process SRc (FIG. 5): The value is set to “0” / “1” / by the preceding stage input of AND 7a found in process SRa.
It is determined whether it is determined to be "X" (undefined). AN
The input B of D7a can be determined by connection from an external terminal. Therefore, the process proceeds to “YES” and proceeds to the process S4e in FIG.

Process S4e (FIG. 4): The return value after process S5 is compared with the oscillation stop condition.

From the oscillation stop condition obtained in step S4c, it is possible to stop oscillation as long as the external terminal obtained in step SRc is fixed at "0". Therefore, the process S4f
Move to

Process S4f (FIG. 4): It is determined from the result of process S4e whether oscillation stops. As a result of the determination, the operation stops, so that the processing proceeds to “YES”, and proceeds to the next processing S4g.

Process S4g (FIG. 4): Based on the result of process S4e, it is determined whether or not there is a condition for stopping oscillation. From the processing S4e, since there is a condition that the external terminal “IN1” is fixed at “0”, the processing proceeds to “YES” and proceeds to the next processing S4h.

Process S4h (FIG. 4): The condition confirmed in process S4g is specified. For example, in the case of this example, “there is no problem if the external terminal“ IN1 ”is fixed at 0”.

Process S4i (FIG. 4): Since verification of AND7a has been completed, verification of another element is performed. The subsequent block, NON-INVERTER 7b, is selected as a new element to be verified, and the process proceeds to S4j.

Process S4j (FIG. 4): It is checked whether the NON-INVERTER 7b, which is the currently verified element, has returned to the start point in the currently verified loop found in process S1. The starting point is AND7a, and since the element currently being verified is NON-INVERTER7b, the process proceeds to "NO" and proceeds to the next process S4b (second time).

Process S4b (FIG. 4) -2: NON-INV
Check whether ERTER7b is not XOR / XNOR (because it has been traced by another method in process S2). NON-IN
Since VERTER7b is not XOR / XNOR, "N
The process proceeds to O "and moves to the next process S4c-2.

Process S4c (FIG. 4) -2: NON-INV
Check whether the ERTER 7b has an oscillation stop condition. Referring to the library of FIG. 6, since there is no oscillation stop condition, the process proceeds to “NO” and proceeds to process S4i-2.

Process S4i (FIG. 4) -2: NON-INV
Since the verification of the ERTER 7b has been completed, the process proceeds to verification of another element.

The subsequent block OR7c is selected as a new element to be verified, and the flow advances to step S4j-2.

Process S4j (FIG. 4) -2: It is checked whether or not the OR7c, which is the currently verified element, has returned to the start point in the currently verified loop found in process S1. The starting point is AND7a, and the element currently being verified is OR7c, so the process proceeds to "NO" and proceeds to processing S4b (the third time).

Process S4b (FIG. 4) -3: OR7c is XO
Check if it is not R / XNOR (because it has been traced by another method in process S2). Since OR7c is not XOR / XNOR, the process proceeds to "NO" and proceeds to process S4c-3.

Process S4c (FIG. 4) -3: It is checked whether OR7c has an oscillation stop condition.

Referring to the library in FIG. 6, input B = 1
If the value is fixed in step (1), the oscillation can be stopped, so that the process proceeds to "YES" and proceeds to the next process S4d-3.

Process S4d (FIG. 4) -3: Trace the input stage from input terminal B outside the loop to OR7c (subroutine). Move to the next processing SRa-3.

Process SRa (FIG. 5) -3: Traces the previous element from the other input terminal B outside the loop of OR7c. The input B of the OR 7c is clamped at "0" (LOW). Move to the next processing SRb-3.

Process SRb (FIG. 5) -3: It is confirmed whether or not the element one stage before OR7c found in process SRa has visited before. Since it has not been visited yet, the process proceeds to “NO”, and proceeds to the next process SRc-3.

Process SRc (FIG. 5) -3: The value is set to "0" / "1" by the preceding stage input of OR7c found in process SRa.
/ "X" (undefined) is determined. In this case, since it is clamped at "0", it is fixed at "0", so the process proceeds to "YES" and proceeds to the process S4e-3.

Process S4e (FIG. 4) -3: Process SRc-3
Is compared with the input value “0” from the other input terminal B outside the loop to the OR 7 c obtained in the above and the oscillation stop condition. According to the oscillation stop condition obtained in step S4c-3, the oscillation does not stop even if it is clamped at "0". Next processing S4f-
Move to 3.

Process S4f (FIG. 4) -3: Process S4e-3
As a result, it is determined whether or not the oscillation stops. As a result, since the oscillation does not stop, the process proceeds to "NO" and proceeds to the process S4i-3.

Process S4i (FIG. 4) -3: Since the verification of OR7c has been completed, the flow advances to verification of another element. The subsequent block AND7a is selected as a new element to be verified, and the process proceeds to S4j-3.

Step S4j (FIG. 4) -3: It is checked whether or not the AND 7a, which is the currently verified element, has returned to the start point in the currently verified loop found in step S1.
The starting point is AND7a, and the element currently being verified is AND7a.
The process proceeds to “YES” for a, and proceeds to processing S5.

Process S5 (FIG. 1): The problem is displayed by clearly indicating the loop circuit location found in process S1. In this example, AND7a, NON-INVERTER7a, OR
7c is clearly indicated using a unique name given to each block in the circuit data, and may be oscillated on a real machine, and that there is no problem as long as the external terminal IN1 is fixed at 0. I do.

Process S6 (FIG. 1): Is there any other loop found in process S1? → No, go to “No”. (Processing end) As described above, the present invention is to supply a product of higher quality by detecting a problematic circuit configuration and specifying conditions for avoiding an oscillation state on an actual machine in advance. Can be done. In addition, it takes several to several tens times the normal development itself.
Can be completely cut.

Further, for each element, information on the path where the signal polarity is inverted between the input / output terminals and the input conditions necessary to determine the output value irrespective of other input values is stored in a library. By doing so, it is possible to determine whether or not an oscillation loop configuration is provided, without depending on the circuit configuration.

Further, the library itself is:
It can be easily created and updated based on the truth value information 11.

Next, a second embodiment to which the above-described verification method is applied will be described with reference to FIG. 8 showing a specific example of a circuit to be verified. Here, an example is shown in a case where the XOR is included in the loop portion.

The difference from the first embodiment is that the XO
When R / XNOR is included, the inversion and non-inversion of the signal polarity change depending on the input value from the other input terminal outside the loop, so that it is determined whether the inside of the loop is a positive feedback loop or a negative feedback loop. It cannot be done by ordinary means.

According to the present invention, when the input outside the loop has its logic determined by the clamp, INVERTE
Replacing with R / NON-INVERTER enables inversion and non-inversion verification. In addition, even if it cannot be replaced, the input outside the loop of another block is checked, and the possibility of a pseudo error is being searched for.

Process S1 (FIG. 1): Find a loop configuration (application of a known technique as described above).

The process proceeds to step S2. As an example, AND8a with INVERTER as shown in FIG. 8 → NON-INV
ERTER8b → 2-input XOR8c → INVERTER
Assume that only one loop with AND8a has been found.

Process S2 (FIG. 1): XOR / XNOR process. That is, the process proceeds to processing 2a.

Process S2a (FIG. 2): Is XOR / XNOR in the loop found in process S1? → XOR8c
Exists, the process proceeds to “Yes”, and proceeds to the next process S2b.

Process S2b (FIG. 2): Trace the input stage from the other input terminal B outside the loop of XOR 8c found in process S2a.

Process SRa (FIG. 5): The previous stage is checked to see where the input from outside the XOR8c loop comes from.
The input from the other input terminal B outside the loop of the XOR 8c is clamped LOW (8e) and fixed at the logical level "0". Move to the next processing SRb.

Process SRb (FIG. 5): Has the clamp (8e) been visited before? → "NO" because you have not visited
The process proceeds to the next process SRc.

Processing SRc (FIG. 5): XOR
Is it determined whether the input from outside the 8c loop is any of "0", "1", and "X"? → Since the input of the XOR 8c from the outside of the loop is the LOW clamp (8e), the process proceeds to “YES” to determine it to “0” and proceeds to the process S2c.

Process S2c (FIG. 2): Can XOR8c in the loop found in process S1 be replaced with INVERTER or the like? → From the result of the processing SRc, since the outside of the loop is fixed at LOW, the NON-
INVERTER can be replaced, and the next processing S
Move to 2d.

Process S2d (FIG. 2): XOR8c in the loop found in process S1 is set to NON-INVER
Replace with TER. Thereafter, the circuit shown in FIG. 9 which has been internally replaced is analyzed, and the process proceeds to the next process S2e.

Process S2e (FIG. 2): Does XOR / XNOR exist in the loop found in process S1? → Since there is no data, “verification continues” and the process proceeds to step S3.

Process S3 (FIG. 1): It is determined whether the loop found in process S1 is a positive feedback loop or a negative feedback loop, and the process proceeds to process S3a.

Process S3a (FIG. 3): In verifying each device, it is arbitrarily determined from which device to start verification. Suppose it is AND (9a in FIG. 9).

[0183] Subsequent steps until the element to be verified in the process S3 moves to the NON-INVERTER 9c are the same as those in the above-described first embodiment, and thus description thereof will be omitted.

Process S3d (FIG. 3) -2: Since the verification of the element currently being verified has been completed, the next element is selected as a new element to be verified. NON-
The process moves to INVERTER (original XOR8c) 9c and moves to the next process S3e-2.

Process S3e (FIG. 3) -2: The element to be verified goes around the loop found in process S1.
Check if you have returned to the starting point? → The starting point is 9a, 9
Since it is not c, the process proceeds to “NO” and proceeds to the process S3b-2.

Process S3b (FIG. 3) -3: Is the path to which the currently verified element is connected in the loop included in the “logical inversion path” defined in the dedicated library (FIG. 6)? Is determined. NON-INVE in FIG.
In the case of the RTER 9c, since there is no logical inversion path when the library is referred to, the process proceeds to “not pass”.

The subsequent operation is the same as that of the first embodiment described above, and the description is omitted here.

Next, a third example of applying the above-described verification method with reference to FIG. 10 showing a specific example of a circuit to be verified.
An example will be described. This example describes a case where XOR / XNOR cannot be degenerated as in the above-described second embodiment.

Here, the degeneracy means that redundant portions and configurations are
If it is possible to replace it with a more simplified one, it means to replace it. In this example, X
OR / XNOR is changed to BUFFER / INVE from the circuit configuration.
RTER.

When the degeneration cannot be performed, the inversion / non-inversion verification of the loop is not performed, and only the input outside the loop of another block is checked.

Process S1 (FIG. 1): As an example of finding a loop configuration (application of a known technique), an INV as shown in FIG.
AND10a with ERTER → NON-INVERTE
Assume that only one loop by R10b → two-input XOR10c → AND10a with INVERTER is found.

Processing S2 (FIG. 1): XOR / XNOR processing in the loop found in processing S1 is performed. Processing S
Move to 2a.

Process S2a (FIG. 2): Is there XOR / XNOR in the loop found in process S1? → Yes → Move to processing S2b.

Process S2b (FIG. 2): Traces the input stage of the other input terminal B outside the XOR / XNOR loop found in process S2a. That is, the process proceeds to processing SRa.

Process SRa (FIG. 5): The input from the preceding block outside the XOR / XNOR loop found in process S2a is viewed. The input value from outside the loop of the XOR 10c comes from the sequential circuit 10e, and it is unlikely that the value is fixed. Move to the next processing SRb.

Processing SRb (FIG. 5): Did the sequential circuit 10e come before? → Since it has not been visited, the process proceeds to “NO” and proceeds to the next process SRc.

Processing SRc (FIG. 5): Is the output of the sequential circuit 10e determined to be "0", "1" or "X"? → Go to “YES” to confirm X. It returns to processing S2c.

Process S2c (FIG. 2): Can XOR / XNOR found in process S2a be replaced with INVERTER or the like? → Since the input from outside the loop is not fixed, it cannot be replaced.

The subsequent operation is the same as in the first embodiment described above until the element to be verified moves to 10c in the processing S4, and the description is omitted here.

Process S4b (FIG. 4): The input value from the other input terminal outside the loop is traced, but XOR / X
Since the NOR has already been verified, it is checked whether the currently selected verification target element is not XOR / XNOR (because it has been traced by another method in the process S2). XO
Go to "YES" for R. That is, the input stage verification is skipped, and the process proceeds to step S4i.

Process S4i (FIG. 4): The next element of the element currently being verified is newly selected as a verification element.
Here, AND10a is selected. Move to processing S4j.

Process S4j (FIG. 4): Did the element selected in process S4i return to the starting point? → The starting point is AND10a and proceeds to "YES".

The subsequent operation is the same as that of the first embodiment, and the description is omitted here.

Next, a fourth example of applying the above-described verification method with reference to FIG. 11 showing a specific example of a circuit to be verified.
An example will be described. Here, an example in the case of a double loop configuration will be described.

If a smaller loop, for example, a negative feedback loop, exists in the found loops, the tracing does not end when tracing the input stage. A small loop can be verified separately, and if the value is determined within the small loop, it can be discovered by continuing tracing after the loop cut. The input value outside the loop in the part is uncertain (X) and the trace is continued by cutting the loop once.

Process S1 (FIG. 1): As an example of finding a loop configuration (this process is an application of a known technique), as an example, a NAND 11a → INVERTER11b → NAN as shown in FIG.
It is assumed that a loop of D11c → AND11d → NAND11a is found as one of many loops.

The subsequent operation is the same as that of the first embodiment until the verification element moves to the NAND 11c in the processing S4, and therefore the description is omitted here.

Process S4b (FIG. 4): In tracing the input value from the other input terminal outside the loop, it is checked whether the element currently being verified is not XOR / XNOR. As described above, the element currently being verified is the NAND
Since it is 11c and not an XOR, the process proceeds to "NO" and proceeds to the next process S4c.

Process S4c (FIG. 4): Does NAND11c, which is the element currently being verified, have an oscillation stop condition? → Referring to the library in FIG. 6, if the input A is fixed at 0, the oscillation can be stopped, so that the process proceeds to “YES” and proceeds to the next process S4d.

Processing S4d (FIG. 4): Element NAND 11c
The input value from the other input terminal A outside the loop is traced.

Process SRa (FIG. 5): The current device to be verified is the NAND 11c, but the immediately preceding device AND11d from outside the loop is newly selected as the current device to be verified, and the process proceeds to the next process SRb.

Processing SRb (FIG. 5): This element AND11
Have you visited d before? → "N
The process proceeds to O "and proceeds to the next process SRc.

Processing SRc (FIG. 5): This element AND11
It is determined whether the output value of d is determined to be “0” / “1” / “X” (undefined). However, since it is impossible to determine the output value only with this information, the process proceeds to “NO”, Move to the next process SRa (second time).

Process SRa (FIG. 5) -2: The element to be verified is AND11d, but the element N which is one immediately preceding stage
AND11c (from input A), NON-INVERT
ER11e (from input B). The two are selected as newly verified elements, and the next processing SRb-
Move to 2.

Process SRb (FIG. 5) -2: When it is confirmed whether these elements have visited before, since the AND 11c has visited before, the process proceeds to "YES", and the next process SRd
Move to -2.

Process SRd (FIG. 5) -2: NAND 11c
Since this is a loop of → AND11d → NAND11c, this path is cut. Input A of NAND 11c
Is determined to be indeterminate (X), and proceeds to the next process SRc-2.

Process SRc (FIG. 5) -2: Process SRd-2
Accordingly, the input A of the NAND 11c is determined to be indeterminate (X), and the process returns to step S4e.

Process S4e (FIG. 4): The process returns to the NAND 11c, which is the last device verified in the loop, and compares it with the oscillation stop condition. The oscillation stop condition obtained in step S4c is not satisfied. Move to the next step S4f.

Process S4f (FIG. 4): Since oscillation cannot be stopped with the input value from process S4e, the process proceeds to "NO" and proceeds to process S4i.

Process S4i (FIG. 4): The next stage, AND11d, is newly selected as the element to be verified, and the flow advances to process S4j.

Process 4S4j (FIG. 4): Is the element selected in process S4i the element selected as the starting point when entering process S4 for the first time? → Since the starting point is AND11a, "N
The process proceeds to O ", and proceeds to process S4b (second time).

Process S4b (FIG. 4) -2: Check if AND 11d selected in process S4i is not XOR / XNOR? → The process advances to "NO", and moves to the next process S4c-2.

Process S4c (FIG. 4) -2: The AND 11d selected in process S4i is stored in the dedicated library (FIG. 6).
Is there an oscillation stop condition? → If the input B is fixed at “0”, the oscillation stops and the process proceeds to “YES”, and the next processing S
Move on to 4d-2.

Process S4d (FIG. 4) -2: The process proceeds to a subroutine process SRa-3 for tracing an input from outside the loop of the AND 11d selected in the process S4i.

Process SRa (FIG. 5) -3: Check the preceding element from outside the loop of AND 11d. AND11
The input B of d comes from NON-INVERTER 11e. Move to the next processing SRb-3.

Process SRb (FIG. 5) -3: Process SRa-3
It is confirmed whether or not the NON-INVERTER 11e selected in step 1 has been visited before. → Since it has not been visited, the process proceeds to “NO” and proceeds to the next process SRc-3.

Process SRc (FIG. 5) -3: Process SRa-3
The output value from the element selected in is “0” / “1” /
It is determined which of “X” (undefined) is to be determined. N
It comes from the output of the ON-INVERTER 11e, and it is not known from this information alone that it is determined. Processing S
Return to Ra-4.

Process SRa (FIG. 5) -4: NON-INV
Trace one stage before the ERTER 11e. N
Input A of ON-INVERTER11e is LOW_CL
It comes from AMP (clamped LOW) 11g. Move to the next processing SRb-4.

Process SRb (FIG. 5) -4: Process SRa-4
Have you visited the element selected in previous? → Since it has not been visited, the process proceeds to “NO” and proceeds to the next process SRc-4.

Process SRc (FIG. 5) -4: Process SRa-4
The output value of the element selected in the step is "0" / "1" / "X"
(Indeterminate) It is determined whether to determine any of them. Processing SR
LOW_CLAMP11g discovered in a-4 is NON
-Connected to input terminal B of AND 11d via INVERTER 11e. As a result, only "0" is output from the AND 11d.

The subsequent operation is the same as that of the first embodiment, and the description is omitted here.

[0232]

As described above, the method for detecting an oscillation component in a loop circuit according to the present invention detects a prohibited negative feedback loop in a loop circuit by positive feedback and negative feedback in an internal circuit at a logic verification stage. As a loop detecting means, it is necessary to determine a path where the signal polarity is inverted between at least one input terminal and an output terminal of each of the elements constituting the internal circuit, and to determine an output value irrespective of an input value of the other input terminal. Information on the input conditions is created and updated based on the predetermined truth value information to make a library in the storage means of the logic verification device, and whether the internal circuit has an oscillation loop configuration while referring to the library. Is determined, and the result of the determination is displayed on an external display means, so that a problematic circuit configuration can be detected or generated on the actual machine. State can be explicitly advance the conditions of the order to avoid, it is possible to supply a better quality of products.

Further, it is possible to completely cut the TAT of analysis, discovery, and recovery at the time of failure occurrence, which usually takes several to several tens times the development itself.

Furthermore, for each element, information on the path that is inverted between the input and output and the input conditions necessary to determine the output irrespective of other input values are stored in a library. It is possible to easily determine whether or not the circuit has an oscillation loop configuration without depending on the circuit configuration.

Further, the library itself is:
It can be easily created and updated based on the truth value information.

[Brief description of the drawings]

FIG. 1 is an overall flowchart illustrating a method for detecting an oscillation configuration portion in a loop circuit according to an embodiment of the present invention.

FIG. 2 is a detailed flowchart of a process S2.

FIG. 3 is a detailed flowchart of a process S3.

FIG. 4 is a detailed flowchart of a process S4.

FIG. 5 is a detailed flowchart of processes S2b and S4d.

FIG. 6 is a diagram illustrating an example of a library.

FIG. 7 is a diagram showing a circuit example of a first embodiment to which the verification method of the present invention is applied.

FIG. 8 is a diagram showing a circuit example of a second embodiment to which the verification method of the present invention is applied.

FIG. 9 shows that XOR8c in FIG.
It is the figure replaced with TER9c.

FIG. 10 is a diagram showing a circuit example of a third embodiment to which the verification method of the present invention is applied.

FIG. 11 is a diagram showing a circuit example of a fourth embodiment to which the verification method of the present invention is applied.

FIG. 12 is a diagram showing a circuit example for explanation of a conventional verification method.

FIG. 13 is a diagram showing a waveform diagram of a simulation result.

FIG. 14 is a diagram showing input / output waveforms of a NAND on an actual device.

[Explanation of symbols]

11 Truth information 12 Library 7a, 8a, 9a, 10a A with INVERTER
ND 7b, 8b, 9c, 10b, 11e, 12b NON
-INVERTER 7c OR 8c, 10c XOR 10e Sequential circuit 11a, 11c, 12a NAND 11b INVERTER 11d AND 11g LOW_CLAMP 12c HIGH_CLAMP

Claims (14)

[Claims] At least one of elements constituting an internal circuit of an internal circuit of a semiconductor device, as a loop detecting means for detecting a forbidden negative feedback loop in a logic verification stage among positive and negative feedback loop circuits. Based on predetermined truth value information, a path in which the signal polarity is inverted between one input terminal and the output terminal and information on input conditions necessary to determine an output value regardless of the input value of the other input terminal are determined. A library is created in the storage means of the logic verification device by creating and updating, and it is determined whether or not the configuration of the internal circuit has an oscillation loop configuration while referring to the library, and the determination result is displayed on an external display. A method for detecting an oscillation configuration portion in a loop circuit, characterized by displaying on a means. 2. The negative feedback loop having one input terminal of each of an exclusive-OR and an exclusive-NOR as a path, wherein the logic level of the other input terminal outside the negative feedback loop is clamped. 2. The method according to claim 1, wherein when the determination is made, the exclusive OR or exclusive NOR is replaced with an inverter or a non-inverter based on the truth value information to perform verification. 3. The negative feedback loop having a path through one input terminal of each of an exclusive OR and an exclusive NOR, wherein a logic level of the other input terminal outside the negative feedback loop is a specific level. In the case of uncertainty due to an element or a specific functional block, inversion or non-inversion verification of the signal polarity in the negative feedback loop is not performed, and only verification of another block in the path of the other input terminal outside the negative feedback loop is performed. 2. A method for detecting an oscillation component in a loop circuit according to claim 1. 4. If a small negative feedback loop further exists in the detected negative feedback loop, the small negative feedback loop is verified in advance, and the oscillation stop condition of the library is set in the small negative feedback loop. If the value to be satisfied is determined, the trace is continued after the loop is cut off, and the input value of the other input terminal outside the small negative feedback loop is determined to be indefinite, and the trace is continued by cutting off the negative feedback loop. Item 2. A method for detecting an oscillation component in a loop circuit according to item 1. 5. The logic inversion path stored in the library defines a path in which logic is inverted between input and output terminals in a connection path in the negative feedback loop, and the oscillation stop condition is: 2. The method according to claim 1, wherein information indicating which value of a signal input value from the other input terminal outside the negative feedback loop is fixed to prevent oscillation is defined. 6. A loop detection process of tracing an output stage starting from all devices to be verified while referring to the library, and detecting the device as the loop when returning to a device already visited; When an exclusive OR or exclusive NOR is detected in the loop, it is verified whether an input signal level from the other input terminal outside the loop is fixed, and an inverter or an inverter based on the truth value information is checked. Determine whether or not it can be replaced by a non-inverter, and if it is possible, perform processing of exclusive OR or exclusive NOR to replace, and compare each element in the loop with the logical inversion path in the library. The number of inversion paths existing in the entire loop is calculated, and if the result is odd, it is determined as a negative feedback loop, and if the result is zero or even, it is determined as a positive feedback loop. In the case of the negative feedback loop and when the inverter is not replaced with the inverter or the non-inverter, each element in the negative feedback loop is controlled by an input signal from the other input terminal outside the loop. Out-of-loop input check processing for sequentially verifying whether or not the output logic is fixed retroactively to the element at the preceding stage of the element, and when it is not confirmed that there is no problem in the out-of-loop input check processing, A problem display process for ending the verification of the loop by explicitly indicating information on which element has a loop configuration, and a loop detection confirmation for confirming whether all the loops detected in the loop detection process have been detected 2. The method according to claim 1, further comprising the steps of: 7. A specific element or a specific functional block which determines that output logic is not fixed in the out-of-loop input check processing and does not trace back to the preceding element is a sequential circuit or an input / output circuit. 7. The method according to claim 6, wherein all terminal connections of the return, adder and parity generators and terminal connections of an enable portion of the latch, multiplexer and decoder are provided. 8. The method according to claim 6, wherein in the out-of-loop input check processing, it is arbitrarily selected whether or not to execute a trace going back to the preceding element. 9. The loop circuit according to claim 6, wherein in the input check processing outside the loop, the number of stages of the preceding trace is arbitrarily specified, and if the value is not determined or undetermined within the number of stages, the loop circuit is treated as indeterminate. Method of detecting the oscillation configuration part in. 10. The exclusive OR and exclusive OR processing includes determining whether an exclusive OR or exclusive NOT is included in a logical loop found in the loop detection processing. Determining whether there is a first exclusive OR or exclusive OR, and comparing the exclusive OR or the exclusive NOR detected in the preceding process, which has not been verified yet, with one Input stage tracing process for selecting whether an input value from the other input terminal outside the loop for the element is fixed, and the exclusive OR obtained by performing a previous stage trace in a previous stage process Alternatively, it is determined whether or not the exclusive NOR can be replaced with an inverter or a non-inverter. If it is possible, the process proceeds to the next step. A replacement determination process, a replacement execution process that replaces the exclusive OR or the exclusive NOR determined by the input stage process in response to the determination result of the replacement determination process with an inverter or a non-inverter, If there is another exclusive OR or exclusive NOR found in the presence / absence processing of the exclusive OR or exclusive NOT, the input stage tracing process is repeated again for the exclusive OR or the exclusive NOR, and the detected 2. The detection of an oscillation component in a loop circuit according to claim 1, further comprising a second exclusive OR or an exclusive negative OR presence / absence determination process for determining whether to continue verification and moving to the positive / negative feedback process when the error is exhausted. Method. 11. If the input value from the other input terminal outside the loop, which is input to the exclusive OR or the exclusive NOR verified in the input stage tracing processing, is a logic level “1” If the inverter is "0", it is determined that it can be replaced with a non-inverter, and the process proceeds to the next process.
11. The method according to claim 10, wherein it is determined that replacement is impossible and the process proceeds to the input check processing outside the loop. 12. The positive / negative feedback processing may include an element detected in the loop verification processing, or an arbitrary part in a loop partially converted in the processing of the exclusive logical sum or the exclusive negative logical sum. A starting point determination process of selecting an element as an element to be verified, and whether or not a signal polarity is inverted between input / output terminals in the loop of the element currently being verified is determined by a logical inversion path defined in the library. As a result of the inversion path passage determination processing for determining whether the connection is within the loop and the verification of the inversion path passage determination processing, the signal polarity between the input / output terminals of the element being verified in the loop is inverted. In this case, the number of inversions is increased by one, and the number of inversions + 1 is cleared when all of the positive / negative feedback processing is completed, and the next-stage element selection processing for newly selecting a subsequent element as a verification target element; It is determined whether or not the element newly selected in the next-stage element selection processing is the same as the element selected in the start point determination processing. If they are the same, the process proceeds to the next processing. When the inversion number stored in the inversion number + 1 processing is an even number as a result from the inversion path passage determination processing to the start point return determination processing, it is determined that the feedback is positive, and the problem display is performed. 2. The method according to claim 1, further comprising an inversion result determination process that proceeds to a process, and in the case of an odd number, proceeds to the out-of-loop input check process. 13. The start point for selecting an arbitrary element in the loop in which the exclusive OR or the exclusive NOR is replaced with another element as an element to be verified first. Determination processing, and processing for determining whether the element currently being verified is the exclusive OR or the exclusive NOR, and proceeding to a subsequent specified processing, respectively, for determining the exclusive OR or exclusive NOR And whether or not the element currently being verified has the oscillation stop condition in the library.If the oscillation stop condition does not exist, the process proceeds to the subsequent element selection process, and if the oscillation stop condition exists. Is a process for confirming the presence or absence of an oscillation stop condition that proceeds to the next input stage trace process, and when the oscillation stop condition is satisfied, the other input terminal outside the loop of the element currently being verified is An input stage tracing process for verifying whether an input value of the input stage is fixed, an input value from the other input terminal outside the loop for a device under verification obtained by the input stage tracing process, and the oscillation Oscillation stop condition comparison processing for comparing with the stop condition, and if the determination result obtained in the oscillation stop condition comparison processing satisfies the oscillation stop condition, the process proceeds to the next stage; otherwise, the process proceeds. The process of checking for the presence or absence of an oscillation loop that moves to the next element selection process, which is the process, and the input value from the input terminal outside the loop determined to satisfy the oscillation condition in the process of checking the presence or absence of the oscillation loop is fixed by a clamp. In this case, the verification of the loop currently being verified is completed, and if the oscillation is stopped due to the use condition of the external terminal, the processing for confirming the presence or absence of the condition proceeds to the next stage processing, and the processing for confirming the presence or absence of the condition If there is a condition for stopping the oscillation, the condition is explicitly displayed to indicate the condition on an external display, and it cannot be confirmed from the element currently being verified that the oscillation can be stopped with the input value of the other input terminal outside the loop. In the case and in the case of conditional stop, a next-stage element selection process of selecting a subsequent element of the element currently being verified in the loop as a new verification target element, and the element selected as the verification target element is It is determined whether or not it is the same as the one selected in the start point determination processing. If it is the same, the processing proceeds to the external display processing as a conditional passage or a problem, and if not, the exclusive OR or exclusive NOR is determined. And a verification end confirmation process returning to the determination process of (1).
A method for detecting an oscillation configuration portion in the loop circuit described above. 14. The input stage tracing process newly selects an immediately preceding device connected to an input terminal outside the loop of the device verified in the immediately preceding process as a device to be verified. A first element selection unit and a verification that determines whether the verification target element selected by the first element selection unit is a previously visited element, and branches into an already visited element and a first visited element, respectively. The element determination process, an uncertain value setting process in which, if it is determined that the device has already been visited in the verification device determination process, the route is excluded from the verification target, and the value from the route is not determined. It is determined whether the input value from the other input terminal outside the loop for the element is determined to be “0”, “1”, or “indeterminate”. Return “0” 14. The method according to claim 10 or 13, further comprising "" 1 """uncertain" determination processing.