JP2002164874A - Time/date correction system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct transmission of more accurate time/date table, by modifying a delay time of transmission and a delay time caused by processing at a transmission side system and a reception side system. SOLUTION: A time correction circuit 7 inputs TS(transport stream) signals 24 for MPEG(moving picture experts group) multiplexing and outputs time modification TS signals 30 for which time correction is conducted. A current time read circuit 1 reads reference time data 23 and outputs time/date information 25. An addition value set circuit 2 outputs transmission delay information 26 to which value of transmission delay time is set in the unit of second. A TOT(time offset table) value addition circuit 3 adds transmission delay information 26 to time/date information 25 and outputs TOT information 27. A second phase set circuit 4 outputs second phase data 28 to which value of transmission delay time less than a second is set. A timing adjustment circuit 5 outputs insert timing signals 29 to which correction of transmission delay time less than a second is conducted by adjusting insert timing of TOT information 27. A multiplex circuit 6 outputs the multiplexed time modification TS signals 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a time / date correction system, and more particularly to a time / date correction system capable of transmitting a more accurate time / date table in an MPEG multiplexer.

[0002]

2. Description of the Related Art In general, in BS digital TV broadcasting, ARIB STD, a standard specification of the Radio Industry Association of Japan, is used.
-Time table (TDT: Ti
mean Date Table) or a time date offset table (TOT: Time Offset Ta) including offset time information when daylight saving time is implemented.
ble), JST (Japan Standard)
d Time) Time and date information are transmitted.

The JST time and date information is used for displaying time and date information in a digital TV receiver, for example. In digital TV broadcasting, such as the BS digital broadcasting system in Japan and the terrestrial digital broadcasting system which is being researched and developed for practical use, unlike the current analog TV broadcasting, the transmitting system uses video, audio and data. Is transmitted through processing such as band compression, multiplexing and modulation.

[0004] The receiving-side system reproduces a broadcast program by performing processing reverse to that of the transmitting side, that is, demodulation, demultiplexing, and band expansion. Due to these processes, the transmission delay from the transmission side to the reception side increases, and it is necessary to expect a transmission delay time of about 1 to 2 seconds.

An example of such a technique is disclosed in
A “relay broadcasting device” described in JP-A-209170 is known.

In this publication, a digital broadcast signal including time information is demodulated, the demodulated digital broadcast signal is modulated by a predetermined carrier, and retransmitted. There is described a technique for transmitting a more accurate time / date table in a relay broadcast device by having a time correction unit that corrects an error corresponding to a delay time generated in an internal signal processing process.

[0007]

In the conventional time / date correction system described above, when multiplex transmission of a plurality of transport streams is performed, the transmission delay time including the system processing time from the transmission side to the reception side increases. Since the transmission delay time of about 1 to 2 seconds and the processing time of the transmission side system and the reception side system must be expected,
There is a disadvantage that an accurate time / date table cannot be transmitted.

An object of the present invention is to provide a time / date correction system capable of transmitting a more accurate time / date table by correcting a transmission delay time and a delay time associated with processing of a transmission side system and a reception side system. Is to do.

[0009]

A time / date correction system according to the present invention comprises: a time / date table generating means for generating a time / date table including a time / date offset value at a second change point of a reference time; And a timing adjustment unit that adjusts the insertion timing of a time / date table including the time / date offset value that corrects for sub-second correction. And

[0010] MPEG (Moving Picture)
A transport signal for multiplexing (Experts Group) (hereinafter, TS [Transport Street]
am) signal, and a time correction circuit for correcting the time and date of the TS signal and outputting a time corrected TS signal in which date information is multiplexed with Japan Standard Time based on time and date offset information. An output terminal for outputting the time-corrected TS signal; a modulator for modulating the time-corrected TS signal with a predetermined carrier to output a modulation signal; a transmission device for transmitting the modulation signal; and a demodulation and decoding of the modulation signal And a receiver that performs the operation.

[0011] MPEG (Moving Picture)
A transport signal for multiplexing (Experts Group) (hereinafter, TS [Transport Street]
am) signal, and a time correction circuit for correcting the time and date of the TS signal and outputting a time corrected TS signal in which date information is multiplexed with Japan Standard Time based on time and date offset information. An output terminal for outputting the time-corrected TS signal; a modulator for modulating the time-corrected TS signal with a predetermined carrier to output a modulation signal; a transmission device for transmitting the modulation signal; and a demodulation and decoding of the modulation signal A time correction circuit that reads reference time data supplied from a data input terminal and outputs time and date information; and a value in seconds of a transmission delay time is set in advance. An additional value setting circuit for outputting the transmission delay information; and adding the transmission delay information to the time / date information to obtain a TOT (Time Offset T).
atable) a TOT value addition circuit for generating and outputting information;
A second-phase setting circuit for outputting second-phase data in which a value of a second or less of a transmission delay time is set in advance; an insertion that corrects a transmission delay time of a second or less by adjusting the insertion timing of the TOT information; A timing adjustment circuit that outputs a timing signal; and a multiplexing circuit that inserts the TOT information into the TS signal using the insertion timing signal and outputs a multiplexed time correction TS signal. .

[0012] MPEG (Moving Picture)
A transport signal for multiplexing (Experts Group) (hereinafter, TS [Transport Street]
am) signal, and a time correction circuit for correcting the time and date of the TS signal and outputting a time corrected TS signal in which date information is multiplexed with Japan Standard Time based on time and date offset information. An output terminal for outputting the time-corrected TS signal; a modulator for modulating the time-corrected TS signal with a predetermined carrier to output a modulation signal; a transmission device for transmitting the modulation signal; and a demodulation and decoding of the modulation signal A current time generating circuit that outputs time and date information indicating a current time;
An addition value setting circuit for outputting transmission delay information in which the value of the transmission delay time in seconds is set in advance; and adding the transmission delay information to the time / date information to obtain a TOT (Time Offset).
t Table) a TOT value adding circuit for generating and outputting information; a second phase setting circuit for outputting second phase data in which a value equal to or less than a second of the transmission delay time is preset;
A timing adjustment circuit for adjusting the insertion timing of information to output an insertion timing signal corrected for a transmission delay time of less than a second; and inserting the TOT information into the TS signal using the insertion timing signal, and multiplexing. And a multiplexing circuit for outputting the time-corrected TS signal.

[0013] The present time generation circuit is characterized in that it is an atomic clock using a rubidium oscillator.

The current time generation circuit is a clock device synchronized with a high precision standard radio wave.

The current time generation circuit is provided with a GPS (Glo
bal Positioning System).

Also, MPEG (Moving Pict)
ure Experts Group) multiplexing transport signal (hereinafter referred to as TS [Transport S
stream) signal, and a time correction T which corrects the time and date of the TS signal and multiplexes the Japanese standard time and date information based on the time and date offset information.
A time correction circuit for outputting an S signal; an output terminal for outputting the time-corrected TS signal; a modulator for modulating the time-corrected TS signal with a predetermined carrier to output a modulation signal; and a transmission for transmitting the modulation signal Device, comprising a receiver for demodulating and decoding the modulated signal, the time correction circuit,
A TOT information reading / deleting circuit for reading time / date information from the input TS signal and outputting read TOT information; an addition value setting circuit for outputting transmission delay information in which a value of a transmission delay time in seconds is set in advance; A TOT value adding circuit for adding the transmission delay information to the read TOT information to generate and output corrected TOT information; and a second phase setting for outputting second phase data in which a value of a second or less of the transmission delay time is preset. A timing adjustment circuit that adjusts the insertion timing of the corrected TOT information to output an insertion timing signal corrected for a transmission delay time of less than a second;
A multiplexing circuit that inserts the corrected TOT information into the TS signal output by the TOT information reading and deleting circuit using the insertion timing signal and outputs a multiplexed time-corrected TS signal.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the time and date correction system of the present invention.

The present embodiment shown in FIG.
oving Picture Experts Gro
up) TS (Transport Street) for multiplexing
am) a TSin terminal 21 for inputting the signal 24, a time correction circuit 7 for correcting the time and date of the TS signal 24 and outputting a time-corrected TS signal 30, and outputting the time-corrected time-corrected TS signal 30 A TSout terminal 22;
A modulator 8 that modulates a time-corrected TS signal 30 in which JST time and date information based on TOT information 27 are multiplexed by a predetermined carrier and outputs a modulated signal 31, and a satellite that transmits the modulated signal 31 and outputs the modulated signal 32 as a modulated signal 32 It comprises a transmission device 9 such as a communication system and a receiver 10 for demodulating and decoding the modulated signal 32.

The time correction circuit 7 reads the reference time data 23 supplied from an external reference clock device (not shown) from the BCDin terminal 20 and outputs time / date information 25; An addition value setting circuit 2 that outputs transmission delay information 26 in which a value of delay time in seconds is set in advance;
6, a TOT value adding circuit 3 for generating and outputting TOT information 27, and a second phase setting circuit 4 for outputting second phase data 28 in which a value equal to or less than a second of the transmission delay time is preset.
A timing adjustment circuit 5 for adjusting the insertion timing of the TOT information 27 to output an insertion timing signal 29 having a transmission delay time of less than a second corrected, and a TS signal 2
4 includes a multiplexing circuit 6 that inserts TOT information 27 using an insertion timing signal 29 and outputs a multiplexed time correction TS signal 30.

Here, TOT (Time Offset)
Table) indicates a time / date offset table.

Also, MPEG (Moving Pict)
ure Experts Group) indicates a standardized color moving picture coding method.

Next, the operation will be described in detail with reference to FIG.

In the time / date table correction in the MPEG multiplexing, the current / time reading circuit 1 reads time / date information 25 from reference time data 23 supplied from an external reference clock device (not shown).
A TOT value is generated by the TOT value adding circuit 3 from the
The information 27 is output. The TOT information 27 is set with the accuracy of the unit of second, and the time and date table including the TOT value changes the time of the second in the count-up direction.

The addition value setting circuit 2 includes a modulator 8,
A value in seconds of a transmission delay time generated in the transmission device 9 and the receiver 10 such as a satellite communication system is set in advance,
The preset transmission delay time in seconds is output to the TOT value addition circuit 3 as transmission delay information 26,
Is added to the value.

On the other hand, the second phase setting circuit 4 has a transmission delay time generated in the modulator 8, the transmission device 9 and the receiver 10 of a value equal to or less than a second (for example, 0.1 second, 0.01 second, 0.00 second).
1 second) is set in advance, and the timing adjustment circuit 5
By adjusting the insertion timing of the TOT information 27 with the second phase data 28 output from the second phase setting circuit 4, the transmission delay time of less than a second is corrected. Multiplex circuit 6
Is an insertion timing signal 29 for correcting the transmission delay time of sub-second by the timing adjustment circuit 5 from the TOT information 27 in which the transmission delay time supplied from the TOT value addition circuit 3 is corrected in units of seconds, and a TSin terminal. 21 is multiplexed into the TS signal 24 input from the
The signal 30 is output.

Here, assuming that a transmission delay time generated in the modulator 8, the transmission device 9, and the receiver 10 is Tdelay,
The following relationship holds.

[0028]

(Equation 1)

Note that Tsec is a correction in units of seconds corrected by the TOT value addition circuit 3, and Tphase is a correction of time less than or equal to seconds corrected by the timing adjustment circuit 5.

The rewriting of the value of the TOT information 27 by the time correction circuit 7 and the adjustment of the insertion timing of the time / date table including the TOT information 27 perform the correction processing with high accuracy.

FIG. 2 is a block diagram showing a time and date correction system according to a second embodiment of the present invention.

In FIG. 2, components corresponding to those shown in FIG. 1 are denoted by the same reference numerals or symbols, and description thereof will be omitted.

The time correction circuit 17 shown in FIG. 2 is obtained by replacing the current time reading circuit 1 with the current time generation circuit 11 in the embodiment shown in FIG. The current time generation circuit 11 is, for example, an atomic clock device provided with a high-precision reference signal such as a rubidium oscillator or a cesium oscillator, a clock device synchronized with a high-accuracy standard radio wave, or a GPS (Globa).
1 Positioning System).

In the present embodiment, since the time / date information 35 indicating the correct current time is output by the current time generation circuit 11, an external reference clock device (not shown) and a BC
The Din terminal 20 becomes unnecessary.

Other operations are the same as those in FIG.
Here, the description is omitted.

FIG. 3 is a block diagram showing a time and date correction system according to a third embodiment of the present invention.

In FIG. 3, components corresponding to those shown in FIG. 1 are denoted by the same reference numerals or symbols, and description thereof is omitted.

The time correction circuit 37 shown in FIG. 3 is different from the embodiment shown in FIG.
The terminal 20 is deleted, and a TOT information reading and deleting circuit 12 is provided. In the third embodiment, the read TOT information 36 read by the TOT information reading / deleting circuit 12 is output to the TOT value adding circuit 3, and the TOT value adding circuit 3 corrects the transmission delay time in seconds. The output timing correction circuit 38 corrects the transmission delay time of less than second by the timing adjustment circuit 5 and outputs an insertion timing signal 29 to the multiplexing circuit 6. With this insertion timing signal 29, the corrected TO corrected to the time slot location different from the time slot location originally set in the TS signal 35 output from the TOT information reading / deleting circuit 12
The T information 38 is set, and the multiplexing circuit 6 outputs the time correction TS signal 39.

Other operations are the same as those in FIG.
Here, the description is omitted.

As described above, although the configurations of FIGS. 1 to 3 are different, a more accurate time / date table can be transmitted by the time correction circuit.

That is, a time / date table including a time / date offset value at a change point of the second of the reference time is generated, the transmission delay time is corrected in seconds by correcting the time / date offset value, and the correction of the second or less is performed. A time / date correction system that adjusts the insertion timing of a time / date table including the time / date offset value to be performed.

The detailed contents of the TOT table are described in A
Although specified by RIB STD-B10, the main bit configuration is as follows. table_id: 8-bit section_syntax_indicator
: 1 bit reserved_future_use: 1 bit reserved: 2 bits section_length: 12 bits JST_time: 40 bits reserved: 2 bits descriptors_loop_length:
12 bits <for (I = 0; I <N; I ++) @ desrip
tor ()}> CRC_32: 32 bits Further details of the TDT are described in ARIB STD-B10
The main bit configuration contents are as follows. table_id: 8-bit section_syntax_indicator
: 1 bit reserved_future_use: 1 bit reserved: 2 bits section_length: 12 bits JST_time: 40 bits According to these information, "00/12/01 10: 3"
5:45 "is transmitted.

According to the specification of ARIB STD-B10, the TOT is a TDT that gives information on the current time and date and offset time information when daylight saving time is in effect.
Includes all items included in.

[0044]

As described above, the time and date correction system according to the present invention provides the M / M of a plurality of transport streams.
Since the error of the transmission delay time including the processing time of the digital broadcast transmission / reception system can be corrected with respect to the PEG multiplex transmission, there is an effect that a more accurate time / date table can be transmitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a time and date correction system of the present invention.

FIG. 2 is a block diagram showing a time and date correction system according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a time and date correction system according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Current time reading circuit 2 Addition value setting circuit 3 TOT value addition circuit 4 Second phase setting circuit 5 Timing adjustment circuit 6 Multiplexing circuit 7 Time correction circuit 8 Modulator 9 Transmission device 10 Receiver 11 Current time generation circuit 12 TOT information reading and deletion Circuit 17 Time correction circuit 20 BCDin terminal 21 TSin terminal 22 TSout terminal 23 Reference time data 24 TS signal 25 Time date information 26 Transmission delay information 27 TOT information 28 second phase data 29 Insertion timing signal 30 Time correction TS signal 31, 32 Modulation signal 35 TS signal 36 Read TOT information 37 Time correction circuit 38 Corrected TOT information 39 Time corrected TS signal

Claims (8)

[Claims] 1. A time / date table generating means for generating a time / date table including a time / date offset value at a second change point of a reference time, and correcting the transmission delay time in seconds by correcting the time / date offset value. Time adjustment means;
And a timing adjusting means for adjusting the insertion timing of a time / date table including the time / date offset value for performing correction of seconds or less. 2. An MPEG (Moving Picture)
e ExpertsGroup) transport signal for multiplexing (hereinafter, TS [Transport Street
am) signal, and a time correction circuit for correcting the time and date of the TS signal and outputting a time corrected TS signal in which date information is multiplexed with Japan Standard Time based on time and date offset information. An output terminal for outputting the time-corrected TS signal, a modulator for modulating the time-corrected TS signal with a predetermined carrier and outputting a modulated signal, a transmission device for transmitting the modulated signal, and demodulating and decoding the modulated signal A date and time correction system, comprising: 3. An MPEG (Moving Picture)
e ExpertsGroup) transport signal for multiplexing (hereinafter, TS [Transport Street
am) signal, and a time correction circuit for correcting the time and date of the TS signal and outputting a time corrected TS signal in which date information is multiplexed with Japan Standard Time based on time and date offset information. An output terminal for outputting the time-corrected TS signal; a modulator for modulating the time-corrected TS signal with a predetermined carrier to output a modulation signal; a transmission device for transmitting the modulation signal; and a demodulation and decoding of the modulation signal A current time reading circuit that reads reference time data supplied from a data input terminal and outputs time / date information;
An addition value setting circuit for outputting transmission delay information in which the value of the transmission delay time in seconds is set in advance; and adding the transmission delay information to the time / date information to obtain a TOT (Time Offset).
t Table) a TOT value addition circuit for generating and outputting information; a second phase setting circuit for outputting second phase data in which a value equal to or less than a second of the transmission delay time is preset;
A timing adjustment circuit for adjusting the insertion timing of information to output an insertion timing signal corrected for a transmission delay time of less than a second; and inserting the TOT information into the TS signal using the insertion timing signal and multiplexing. And a multiplexing circuit for outputting a time-corrected TS signal. 4. An MPEG (Moving Picture)
e ExpertsGroup) transport signal for multiplexing (hereinafter, TS [Transport Street
am) signal, and a time correction circuit for correcting the time and date of the TS signal and outputting a time corrected TS signal in which date information is multiplexed with Japan Standard Time based on time and date offset information. An output terminal for outputting the time-corrected TS signal; a modulator for modulating the time-corrected TS signal with a predetermined carrier to output a modulation signal; a transmission device for transmitting the modulation signal; and a demodulation and decoding of the modulation signal A time correction circuit, a current time generation circuit that outputs time and date information indicating a current time; and an addition value that outputs transmission delay information in which a value of a transmission delay time in seconds is set in advance. A setting circuit; adding the transmission delay information to the time / date information, and TOT (Time Of
fset Table) A TOT value addition circuit that generates and outputs information; a second phase setting circuit that outputs second phase data in which a value equal to or less than a second of the transmission delay time is set in advance; and adjusts the insertion timing of the TOT information. A timing adjustment circuit for outputting an insertion timing signal corrected for a transmission delay time equal to or less than a second;
A multiplexing circuit for inserting T information by the insertion timing signal and outputting a multiplexed time correction TS signal. 5. The time and date correction system according to claim 4, wherein the current time generation circuit is an atomic clock using a rubidium oscillator. 6. The time and date correction system according to claim 4, wherein the current time generation circuit is a clock device synchronized with a high-precision standard radio wave. 7. The current time generation circuit includes a GPS (Gl)
5. The time / date correction system according to claim 4, wherein the time / date correction system is a clock device synchronized with an Oval Positioning System. 8. An MPEG (Moving Picture)
e ExpertsGroup) transport signal for multiplexing (hereinafter, TS [Transport Street
am) signal, and a time correction circuit for correcting the time and date of the TS signal and outputting a time corrected TS signal in which date information is multiplexed with Japan Standard Time based on time and date offset information. An output terminal for outputting the time-corrected TS signal; a modulator for modulating the time-corrected TS signal with a predetermined carrier to output a modulation signal; a transmission device for transmitting the modulation signal; and a demodulation and decoding of the modulation signal A time correction circuit, which reads time and date information from the input TS signal and outputs read TOT information; and a TOT information reading and deleting circuit that outputs a read TOT information; Value setting circuit for outputting the transmission delay information, and adding the transmission delay information to the read TOT information to generate and output corrected TOT information. A second phase setting circuit for outputting second phase data in which a value of a second or less of a transmission delay time is preset, and a correction of a transmission delay time of a second or less by adjusting the insertion timing of the modified TOT information. A timing adjustment circuit that outputs an insertion timing signal after performing the above operation;
A multiplexing circuit that inserts the modified TOT information into the TS signal output by the TOT information reading and deleting circuit based on the insertion timing signal and outputs a multiplexed time-corrected TS signal. Date correction system.