JP2002164787A - D/a output port - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D/A output port which is used both as an output terminal for a digital value and as an output terminal of an analog value. SOLUTION: This D/A output port is provided with a port register for holding a first digital value, an input-output mode setting register for setting the input- output mode of a port, a digital-to-analog converter for receiving the supplies of a high potential power source and a low potential power source and converting a second digital value into an analog value, the output terminal of the digital-to-analog converter and the conversion value setting register of the digital-to-analog converter, transfers a value written in the port register to all bits of the conversion value setting register with the input-output mode setting register as an output mode and outputs the first digital value to the output terminal with an output of the digital-to-analog converter as low potential in accordance with the output value of the conversion value setting register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A output port, and more particularly, to a D / A converter corresponding to a function of a D / A converter output terminal of a microcomputer and a digital port.
Regarding the A output port.

[0002]

2. Description of the Related Art Conventionally, an output terminal of a digital / analog converter (hereinafter, referred to as a D / A converter), a digital port, and an analog / digital converter (hereinafter, referred to as A / D converter).
/ D converter) is well known, and it is well known that it is important to use these input / output terminals effectively.

This D / A converter output terminal (hereinafter referred to as A
The digital port will be described with reference to FIG. The ANO terminal 11 is an analog output terminal.

Referring to FIG. 2, when this D / A converter is connected to a digital port, for example, by a wired connection, a relatively stable analog / digital converter is used to supply power to the D / A converter output terminal protection buffer 20. A digital high-potential power supply AVDD and an analog / digital low-potential power supply AVSS are used (see FIG. 3). D /
Since the A-converter output terminal and the digital port terminal are at the same potential, as shown in FIG.
It is common to use VDD and analog / digital low potential power supplies.

[0005] On the other hand, usually, a register area is allocated to a port with regularity, and depending on a program, port operation can be performed using an operation instruction by using the above-described regularity.

That is, a user uses a D / A converter as a port in a pseudo manner,
LL “0” and ALL “1” are written, and V is output from the output terminal.
It is also possible to output a DD level or a GND level.

[0007]

However, the ANO
The terminal 11 is an analog output terminal, and it is difficult to use the terminal 11 as a digital port. The reason will be described below.

When the digital port is used as an output in the above configuration, the output noise of the digital port propagates to the analog / digital high-potential power supply AVDD and the analog / digital low-potential power supply AVSS, and the A / D
There is a problem that the accuracy of the converter is deteriorated.

[0009] In addition, as shown in FIG. 8, a method in which a user uses a D / A converter as a port in a simulated manner is that, as shown in FIG. The position also requires an operation different from the register operation of the digital port, and in particular, there is a problem in that the user is forced to convert the operation difference.

[0010]

According to the present invention, a D / A output port comprises: a port register for holding a first digital value;
An input / output mode setting register for setting an input / output mode of the port, and receiving supply of a high potential power supply and a low potential power supply,
A digital / digital converter for converting a second digital value to an analog value
An analog converter; an output terminal of the digital / analog converter; and a conversion value setting register of the digital / analog converter. The input / output mode setting register is set to an output mode, and a value written in the port register is provided. Is transferred to all the bits of the conversion value setting register, and when the value of the port register is “1” corresponding to the output value of the conversion value setting register, the output of the digital / analog converter is set to the high level. When the value of the port register is “0”, the output of the digital / analog converter is set to the low potential, and the first digital value is output to the output terminal. The configuration is such that the digital value output terminal and the analog output terminal obtained by converting the second digital value into an analog value are also used.

In the input / output mode setting register of the D / A output port of the present invention, when the value is "0", the port is in the output mode, and when the value is "1", the port is in the input mode. It is a configuration to specify.

Further, when the D / A output port of the present invention is set in the output mode, the digital / analog converter may be set to the operation enabled state.

The digital / analog converter operation setting register for designating the operation of the digital / analog converter of the D / A output port according to the present invention is provided. A configuration for outputting to the analog converter operation setting register is also possible.

Further, the switching control is performed by the input / output mode setting register of the D / A output port of the present invention, and a selector for selecting the port register and the conversion value setting register may be provided.

[0015]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a D / A output port according to the first embodiment of the present invention.

According to the present invention, in a microcomputer field, a value written in a port register (hereinafter, referred to as a P register) is transferred to all 8 bits of a conversion value setting register (hereinafter, referred to as a DAC register) of a D / A converter. In addition, this embodiment is characterized in that a digital port and a D / A converter output terminal are shared according to the output of the DACS register 6.

As shown in the configuration of FIG. 1, by setting a port input / output mode setting register (hereinafter referred to as a PM register) 4 to an output mode, a D / A converter operation setting register (hereinafter referred to as a DACE register) 7 is set. The operation of the D / A converter is permitted without operating the
The terminal 11 enters the output permission state.

In this state, "0" or "0" is stored in the P register 5.
When "1" is written, the data is transferred to all 8 bits of the DACS register 6, and is supplied from the D / A converter output terminal 11 to VDD.
Level or GND level is output.

By providing the above-described configuration, binary output can be performed from the ANO terminal 11 with exactly the same operation as a normal port, and the dual use of the D / A converter output terminal and the digital port can be realized.

Next, the first embodiment of the present invention will be described more specifically.

The address decoders (2, 3) of the microcomputer having the D / A output port according to the first embodiment of the present invention are supplied with address signals from the address bus 12, and the address decoders (8, 9) , Address bus 14 supplies an address signal.

The address decoders (2, 3, 8, 9)
When the address signal supplied from the address bus indicates the address of a register connected to each address decoder, the signal becomes active.

The output of the address decoder 2 is connected to the PM register 4, the output of the address decoder 3 is connected to the P register 5, the output of the address decoder 8 is connected to the DACE register 7, and the output of the address decoder 9 is connected to the DACS register 6. I have.

The PM register 4 is connected to the internal bus 13 and is supplied with a data signal. PM register 4
Is a 1-bit register that specifies the output mode of the port when its value is "0" and specifies the input mode of the port when its value is "1".

In the present invention, in the output mode,
The D / A converter is set to the operation enabled state instead of the output buffer being set to the active state.

The DACE register 7 is connected to the internal bus 13, and a data signal is supplied from the internal bus 13. When the value of the DACE register 7 is “0”,
This is a 1-bit register that specifies the inhibition of the / A conversion operation and the permission of the D / A conversion operation when "1".

The output of the DACE register 7 is an OR circuit 16
Is connected to The output of the PM register 4 is connected to an OR circuit 16 via a NOT circuit 15.

Next, the DACS register 6 stores the internal bus 13
And a data signal is supplied from the internal bus 13. When a digital value to be output is written to the DACS register 6, an analog voltage value corresponding to the written value is output.

The P register 5 is connected to the internal bus 13 and is supplied with a data signal. The P register 5 writes a digital value to be output using a 1-bit register.

The output of the P register 5 is connected to all 8 bits of the DACS register 6, and the data written in the P register 5 is transferred to all 8 bits of the DACS register 6.

Output of OR circuit 16 and DACS register 6
Is connected to the selector 1, and the selector 1
Upon receiving the enable signal from the R circuit 16, the D / A converter is set in the operation permission state.

Further, the digital data of the DACS register 6 is taken in, and a circuit is selected so as to output an analog voltage corresponding to the digital data.

An ANO terminal 11 is an analog output terminal from which an analog signal converted from digital data is output via a selector 1 or a ladder R-2R resistor.

Next, the operation of the first embodiment of the present invention will be described.

First, an address signal is supplied to the address decoder 2 via the address bus 12.

When the supplied address signal indicates the address of the PM register 4, the address decoder 2
A signal is output to the register 4.

In response to the above signal, the PM register 4 takes in “0” for designating the output mode from the internal bus 13,
“0” is output to the OT circuit 15, and “1” is supplied to the OR circuit 16 via the NOT circuit 15.

Regardless of the value of the DACE register 7, OR
The output value “1” of the circuit 16 is supplied to the selector 1 and D /
A converter operation is enabled.

Next, an address signal is supplied to the address decoder 3 via the address bus 12.

The address decoder 3 outputs a signal to the P register 5 when the supplied address signal indicates the address of the P register 5.

In response to the above signal, the P register 5 takes in “0” or “1” from the internal bus 13 and
"0" or "1" is transferred to all 8 bits of the S register 6. The transferred “0” or “1” is the DACS
The signal is supplied from the register 6 to the selector 1, and the VDD level or the GND level is output from the ANO terminal 11 via the circuit selected by the selector 1. Next, a second embodiment of the present invention will be described with reference to the drawings.

According to the second embodiment of the present invention, instead of connecting the inverted output of the PM register 4 and the output of the DACE register 7 to the OR circuit 16 as shown in the first embodiment of the present invention, FIG. The data signal is transferred from the PM register 4 to the DACE register 7 via the NOT circuit 15 as shown in FIG. The DACE register 7 supplies the signal received from the PM register 4 to the selector 1 as an enable signal.

The other operations are the same as those described in the first embodiment of the present invention, and the detailed description is omitted.

Next, a third embodiment of the present invention will be described with reference to the drawings.

According to the third embodiment of the present invention, the output of the P register 5 described in the second embodiment of the present invention is
Instead of supplying all 8 bits of the S register 6, the P register 5 and the DAC register 6, which are controlled by the PM register 4 as shown in FIG.
Connect to

As shown in FIG. 7, which is a detailed diagram of the selector 17, when the signal supplied from the PM register 4 to the selector 17 is "0", the data signal from the P register is selected and supplied to the selector 1. .

When the signal supplied from the PM register 4 to the selector 17 is 1, the data signal from the DACS register 6 is selected and supplied to the selector 1.

Other operations are the same as those described in the first embodiment of the present invention, and a detailed description will be omitted.

[0049]

As described above, according to the present invention, the user can operate the digital port exactly the same as the ordinary digital port without operating the D / A converter. It can output two values of VDD level or GND level.

That is, the dual use of the digital port and the D / A converter output terminal can be realized. Since it is not shared by wired connection, there is an effect that the problem of deterioration in accuracy of the A / D converter can be solved.

Further, the problem that the user is forced to convert the register operation difference in order to perform the same operation as the digital port is also solved.

As a final effect, as described above, D / A
The converter output terminal can also be used as a digital port. Even when the user does not use all the built-in D / A converter output terminals, the user can effectively use the terminal as a digital port.

[Brief description of the drawings]

FIG. 1 is a block diagram of a D / A output port according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional D / A output port.

FIG. 3 is a block diagram of a protection buffer applied to a D / A output port.

FIG. 4 is a block diagram of a buffer applied to a D / A output port.

FIG. 5 is a block diagram of a D / A output port according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a D / A output port according to a third embodiment of the present invention.

FIG. 7 is a block diagram of a selector 17 of a D / A output port according to a third embodiment of the present invention.

FIG. 8 is a memory map showing a memory storage area of a port.

[Explanation of symbols]

 Reference Signs List 1 selector 2, 3, 8, 9 address decoder 4 PM register 5 P register 6 conversion value setting register of D / A converter 7 D / A converter operation setting register 11 terminal 12, 14 address bus 13 internal bus 15 NOT circuit 16 OR Circuit 17 Selector 20 Protection buffer 21 Buffer

Claims (7)

[Claims] A first register for holding a first digital value; an input / output mode setting register for setting an input / output mode of the port; A digital / analog converter for converting a value into an analog value; an output terminal of the digital / analog converter; and a conversion value setting register of the digital / analog converter. The value written in the port register is transferred to all bits of the conversion value setting register. If the value of the port register is "1" in accordance with the output value of the conversion value setting register, When the output of the analog / digital converter is set to the high potential and the value of the port register is "0", the output of the digital / analog converter is As low potential, by outputting the first digital value to said output terminal, said output terminal of said first digital value second
A D / A output port, which also serves as an analog output terminal for converting a digital value of the signal into an analog value. 2. The input / output mode setting register according to claim 1, wherein the port specifies the output mode when the value of the input / output mode setting register is “0”, and specifies the input mode when the value is “1”. / A output port. 3. The D / A output port according to claim 1, wherein said digital / analog converter is set in an operation permission state when said port is in an output mode. 4. The D / A output port according to claim 1, further comprising a digital / analog converter operation setting register for specifying an operation of said digital / analog converter. 5. The D / A output port according to claim 4, wherein an inverted signal of said input / output mode setting register is output to said digital / analog converter operation setting register. 6. The D / A output port according to claim 5, wherein switching control is performed by said input / output mode setting register, and said selector includes a selector for selecting said port register and said conversion value setting register. 7. The D / D converter according to claim 1, wherein said conversion value setting register has an 8-bit configuration.
A output port.